September 1983
Revised February 1999
MM74HC374 3-ST
A
T
E
Oct
a
l D-T
ype Fli
p
-Fl
o
p
1999 Fairchild Semiconductor Corporation
DS005336.prf
www.fairchildsemi.com
MM74HC374
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HC374 high speed Octal D-Type Flip-Flops uti-
lize advanced silicon-gate CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the setup and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns
s
Wide operating voltage range: 26V
s
Low input current: 1
A maximum
s
Low quiescent current: 80
A maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
=
Transition from LOW-to-HIGH
Z
=
High Impedance State
Q
0
=
The level of the output before steady state input conditions were
established
Order Number
Package Number
Package Description
MM74HC374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output
Clock
Data
Output
Control
L
H
H
L
L
L
L
L
X
Q
0
H
X
X
Z
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2
MM
74HC374
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package:
-
12 mW/
C from 65
C to 85
C.
DC Electrical Characteristics
Note 4: For a power supply of 5V
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
35 mA
DC V
CC
or GND Current, per pin (I
CC
)
70 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
2
6
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
1000
ns
V
CC
=
4.5V
500
ns
V
CC
=
6.0V
400
ns
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
V
IL
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
A
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
20
A
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
IN
=
V
IH
or V
IL
|I
OUT
|
6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
7.8 mA
6.0V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND
6.0V
0.1
1.0
1.0
A
Current
I
OZ
Maximum 3-STATE
V
IN
=
V
IH
, OC
=
V
IH
6.0V
0.5
5
10
A
Output Leakage
V
OUT
=
V
CC
or GND
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
6.0V
8.0
80
160
A
Supply Current
I
OUT
=
0
A
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4
MM
74HC374
AC Electrical Characteristics
V
CC
=
2.0
-
6.0V, C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Note 5: C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
C
L
=
50 pF
2.0V
6
5
4
MHz
Frequency
4.5V
30
24
20
MHz
6.0V
35
28
23
MHz
t
PHL
, t
PLH
Maximum Propagation
C
L
=
50 pF
2.0V
68
180
225
270
ns
Delay, Clock to Q
C
L
=
150 pF
2.0V
110
230
288
345
ns
C
L
=
50 pF
4.5V
22
36
45
48
ns
C
L
=
150 pF
4.5V
30
46
57
69
ns
C
L
=
50 pF
6.0V
20
31
39
46
ns
C
L
=
150 pF
6.0V
28
40
50
60
ns
t
PZH
, t
PZL
Maximum Output
R
L
=
1 k
Enable Time
C
L
=
50 pF
2.0V
50
150
189
225
ns
C
L
=
150 pF
2.0V
80
200
250
300
ns
C
L
=
50 pF
4.5V
21
30
37
45
ns
C
L
=
150 pF
4.5V
30
40
50
60
ns
C
L
=
50 pF
6.0V
19
26
31
39
ns
C
L
=
150 pF
6.0V
26
35
44
53
ns
t
PHZ
, t
PLZ
Maximum Output
R
L
=
1 k
2.0V
50
150
189
225
ns
Disable Time
C
L
=
50 pF
4.5V
21
30
37
45
ns
6.0V
19
26
31
39
ns
t
S
Minimum Setup Time
2.0V
50
60
75
ns
4.5V
9
13
15
ns
6.0V
9
11
13
ns
t
H
Minimum Hold Time
2.0V
5
30
5
ns
4.5V
5
5
5
ns
6.0V
5
5
5
ns
t
W
Minimum Pulse Width
2.0V
30
80
100
120
ns
4.5V
9
16
20
24
ns
6.0V
8
14
18
20
ns
t
THL
, t
TLH
Maximum Output Rise
C
L
=
50 pF
2.0V
25
60
75
90
ns
and Fall Time
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
t
r
, t
f
Maximum Input Rise and
2.0V
1000
1000
1000
ns
Fall Time, Clock
4.5V
500
500
500
ns
6.0V
400
400
400
ns
C
PD
Power Dissipation
(per flip-flop)
Capacitance (Note 5)
OC
=
V
CC
30
pF
OC
=
GND
50
pF
C
IN
Maximum Input Capacitance
5
10
10
10
pF
5
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MM74HC374
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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