December 1983
Revised February 1999
MM74HCT08 Q
u
ad
2-
Inpu
t A
ND Gate
1999 Fairchild Semiconductor Corporation
DS005754.prf
www.fairchildsemi.com
MM74HCT08
Quad 2-Input AND Gate
General Description
The MM74HCT08 is a logic function fabricated by using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS--low quiescent power and
wide power supply range. This device is input and output
characteristic and pinout compatible with standard 74LS
logic families. All inputs are protected from static discharge
damage by internal diodes to V
CC
and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL, LS pin-out and threshold compatible
s
Fast switching: t
PLH
, t
PHL
=
12 ns (typ)
s
Low power: 10
W at DC
s
High fan-out, 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
Order Number
Package Number
Package Description
MM74HCT08M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
MM74HCT08SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT08MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT08N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
MM
74
H
C
T08
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -- plastic "N" package
-
12
mW/
C from 65
C to 85
C.
DC Electrical Characteristics
V
CC
=
5V
10% (unless otherwise specified)
Note 4: This is measured per input with all other inputs held at V
CC
or ground.
Supply Voltage (V
CC
)
-
0.5 to
+
7.0V
DC Input Voltage (V
IN
)
-
1.5 to V
CC
+
1.5V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Clamp Diode Current (I
IK
, I
OK
)
20 mA
DC Output Current, per pin (I
OUT
)
25 mA
DC V
CC
or GND Current, per pin (I
CC
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
C
Min
Max
Units
Supply Voltage (V
CC
)
4.5
5.5
V
DC Input or Output Voltage
(V
IN
, V
OUT
)
0
V
CC
V
Operating Temperature Range (T
A
)
-
40
+
85
C
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Symbol
Parameter
Conditions
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
2.0
2.0
2.0
V
Input Voltage
V
IL
Maximum LOW Level
0.8
0.8
0.8
V
Input Voltage
V
OH
Minimum HIGH Level
V
IN
=
V
IH
or V
IL
Output Voltage
|I
OUT
|
=
20
A
V
CC
V
CC
-
0.1
V
CC
-
0.1
V
CC
-
0.1
V
|I
OUT
|
=
4.0 mA, V
CC
=
4.5V
4.2
3.98
3.84
3.7
V
|I
OUT
|
=
4.8 mA, V
CC
=
5.5V
5.2
4.98
4.84
4.7
V
V
OL
Maximum LOW Level
V
IN
=
V
IH
Voltage
|I
OUT
|
=
20
A
0
0.1
0.1
0.1
V
|I
OUT
|
=
4.0 mA, V
CC
=
4.5V
0.2
0.26
0.33
0.4
V
|I
OUT
|
=
4.8 mA, V
CC
=
5.5V
0.2
0.26
0.33
0.4
V
I
IN
Maximum Input
V
IN
=
V
CC
or GND, V
IH
or V
IL
0.1
1.0
1.0
A
Current
I
CC
Maximum Quiescent
V
IN
=
V
CC
or GND
2.0
20
40
A
Supply Current
I
OUT
=
0
A
V
IN
=
2.4V or 0.5V (Note 4)
1.2
1.4
1.5
mA
3
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MM74HCT08
AC Electrical Characteristics
V
CC
=
5.0V, t
r
=
t
f
=
6 ns, C
L
=
15 pF, T
A
=
25
C
AC Electrical Characteristics
V
CC
=
5.0V
10%, t
r
=
t
f
=
6 ns, C
L
=
50 pF
Note 5: C
PD
determines the no load dynamic power consumption. P
D
=
C
PD
V
CC
2 f
+
I
CC
V
CC
and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PLH
, t
PHL
Maximum Propagation Delay
9
15
ns
Symbol
Parameter
Conditions
T
A
=
25
C
T
A
=
-
40 to 85
C T
A
=
-
55 to 125
C
Units
Typ
Guaranteed Limits
t
PLH
, t
PHL
Maximum Propagation Delay
11
18
23
27
ns
t
THL
, t
TLH
Maximum Output Rise & Fall
Time
7
15
19
22
ns
C
PD
Power Dissipation Capaci-
tance
(Note 5)
38
pF
C
IN
Input Capacitance
5
10
10
10
pF
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4
MM
74
H
C
T08
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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MM74HCT08
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
M
M
74HCT08 Quad
2
-
I
nput AND
Gate
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
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