2005 Fairchild Semiconductor Corporation
DS500499
www.fairchildsemi.com
July 2001
Revised January 2005
NC7SZ74
T
i
nyL
ogic
UHS D-T
y
pe Fli
p
-
F
lop wit
h
Pr
eset and Clear
NC7SZ74
TinyLogic
UHS D-Type Flip-Flop with Preset and Clear
General Description
The NC7SZ74 is a single D-type CMOS Flip-Flop with pre-
set and clear from Fairchild's Ultra High Speed Series of
TinyLogic
in the space saving US8 package. The device
is fabricated with advanced CMOS technology to achieve
ultra high speed with high output drive while maintaining
low static power dissipation over a very broad V
CC
operat-
ing range. The device is specified to operate over the
1.65V to 5.5V V
CC
range. The inputs and output are high
impedance when V
CC
is 0V. Inputs tolerate voltages up to
7V independent of V
CC
operating voltage.
The signal level applied to the D input is transferred to the
Q output during the positive going transition of the CLK
pulse.
Features
s
Space saving US8 surface mount package
s
MicroPak
Pb-Free leadless package
s
Ultra High Speed; t
PD
2.6 ns Typ into 50 pF at 5V V
CC
s
High Output Drive;
24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V to 5.5V
s
Power down high impedance inputs/output
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
TinyLogic
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
is a trademark of Fairchild Semiconductor Corporation.
Product
Package Description
Supplied As
Order
Package
Code
Number
Number
Top Mark
NC7SZ74K8X MAB08A
SZ74
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7SZ74L8X MAC08A
N9
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
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2
NC7SZ74
Logic Symbol
IEEE/IEC
Pin Descriptions
Truth Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
Q
n
=
No change in data
Z
=
High Impedance
X
=
Immaterial
=
Rising Edge
=
Falling edge
Connection Diagrams
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
Pin Names
Description
D
Data Input
CK
Clock Pulse Input
CLR
Direct Clear Input
Q, Q
Flip-Flop Output
PR
Direct Preset Input
Inputs
Outputs
Function
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
Clear
H
L
X
X
H
L
Preset
L
L
X
X
H
H
--
H
H
L
L
H
--
H
H
H
H
L
--
H
H
X
Q
n
Q
n
No Change
3
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NC7SZ74
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings: are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
"Recommended Operating Conditions" table will define the conditions for
actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
IN
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
OUT
<
0V
-
50 mA
DC Output (I
OUT
) Source/Sink Current
50 mA
DC V
CC
/GND Current (I
CC
/I
GND
)
50 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Junction Temperature under Bias (T
J
)
150
C
Junction Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Power Dissipation (P
D
) @
+
85
C
250 mW
Power Supply
Operating (V
CC
)
1.65V to 5.5V
Data Retention
1.5V to 5.5V
Input Voltage (V
IN
)
0V to 5.5V
Output Voltage (V
OUT
)
Active State
0V to V
CC
3-STATE
0V to 5.5V
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
1.8V, 2.5V
0.2V
0 to 20 ns/V
V
CC
=
3.3V
0.3V
0 to 10 ns/V
V
CC
=
5.5V
0.5V
0 to 5 ns/V
Operating Temperature (T
A
)
-
40
C to
+
85
C
Thermal Resistance (
JA
)
250
C/W
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
V
IH
HIGH Level Control
1.65 to 1.95 0.75 V
CC
0.75 V
CC
V
Input Voltage
2.3 to 5.5
0.75 V
CC
0.7 V
CC
V
IL
LOW Level Control
1.65 to 1.95
0.25 V
CC
0.25 V
CC
V
Input Voltage
2.3 to 5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Control
1.65
1.55
1.65
1.55
V
V
IN
=
V
IH
I
OH
=
-
100
A
Output Voltage
2.3
2.2
2.3
2.2
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
1.65
1.29
1.52
1.29
I
OH
=
-
4 mA
2.3
1.9
2.15
1.9
I
OH
=
-
8 mA
3.0
2.4
2.8
2.4
I
OH
=
-
16 mA
3.0
2.3
2.68
2.3
I
OH
=
-
24 mA
4.5
3.8
4.2
3.8
I
OH
=
-
32 mA
V
OL
LOW Level Control
1.65
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
100
A
Output Voltage
2.3
0.1
0.1
3.0
0.1
0.1
4.5
0.1
0.1
1.65
0.08
0.24
0.24
I
OL
=
4
mA
2.3
0.10
0.3
0.3
I
OL
=
8
mA
3.0
0.15
0.4
0.4
I
OL
=
16 mA
3.0
0.22
0.55
0.55
I
OL
=
24 mA
4.5
0.22
0.55
0.55
I
OL
=
32 mA
I
IN
Input Leakage Current
0 to 5.5
0.1
1.0
A
0
V
IN
5.5V
I
OFF
Power Off Leakage Current
0.0
1.0
10
A
V
IN
or V
OUT
=
5.5V
I
CC
Quiescent Supply Current
1.65 to 5.5
1.0
10.0
A
V
IN
=
5.5V, GND
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4
NC7SZ74
AC Electrical Characteristics
Capacitance
(Note 3)
Note 3: T
A
=
+
25C, f
=
1MHz.
Note 4: C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
) (V
CC
) (f
IN
)
+
(I
CC
static).
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Figure
Number
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
1.8
0.15
75
75
MHz
Figures
1, 5
Frequency
2.5
0.2
150
150
C
L
=
15 pF
3.3
0.3
200
200
R
D
=
1 M
5.0
0.5
250
250
S
1
=
Open
3.3
0.3
175
175
C
L
=
50 pF
5.0
0.5
200
200
R
D
=
500
, S
1
=
Open
t
PLH
Propagation Delay
1.8
0.15
2.5
6.5
12.5
2.5
13.0
Figures
1, 3
t
PHL
CK to Q, Q
2.5
0.2
1.5
3.8
7.5
1.5
8.0
C
L
=
15 pF
3.3
0.3
1.0
2.8
6.5
1.0
7.0
ns
R
D
=
1 M
5.0
0.5
0.8
2.2
4.5
0.8
5.0
S
1
=
Open
3.3
0.3
1.0
3.4
7.0
1.0
7.5
C
L
=
50 pF
5.0
0.5
1.0
2.6
5.0
1.0
5.5
R
D
=
500
, S
1
=
Open
t
PLH
Propagation Delay
1.8
0.15
2.5
6.5
14.0
2.5
14.5
ns
Figures
1, 3
t
PHL
CLR, PR, to Q, Q
2.5
0.2
1.5
3.8
9.0
1.5
9.5
C
L
=
15 pF
3.3
0.3
1.0
2.8
6.5
1.0
7.0
R
D
=
1 M
5.0
0.5
0.8
2.2
5.0
0.8
5.5
S
1
=
Open
3.3
0.3
1.0
3.4
7.0
1.0
7.5
C
L
=
50 pF
5.0
0.5
1.0
2.6
5.0
1.0
5.5
R
D
=
500
, S
1
=
Open
t
S
Setup Time,
1.8
0.15
6.5
6.5
ns
Figures
1, 4
CK to D
2.5
0.2
3.5
3.5
C
L
=
15 pF
3.3
0.3
2.0
2.0
R
D
=
1 M
5.0
0.5
1.5
1.5
S
1
=
Open
3.3
0.3
2.0
2.0
C
L
=
50 pF
5.0
0.5
1.5
1.5
R
D
=
500
, S
1
=
Open
t
H
Hold Time,
1.8
0.15
0.5
0.5
ns
Figures
1, 4
CK to D
2.5
0.2
0.5
0.5
C
L
=
15 pF
3.3
0.3
0.5
0.5
R
D
=
1 M
5.0
0.5
0.5
0.5
S
1
=
Open
3.3
0.3
0.5
0.5
C
L
=
50 pF
5.0
0.5
0.5
0.5
R
D
=
500
, S
1
=
Open
t
W
Pulse Width,
1.8
0.15
6.0
6.0
ns
Figures
1, 5
CK, PR, CLR
2.5
0.2
4.0
4.0
C
L
=
15 pF
3.3
0.3
3.0
3.0
R
D
=
1 M
5.0
0.5
2.0
2.0
S
1
=
Open
3.3
0.3
3.0
3.0
CL
=
50 pF
5.0
0.5
2.0
2.0
R
D
=
500
, S
1
=
Open
t
REC
Recover Time
1.8
0.15
8.0
8.0
ns
Figures
1, 4
CLR, PR to CK
2.5
0.2
4.5
4.5
C
L
=
15 pF
3.3
0.3
3.0
3.0
R
D
=
1 M
5.0
0.5
3.0
3.0
S
1
=
Open
3.3
0.3
3.0
3.0
C
L
=
50 pF
5.0
0.5
3.0
3.0
R
D
=
500
, S
1
=
Open
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Input Capacitance
3
pF
V
CC
=
0V
C
OUT
Output Capacitance
4
pF
V
CC
=
0V
C
PD
Power Dissipation Capacitance (Note 4)
10
pF
V
CC
=
3.3V
12
V
CC
=
5.0V
5
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NC7SZ74
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
w
=
500 ns
FIGURE 1. AC Test Circuit
CP Input
=
AC Waveform; t
r
=
t
f
=
2.5 ns;
CP Input PRR
=
10 MHz; Duty Cycle
=
50%
D Input PRR
=
5MHz; Duty Cycle
=
50%
FIGURE 2. I
CCD
Test Circuit
FIGURE 3. AC Waveforms
FIGURE 4. AC Waveforms
FIGURE 5. AC Waveforms
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6
NC7SZ74
Tape and Reel Specification
TAPE FORMAT for US8
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
TAPE DIMENSIONS inches (millimeters)
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
K8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
L8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
7
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NC7SZ74
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
8 mm
7.0
0.059
0.512
0.795
2.165
0.331
+
0.059/
-
0.000
0.567
W1
+
0.078/
-
0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40
+
1.50/
-
0.00)
(14.40)
(W1
+
2.00/
-
1.00)
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8
NC7SZ74
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
9
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NC7SZ74
T
i
nyL
ogic
UHS D-T
y
pe Fli
p
-
F
lop wit
h
Pr
eset and Clear
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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