2003 Fairchild Semiconductor Corporation
DS500271
www.fairchildsemi.com
April 2000
Revised April 2003
NC7WZ38 T
i
nyLogi
c
UHS Dual
2-I
nput
NAND Gate
(
O
pe
n Dra
i
n
O
u
t
put
)
NC7WZ38
TinyLogic
UHS Dual 2-Input NAND Gate
(Open Drain Output)
General Description
The NC7WZ38 is a dual 2-Input NAND Gate with open
drain output stage from Fairchild's Ultra High Speed Series
of TinyLogic
. The device is fabricated with advanced
CMOS technology to achieve ultra high speed with high
output drive while maintaining low static power dissipation
over a very broad V
CC
operating range. The device is
specified to operate over the 1.65V to 5.5V V
CC
range. The
inputs and output are high impedance when V
CC
is 0V.
Inputs tolerate voltages up to 7V independent of V
CC
oper-
ating voltage. The open drain output stage will tolerate volt-
ages up to 7V independent of V
CC
when in the high
impedance state.
Features
s
Space saving US8 surface mount package
s
MicroPak
leadless package
s
Open Drain output stage for OR tied applications
s
Ultra High Speed; t
PD
2.2 ns Typ into 50 pF at 5V V
CC
s
High Output Sink Drive; 24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V to 5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/output
s
Overvoltage Tolerant inputs facilitate 5V to 3V
translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
TinyLogic
is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak
is a trademark of Fairchild Semiconductor Corporation.
Product
Package Description
Supplied As
Order
Package
Code
Number
Number
Top Mark
NC7WZ38K8X
MAB08A
WZ38
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ38L8X
(Preliminary)
MAC08A
U5
8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
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2
NC7W
Z38
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
Y
=
AB
H
=
HIGH Logic Level
L
=
LOW Logic Level
*H
=
HIGH Impedance output state (Open Drain)
Connection Diagrams
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
Pin Names
Description
A
n
, B
n
Inputs
Y
n
Output
Inputs
Output
A
B
Y
L
L
*H
L
H
*H
H
L
*H
H
H
L
3
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NC7WZ38
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
7V
DC Input Voltage (V
IN
)
-
0.5V to
+
7V
DC Output Voltage (V
OUT
)
-
0.5V to
+
7V
DC Input Diode Current (I
IK
)
@V
IN
<
-
0.5V
-
50 mA
DC Output Diode Current (I
OK
)
@V
OUT
<
-
0.5V
-
50 mA
DC Output Current (I
OUT
)
+
50 mA
DC V
CC
/GND Current (I
CC
/I
GND
)
100 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Junction Temperature under Bias (T
J
)
150
C
Junction Lead Temperature (T
L
);
(Soldering, 10 seconds)
260
C
Power Dissipation (P
D
) @
+
85
C
250 mW
Supply Voltage Operating (V
CC
)
1.65V to 5.5V
Supply Voltage Data Retention (V
CC
)
1.5V to 5.5V
Input Voltage (V
IN
)
0V to 5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
1.8V
0.15V, 2.5V
0.2V
0 ns/V to 20 ns/V
V
CC
=
3.3V
0.3V
0 ns/V to 10 ns/V
V
CC
=
5.0V
0.5V
0 ns/V to 5 ns/V
Thermal Resistance (
JA
)
250
C/W
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
V
IH
HIGH Level
1.65 to 1.95 0.75 V
CC
0.75 V
CC
V
Input Voltage
2.3 to 5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level
1.65 to 1.95
0.25 V
CC
0.25 V
CC
V
Input Voltage
2.3 to 5.5
0.3 V
CC
0.3 V
CC
I
LKG
HIGH Level
5.5
5
10
A
V
IN
=
V
IL
Output Leakage
V
OUT
=
V
CC
or GND
V
OL
LOW Level
1.65
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
100
A
Output Voltage
2.3
0.0
0.1
0.1
3.0
0.0
0.1
0.1
4.5
0.0
0.1
0.1
1.65
0.08
0.24
0.24
V
I
OL
=
4 mA
2.3
0.10
0.3
0.3
I
OL
=
8 mA
3.0
0.15
0.4
0.4
I
OL
=
16 mA
3.0
0.22
0.55
0.55
I
OL
=
24 mA
4.5
0.22
0.55
0.55
I
OL
=
32 mA
I
IN
Input Leakage Current
5.5
0.1
1
A
V
IN
=
5.5V, GND
I
OFF
Power Off Leakage Current
0.0
1
10
A
V
IN
or V
OUT
=
5.5V
I
CC
Quiescent Supply Current
1.65 to 5.5
1
10
A
V
IN
=
5.5V, GND
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4
NC7W
Z38
AC Electrical Characteristics
Note 3: C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
) (V
CC
) (f
IN
)
+
(I
CC
static).
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
w
=
500 ns
FIGURE 1. AC Test Circuit
Input
=
AC Waveform; t
r
=
t
f
=
1.8 ns
PRR
=
10 MHz; Duty Cycle
=
50%
FIGURE 2. I
CCD
Test Circuit
FIGURE 3. AC Waveforms
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Figure
(V)
Min
Typ
Max
Min
Max
Number
t
PZL
Propagation Delay
1.8
0.15
2.0
5.2
9.2
2.0
9.6
ns
C
L
=
50 pF
2.5
0.2
1.5
3.5
5.7
1.5
6.1
RU
=
500
Figures
1, 3
3.3
0.3
1.0
2.8
4.1
1.0
4.5
RD
=
500
5.0
0.5
0.5
2.2
3.4
0.5
3.6
V
I
=
2
V
CC
t
PLZ
Propagation Delay
1.8
0.15
2.0
4.6
9.2
2.0
9.6
ns
C
L
=
50 pF
2.5
0.2
1.5
3.2
5.7
1.5
6.1
RU
=
500
Figures
1, 3
3.3
0.3
1.0
2.4
4.1
1.0
4.5
RD
=
500
5.0
0.5
0.5
1.6
3.4
0.5
3.6
V
I
=
2
V
CC
C
IN
Input Capacitance
0
2.5
pF
C
OUT
Output Capacitance
0
4.2
pF
C
PD
Power Dissipation
3.3
7
pF
(Note 3)
Figure 2
Capacitance
5.0
9
5
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NC7WZ38
Tape and Reel Specification
TAPE FORMAT for US8
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
TAPE DIMENSIONS inches (millimeters)
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
K8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
L8X
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
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6
NC7W
Z38
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
8 mm
7.0
0.059
0.512
0.795
2.165
0.331
+
0.059/
-
0.000
0.567
W1
+
0.078/
-
0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40
+
1.50/
-
0.00)
(14.40)
(W1
+
2.00/
-
1.00)
7
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NC7WZ38
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
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8
NC7W
Z38
T
i
ny
Logic
U
HS Dual 2-
Input
NAND
Gat
e
(Open D
r
ain
Outpu
t
)
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
(Preliminary)
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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