June1996
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
___________________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol Parameter
NDC632P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
Gate-Source Voltage - Continuous
-8
V
I
D
Drain Current - Continuous
-2.7
A
- Pulsed
-10
P
D
Maximum Power Dissipation
(Note 1a)
1.6
W
(Note 1b)
1
(Note 1c)
0.8
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
30
C/W
NDC632P Rev. B1
3
5
6
4
1
2
-2.7A, -20V. R
DS(ON)
= 0.14
@ V
GS
= -4.5V
R
DS(ON)
= 0.2
@ V
GS
= -2.7V.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
These P-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits
where fast high-side switching, and low in-line power
loss are needed in a very small outline surface
mount package.
SuperSOT
TM
-6
1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-20
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-1
A
T
J
= 55
o
C
-10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 8 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-0.4
-0.7
-1
V
T
J
= 125
o
C
-0.3
-0.5
-0.8
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= - 2.7 A
0.1
0.14
T
J
= 125
o
C
0.145
0.28
V
GS
= -2.7 V, I
D
= - 2.2 A
0.152
0.2
I
D(on)
On-State Drain Current
V
GS
= -4.5 V, V
DS
= -5 V
-10
A
V
GS
= -2.7 V, V
DS
= -5 V
-4
g
FS
Forward Transconductance
V
DS
= -10 V, I
D
= - 2.7 A
6
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
550
pF
C
oss
Output Capacitance
260
pF
C
rss
Reverse Transfer Capacitance
75
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -5 V, I
D
= -1 A,
V
GEN
= -4.5 V, R
GEN
= 6
10
20
ns
t
r
Turn - On Rise Time
40
60
ns
t
D(off)
Turn - Off Delay Time
25
40
ns
t
f
Turn - Off Fall Time
17
30
ns
Q
g
Total Gate Charge
V
DS
= -5 V,
I
D
= -2.7 A, V
GS
= -4.5 V
8.7
15
nC
Q
gs
Gate-Source Charge
1.7
nC
Q
gd
Gate-Drain Charge
1.8
nC
NDC632P Rev. B1
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
Continuous Source Diode Current
-1.3
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-0.77
-1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 125
o
C/W when mounted on a 0.01 in
2
pad of 2oz copper.
c. 156
o
C/W when mounted on a 0.003 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDC632P Rev. B1
1a
1b
1c
NDC632P Rev. B1
-5
-4
-3
-2
-1
0
-15
-12
-9
-6
-3
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
-3.0
DS
D
V =-5V
GS
-3.5
-2.5
-2.0
-2.7
-4.0
-4.5
-15
-12
-9
-6
-3
0
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V =-2.5V
GS
D
-2.7
R , NORMALIZED
DS(ON)
-3.0
-5.0
-4.5
-4.0
-3.5
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
Typical Electrical Characteristics
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = -4.5V
GS
I = -2.7A
D
R , NORMALIZED
DS(ON)
-15
-12
-9
-6
-3
0
0
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V =-4.5 V
GS
T = 125C
J
25C
-55C
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
-5
-4
-3
-2
-1
0
-15
-12
-9
-6
-3
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25C
125C
V =- 5V
DS
GS
D
T = -55C
J
-50
-25
0
2 5
5 0
7 5
100
125
150
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = -250A
D
V = V
DS
GS
V , NORMALIZED
th
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature
.
NDC632P Rev. B1
-50
-25
0
2 5
5 0
7 5
100
125
150
0.9
0.95
1
1.05
1.1
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250A
D
BV , NORMALIZED
DSS
J
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.0001
0.001
0.01
0.1
1
5
15
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V =0V
GS
SD
S
Figure 7. Breakdown Voltage Variation with
Temperature
.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
Typical Electrical Characteristics
(continued)
0
2
4
6
8
10
0
1
2
3
4
5
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -2.7A
D
V = -5V
DS
-10V
-15V
0.1
0.2
0.5
1
5
1 0
1 5 20
50
1 0 0
2 0 0
3 0 0
5 0 0
1 0 0 0
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
f = 1 MHz
V = 0V
GS
C
oss
C
iss
C
rss
D
S
-V
DD
R
L
V
OUT
V
GS
DUT
V
IN
R
GEN
G
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
o n
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics.
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms.
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