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February 1997
NDH833N
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
___________________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise note
Symbol
Parameter
NDH833N
Units
V
DSS
Drain-Source Voltage
20
V
V
GSS
Gate-Source Voltage
8
V
I
D
Drain Current - Continuous
(Note 1a)
7.1
A
- Pulsed
24
P
D
Maximum Power Dissipation
(Note 1a)
1.8
W
(Note 1b)
1
(Note 1c)
0.9
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
70
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
20
C/W
NDH833N Rev. C
SuperSOT
TM
-8 N-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
battery powered circuits or portable electronics where fast
switching, low in-line power loss, and resistance to transients
are needed.
7.1 A, 20 V. R
DS(ON)
= 0.020
@ V
GS
= 4.5 V
R
DS(ON)
= 0.025
@ V
GS
= 2.7 V.
Proprietary SuperSOT
TM
-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
1
5
6
7
8
4
3
2
1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
20
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 16 V, V
GS
= 0 V
1
A
T
J
= 55C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 8 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -8 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
0.4
0.62
1
V
T
J
= 125C
0.3
0.4
0.8
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 7.1 A
0.015
0.02
T
J
= 125C
0.022
0.036
V
GS
= 2.7 V, I
D
= 6.7 A
0.018
0.025
I
D(on)
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
24
A
g
FS
Forward Transconductance
V
DS
= 5 V, I
D
= 7.1 A
35
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
1540
pF
C
oss
Output Capacitance
750
pF
C
rss
Reverse Transfer Capacitance
265
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 5 V, I
D
= 1 A,
V
GEN
= 4.5 V, R
GEN
= 6
12
20
ns
t
r
Turn - On Rise Time
35
70
ns
t
D(off)
Turn - Off Delay Time
110
200
ns
t
f
Turn - Off Fall Time
60
120
ns
Q
g
Total Gate Charge
V
DS
= 10 V,
I
D
= 7.1 A, V
GS
= 10 V
97
140
nC
Q
gs
Gate-Source Charge
8
nC
Q
gd
Gate-Drain Charge
33
nC
NDH833N Rev. C
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
1.5
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.5 A
(Note 2)
0.65
1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 70
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.026 in
2
pad of 2oz copper.
c. 135
o
C/W when mounted on a 0.005 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDH833N Rev. C
1a
1b
1c
NDH833N Rev. C
0
5
10
15
20
25
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 2.0V
GS
D
R , NORMALIZED
DS(on)
3.5
2.7
3.0
2.5
4.5
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
Typical Electrical Characteristics
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 4.5V
GS
I = 7.1A
D
R , NORMALIZED
DS(ON)
0
5
1 0
1 5
2 0
2 5
0
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125C
J
25C
D
V = 4.5 V
GS
-55C
R , NORMALIZED
DS(on)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
0
0.5
1
1.5
2
2.5
0
5
1 0
1 5
2 0
2 5
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25C
125C
V = 5.0V
DS
GS
D
T =-55C
J
-50
-25
0
2 5
5 0
7 5
100
125
150
0.2
0.4
0.6
0.8
1
1.2
1.4
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
J
I = 250A
D
V = V
DS
GS
V , NORMALIZED
th
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature.
0
0.5
1
1.5
2
0
5
10
15
20
25
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
2.7
V =4.5V
GS
DS
D
2.5
3.5
2.0
1.5
NDH833N Rev. C
-50
-25
0
25
50
75
100
125
150
0.92
0.96
1
1.04
1.08
1.12
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = 250A
D
BV , NORMALIZED
DSS
J
0
0.2
0.4
0.6
0.8
1
1.2
0.0001
0.001
0.01
0.1
1
5
10
20
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature.
Typical Electrical Characteristics
(continued)
0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
1 0 0
0
1
2
3
4
5
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 7.1A
D
15V
V =10V
DS
0 .1
0 .2
0 .5
1
2
5
1 0
2 0
1 0 0
2 0 0
3 0 0
5 0 0
1 0 0 0
2 0 0 0
3 0 0 0
5 0 0 0
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
on
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
NDH833N Rev. C
0
5
10
15
20
25
0
10
20
30
40
50
60
70
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55C
J
25C
D
FS
V = 5.0V
DS
125C
Figure 16. Maximum Safe Operating Area.
Typical Electrical and Thermal Characteristics
(continued)
0
0.2
0.4
0.6
0.8
1
4
5
6
7
8
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = 4.5V
A
o
G S
D
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1 b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
A
o
0.1
0.2
0.5
1
2
5
1 0
2 0
3 0
0.01
0.03
0.1
0.3
1
3
1 0
2 0
4 0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
DC
1s
10ms
100ms
10s
1ms
RDS(ON) LIMIT
100us
V = 4.5V
SINGLE PULSE
R = See Note 1c
T = 25C
GS
A
J A
Figure 14. SuperSOT
TM
-8 Maximum Steady-State
Power Dissipation versus Copper Mounting Pad
Area.
Figure 15. Maximum Steady-State Drain Current
versus Copper Mounting Pad Area.
0.0001
0.001
0.01
0.1
1
1 0
1 0 0
3 0 0
0.01
0.02
0.03
0.05
0.1
0.2
0.3
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1
2
R (t) = r(t) * R
R = See Note 1c
JA
JA
JA
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
r(t), NORMALIZED EFFECTIVE
Figure 17. Transient Thermal Response Curve
.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
Figure 13. Transconductance Variation with Drain
Current and Temperature.
SSOT-8 Packaging
Configuration: Figure 1.0
Components
Lead er Tape
500mm mi nimum or
62 empty poc kets
Traile r Tape
300mm mi nimum or
38 empty pockets
SSOT-8 Tape Leader and Trailer
Configuration: Figur e 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SSOT-8 Packaging Information
Standard
(no
f l ow c ode )
D84Z
Packaging type
Reel Size
TNR
13" D ia
TNR
7" Dia
Qty per Reel/Tube/Bag
3,000
500
Box Dimension (mm)
343x64x343
184x187x47
Max qty per Box
6,000
1,000
Weight per unit (gm)
0.0416
0.0416
Weight per Reel (kg)
0.5615
0.0980
184mm x 187mm x 47mm
Pizza Box fo r D84Z Option
F63TNR
Label
F63TNR Labe l
F63TNR Labe l sa mpl e
343mm x 342mm x 64mm
Intermediate bo x fo r Standar d
and L 99Z Opti ons
F63TNR
Label
LOT: CBVK741B019
FSID: FDR835N
D/C1: D9842 QTY1:
SPEC REV:
SPEC:
QTY: 3000
D/C2:
QTY2:
CPN:
N/F: F (F63TNR)3
SSOT-8 Unit Orientation
F852
831N
F852
831N
F852
831N
F852
831N
F852
831N
Pin 1
F63TNR Labe l
Anti static Cover Tape
Customized La bel
Static Dissi pat ive
Emboss ed Carrier Tape
Packaging Description:
SSOT-8 parts are shipped in tape. The carrier tape is
made from a di ssipat ive (carbo n filled) po ly carbon ate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film ,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped w ith
3,000 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 unit s per 7" or
177cm diameter reel. This and some other options are
further described in the Packagin g Information table.
These full reels are in di vidu ally barcod e labeled and
placed inside a standard intermediate box (ill ustrated in
figure 1.0) made of recyclable corrugated brow n paper.
One box contains two reels maximum. And t hese boxes
are placed ins ide a barcode labeled shipp ing bo x whic h
comes in di fferent sizes depend in g on t he nu mber of parts
shippe d.
SuperSOT
TM
-8 Tape and Reel Data and Package Dimensions
August 1999, Rev. C
1998 Fairchild Semiconductor Corporation
Dimensions are in millimeter
Pkg type
A0
B0
W
D0
D1
E1
E2
F
P1
P0
K0
T
Wc
Tc
SSOT-8
(12mm)
4.47
+/-0.10
5.00
+/-0.10
12.0
+/-0.3
1.55
+/-0.05
1.50
+/-0.10
1.75
+/-0.10
10.25
mi n
5.50
+/-0.05
8.0
+/-0.1
4.0
+/-0.1
1.37
+/-0.10
0.280
+/-0.150
9.5
+/-0.025
0.06
+/-0.02
P1
A0
D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
12mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
5.906
150
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
12mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes : A0, B0, and K0 di mens ions are deter mined with r espec t to t he EIA/Jedec RS-481
rotati ona l and lateral movement requi remen ts (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Si de or Front Sectional View)
Component Rotation
User Direction of Feed
SSOT-8 Embossed Carrier Tape
Configuration: Figur e 3.0
SSOT-8 Reel Configuration: Figur e 4.0
SuperSOT
TM
-8 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. C
SuperSOT
TM
-8 (FS PKG Code 34, 35)
1 : 1
Scale 1:1 on letter size paper
Di mensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0416
SuperSOT
TM
-8 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
TRADEMARKS
ACExTM
CoolFETTM
CROSSVOLTTM
E
2
CMOS
TM
FACTTM
FACT Quiet SeriesTM
FAST
FASTrTM
GTOTM
HiSeCTM
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TinyLogicTM
UHCTM
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ISOPLANARTM
MICROWIRETM
POPTM
PowerTrenchTM
QFETTM
QSTM
Quiet SeriesTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
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