February 1997
NDH8504P
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
___________________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol Parameter
NDH8504P
Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage 20 V
I
D
Drain Current - Continuous
(Note 1)
-2.7 A
- Pulsed -8
P
D
Maximum Power Dissipation
(Note 1)
0.8 W
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1)
156 C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
40 C/W
NDH8504P Rev.C
SuperSOT
TM
-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
-2.7 A, -30 V. R
DS(ON)
= 0.07
@ V
GS
= -10 V
R
DS(ON)
= 0.115
@ V
GS
= -4.5 V.
Proprietary SuperSOT
TM
-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
1
5
6
7
8
4
3
2
1997 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-30
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -24V, V
GS
= 0 V
-1
A
T
J
= 55C
-10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= - 250 A
-1
-1.6
-3
V
T
J
= 125C
-0.8
-1.2
-2.4
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -10 V, I
D
= -2.7 A
0.062
0.07
T
J
= 125C
0.088
0.125
V
GS
= -4.5 V, I
D
= -2.1 A
0.102
0.115
I
D(on)
On-State Drain Current
V
GS
= -10 V, V
DS
= -5 V
-8
A
V
GS
= -4.5 V, V
DS
= -5 V
-3
g
FS
Forward Transconductance
V
DS
= -10 V, I
D
= -2.7 A
5.5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
560
pF
C
oss
Output Capacitance
340
pF
C
rss
Reverse Transfer Capacitance
130
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -10 V, I
D
= -1 A,
V
GS
= -10 V, R
GEN
= 6
13
25
ns
t
r
Turn - On Rise Time
16
30
ns
t
D(off)
Turn - Off Delay Time
35
70
ns
t
f
Turn - Off Fall Time
40
80
ns
Q
g
Total Gate Charge
V
DS
= -10 V,
I
D
= -2.7 A, V
GS
= -10 V
19
27
nC
Q
gs
Gate-Source Charge
3.8
nC
Q
gd
Gate-Drain Charge
4.7
nC
NDH8504P Rev.C
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
-0.67
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.67 A
(Note 2)
-0.74
-1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
156
o
C/W when mounted on a 0.0025 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDH8504P Rev.C
NDH8504P Rev.C
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
-3
-2.5
-2
-1.5
-1
-0.5
0
-10
-8
-6
-4
-2
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
DS
D
-3.5
-4.5
-3.0
-5.0
-6.0
V = -10V
GS
-4.0
-10
-8
-6
-4
-2
0
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
-7.0
-4.5
-4.0
-5.0
-6.0
-10
V = -3.5V
GS
-5
-4
-3
-2
-1
-10
-8
-6
-4
-2
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -10V
D S
G S
D
T = -55C
J
125C
25C
- 5 0
- 2 5
0
2 5
5 0
7 5
1 0 0
1 2 5
1 5 0
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
J
V , NORMALIZED
GS(th)
I = -250A
D
V = V
G S
DS
-50
-25
0
2 5
5 0
7 5
1 0 0
1 2 5
1 5 0
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
R , NORMALIZED
DS(ON)
V = -10V
GS
I = -2.7A
D
-10
-8
-6
-4
-2
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -10V
GS
T = 125C
J
25C
-55C
NDH8504P Rev.C
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
Typical Electrical Characteristics
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms.
-50
-25
0
25
50
75
1 0 0
1 2 5
1 5 0
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250A
D
J
BV , NORMALIZED
DSS
0 .1
0 .2
0 .5
1
2
5
1 0
2 0
3 0
5 0
1 0 0
2 0 0
4 0 0
6 0 0
1 0 0 0
1 5 0 0
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
0
4
8
1 2
1 6
2 0
0
2
4
6
8
1 0
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
V =-5V
DS
I = -2.7A
-10V
g
GS
D
-15V
0.2
0.4
0.6
0.8
1
1.2
0 . 0 0 0 1
0 . 0 0 1
0 . 0 1
0.1
0.5
1
3
1 0
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
D
S
-V
DD
R
L
V
O U T
V
GS
D U T
V
IN
R
GEN
G
1 0 %
5 0 %
9 0 %
1 0 %
9 0 %
9 0 %
5 0 %
V
IN
V
OUT
o n
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
1 0 %
PULSE WIDTH
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