March 1996
NDS352P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
____________________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDS352P
Units
V
DSS
Drain-Source Voltage
-20
V
V
GSS
Gate-Source Voltage - Continuous
12
V
I
D
Maximum Drain Current - Continuous
(Note 1a)
0.85
A
- Pulsed
10
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
75
C/W
NDS352P Rev. F1
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-0.85A, -20V. R
DS(ON)
= 0.5
@ V
GS
= -4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
D
S
G
1997 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-20
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -16 V, V
GS
= 0 V
-5
A
T
J
=125C
-20
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 12 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -12 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-0.8
-1.6
-2.5
V
T
J
=125C
-0.5
-1.3
-2.2
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= -0.85 A
0.46
0.5
T
J
=125C
0.59
0.7
V
GS
= -10 V, I
D
= -1 A
0.35
I
D(ON)
On-State Drain Current
V
GS
= -4.5 V, V
DS
= -5 V
-2
A
g
FS
Forward Transconductance
V
DS
= -5 V, I
D
= -0.85 A
1.5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
125
pF
C
oss
Output Capacitance
140
pF
C
rss
Reverse Transfer Capacitance
45
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
d(on)
Turn - On Delay Time
V
DD
= -10 V, I
D
= -1 A,
V
GS
= -10 V, R
GEN
= 50
8
15
ns
t
r
Turn - On Rise Time
19
30
ns
t
d(off)
Turn - Off Delay Time
64
90
ns
t
f
Turn - Off Fall Time
61
90
ns
Q
g
Total Gate Charge
V
DS
= -10 V, I
D
= -0.85 A,
V
GS
= -5 V
2.2
4
nC
Q
gs
Gate-Source Charge
1
nC
Q
gd
Gate-Drain Charge
2
nC
NDS352P Rev. F1
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
-0.6
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
-5
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.85 A
(Note 2)
-0.92
-1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz cpper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS352P Rev. F1
1 a
1b
NDS352P Rev. F1
-4
-3
-2
-1
0
-5
-4
-3
-2
-1
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V = -10V
GS
DS
D
-3.0
-3.5
-7.0
-5.0
-4.5
-4.0
-5.5
-5
-4
-3
-2
-1
0
0.6
0.8
1
1.2
1.4
1.6
1.8
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = -3.5 V
GS
D
R , NORMALIZED
DS(on)
-4.0
-10
-5.5
-5.0
-4.5
-7.0
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
Typical Electrical Characteristics
-50
-25
0
25
50
75
100
125
150
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE (OHMS)
J
V = -4.5V
GS
I = -0.85A
D
R , NORMALIZED
DS(ON)
-4
-3
-2
-1
0
0.6
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
D
R
A
I
N
-
S
O
U
R
C
E
O
N
-
R
E
S
I
S
T
A
N
C
E
D
R
,
N
O
R
M
A
L
I
Z
E
D
D
S
(
o
n
)
V = -4.5V
GS
T = 125C
J
25C
-55C
Figure 3. On-Resistance Variation
with Temperature
Figure 4. On-Resistance Variation
with Drain Current and Temperature
-6
-5
-4
-3
-2
-1
-5
-4
-3
-2
-1
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25
125
V = -10V
DS
GS
D
T = -55C
J
-50
-25
0
25
50
75
100
125
150
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE (V)
J
I = -250A
D
V = V
DS
GS
V , NORMALIZED
th
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation
with Temperature
NDS352P Rev. F1
-50
-25
0
25
50
7 5
100
125
150
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
I = -250A
D
BV , NORMALIZED
DSS
J
0
0.4
0.8
1.2
1.6
2
2.4
0.01
0.1
0.5
1
5
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0V
GS
SD
S
Figure 7. Breakdown Voltage Variation with
Temperature
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
Typical Electrical Characteristics
(continued)
0
1
2
3
4
-10
-8
-6
-4
-2
0
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -850m A
D
V = -5V
DS
-10
0.1
0.2
0.5
1
2
5
1 0
20
2 0
3 0
5 0
1 0 0
2 0 0
3 0 0
5 0 0
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
10%
50%
90%
10%
90%
90%
50%
V
IN
V
OUT
o n
off
d(off)
f
r
d(on)
t
t
t
t
t
t
INVERTED
10%
PULSE WIDTH
Figure 9. Capacitance Characteristics
Figure 10. Gate Charge Characteristics
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
PDF 
ZIP