March 1996
NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
_______________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDS355N
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source Voltage - Continuous
20
V
I
D
Drain Current - Continuous
(Note 1a)
1.6
A
- Pulsed
10
P
D
Maximum Power Dissipation
(Note 1a)
0.5
W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
C/W
R
JC
Thermal Resistance, Junction-to -Case
(Note 1)
75
C/W
NDS355N Rev. D1
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMICA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
1.6A, 30V. R
DS(ON)
= 0.125
@ V
GS
= 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
D
S
G
1997 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
30
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
A
T
J
=125C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 12 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -12 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
1
1.6
2
V
T
J
=125C
0.5
1.3
1.5
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 1.6 A
0.125
T
J
=125C
0.25
V
GS
= 10 V, I
D
= 1.9 A
0.085
I
D(ON)
On-State Drain Current
V
GS
= 4.5 V, V
DS
= 5 V
6
A
g
FS
Forward Transconductance
V
DS
= 5 V, I
D
= 1.6 A
3.5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
245
pF
C
oss
Output Capacitance
130
pF
C
rss
Reverse Transfer Capacitance
20
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
15
30
ns
t
r
Turn - On Rise Time
14
30
ns
t
D(off)
Turn - Off Delay Time
12
25
ns
t
f
Turn - Off Fall Time
4
10
ns
Q
g
Total Gate Charge
V
DS
= 10 V, I
D
= 1.6 A,
V
GS
= 5 V
3.5
5
nC
Q
gs
Gate-Source Charge
1
nC
Q
gd
Gate-Drain Charge
2
nC
NDS355N Rev. D1
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Source Current
0.6
A
I
SM
Maximum Pulse Source Current
(Note 2)
6
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.6 A
0.8
1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed by
design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz cpper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS355N Rev. D1
1 a
1b
NDS355N Rev. D1
Typical Electrical Characteristics
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation with Gate Voltage
and Drain Current
0
1
2
3
4
0
3
6
9
12
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
6.0 5.0
4.5
4.0
3.5
3.0
V =10V
GS
DS
D
0
3
6
9
12
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
6.0
5.0
4.5
4.0
10
V =3.5V
GS
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V =4.5V
GS
I = 1.6A
D
R , NORMALIZED
DS(ON)
-50
-25
0
25
50
75
100
125
150
0.6
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE (V)
J
V , NORMALIZED
th
V = V
DS
GS
I = 250A
D
0
2
4
6
8
10
12
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125C
J
25C
-55C
D
V = 4.5V
GS
R , NORMALIZED
DS(on)
Figure 3. On-Resistance Variation
with Temperature
Figure 4. On-Resistance Variation with Drain
Current and Temperature
Figure 5. Transfer Characteristics
Figure 6. Gate Threshold Variation with
Temperature
1
2
3
4
5
6
0
2
4
6
8
1 0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = 10V
DS
GS
D
T = -55C
J
25C
125C
NDS355N Rev. D1
-50
-25
0
25
50
75
100
125
150
175
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
I = 250A
D
BV , NORMALIZED
DSS
J
0.2
0.4
0.6
0.8
1
1.2
1.4
0.001
0.01
0.1
1
10
20
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
V = 0V
GS
SD
S
T = 125C
J
25C
-55C
0
1
2
3
4
5
6
7
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
V = 5V
DS
g
GS
10
I = 1.6A
D
15
0.1
0.2
0.5
1
2
5
10
30
3 0
5 0
1 0 0
2 0 0
3 0 0
5 0 0
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
C oss
C rss
f = 1 MHz
V = 0V
GS
G
D
S
V
DD
R
L
V
V
IN
OUT
V
GS
DUT
R
GEN
10%
50%
90%
10%
90%
90%
50%
Input, Vin
Output, Vout
t
on
t
off
t
d(off)
t
f
t
r
t
d(on)
Inverted
10%
Pulse Width
Figure 7. Breakdown Voltage Variation
with Temperature
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
Figure 9. Capacitance Characteristics
Figure 10. Gate Charge Characteristics
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
Typical Electrical Characteristics
(continued)
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