June 1999
NDS9407
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
_______________________________________________________________________________________
Absolute Maximum Ratings
T
A
= 25C unless otherwise noted
Symbol
Parameter
NDS9407
Units
V
DSS
Drain-Source Voltage
-60
V
V
GSS
Gate-Source Voltage
20
V
I
D
Drain Current - Continuous T
A
= 25C
(Note 1a)
3.0
A
- Continuous T
A
= 70C
2.4
- Pulsed T
A
= 25C
12
P
D
Maximum Power Dissipation
(Note 1a)
2.5
W
(Note 1b)
1.2
(Note 1c)
1
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
50
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
25
C/W
NDS9407.SAM Rev. B
-3.0A, -60V. R
DS(ON)
= 0.15
@ V
GS
=-10V
R
DS(ON)
= 0.24
@ V
GS
=-4.5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
5
6
8
3
1
7
4
2
These
P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications
such as notebook computer power management and other
battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
1999 Fairchild Semiconductor Corporation
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= -250 A
-60
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -48 V, V
GS
= 0 V
-1
A
T
A
= 55C
-10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 A
-1
-2.3
V
T
A
= 125C
-0.8
-1.8
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -10 V, I
D
= -3.0 A
0.08
0.15
T
A
= 125C
0.13
0.3
V
GS
= -4.5 V, I
D
= -1.6 A
0.135
0.24
T
A
= 125C
0.2
0.48
I
D(on)
On-State Drain Current
V
GS
= -10 V, V
DS
= -5 V
-12
A
g
FS
Forward Transconductance
V
DS
= -15 V, I
D
= -3.0 A
6.8
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= -30 V, V
GS
= 0 V,
f = 1.0 MHz
1400
pF
C
oss
Output Capacitance
290
pF
C
rss
Reverse Transfer Capacitance
80
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -25 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
12
30
ns
t
r
Turn - On Rise Time
12
40
ns
t
D(off)
Turn - Off Delay Time
55
100
ns
t
f
Turn - Off Fall Time
22
45
ns
Q
g
Total Gate Charge
V
DS
= -30 V,
I
D
= -3.0 A, V
GS
= -10 V
37
50
nC
Q
gs
Gate-Source Charge
4
nC
Q
gd
Gate-Drain Charge
10
nC
NDS9407.SAM Rev. B
Electrical Characteristics
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current
-2.1
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -2.5 A
(Note 2)
-0.9
-1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is
guaranteed by design while R
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
-
T
A
R
J A
(
t
)
=
T
J
-
T
A
R
J C
+
R
CA
(
t
)
=
I
D
2
(
t
)
R
DS
(
ON
)
@
T
J
Typical R
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 50
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 105
o
C/W when mounted on a 0.04 in
2
pad of 2oz cpper.
c. 125
o
C/W when mounted on a 0.006 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS9407.SAM Rev. B
1a
1b
1c
NDS9407.SAM Rev. B
-5
-4
-3
-2
-1
0
-20
-15
-10
-5
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V = - 1 0 V
GS
DS
D
-4.0
-6.0
-5.0
-4.5
-7.0
-5.5
-3.5
-50
-25
0
2 5
5 0
7 5
100
125
150
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = - 1 0 V
GS
I = - 3 A
D
R , NORMALIZED
DS(ON)
-50
-25
0
25
50
75
1 0 0
1 2 5
1 5 0
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (C)
GATE-SOURCE THRESHOLD VOLTAGE
I = - 2 5 0 A
D
V = V
DS
GS
J
V , NORMALIZED
th
-20
-16
-12
- 8
- 4
0
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = - 4 . 0 V
GS
- 1 0
-6.0
-5.0
-4.5
-5.5
-8.0
-20
-15
-10
-5
0
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
D
R
A
I
N
-
S
O
U
R
C
E
O
N
-
R
E
S
I
S
T
A
N
C
E
T = 1 2 5 C
J
2 5 C
- 5 5 C
D
V = - 1 0 V
GS
R , NORMALIZED
DS(on)
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate Voltage
and Drain Current.
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with Drain Current
and Temperature.
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
-6
-5
-4
-3
-2
-1
-10
-8
-6
-4
-2
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = - 1 0 V
DS
GS
D
T = - 5 5 C
J
2 5 C
1 2 5 C
NDS9407.SAM Rev. B
-50
-25
0
25
50
75
100
125
150
0.9
0.925
0.95
0.975
1
1.025
1.05
1.075
1.1
1.125
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = - 2 5 0 A
D
BV , NORMALIZED
D
S
S
J
0.2
0.4
0.6
0.8
1
1.2
1.4
0.001
0.01
0.1
0.5
1
5
10
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125C
J
25C
-55C
V = 0 V
GS
SD
S
0
10
20
30
40
0
2
4
6
8
10
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -3A
DS
V = - 1 0 V
DS
- 2 0 V
- 4 0 V
0.1
0.2
0.5
1
2
5
10
20
50
50
1 0 0
2 0 0
5 0 0
1000
1500
2500
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 M H z
V = 0 V
GS
C
oss
C
rss
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
Typical Electrical Characteristics
(continued)
D
S
-V
D D
R
L
V
O U T
V
G S
D U T
V
IN
R
G E N
G
1 0 %
5 0 %
9 0 %
1 0 %
9 0 %
9 0 %
5 0 %
V
I N
V
O U T
o n
o f f
d ( o f f )
f
r
d ( o n )
t
t
t
t
t
t
INVERTED
1 0 %
P U L S E W I D T H
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