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REV. 1.0.2 9/14/01
www.fairchildsemi.com
Features
Implements ACPI control with PWROK, SLP_S3# and
SLP_S5
#
Switch and linear regulator controller for 3.3V Dual (PCI)
Linear regulator controller and linear regulator for 2.5V
Dual (RAMBUS)
Two switch controller for 5V Dual (USB)
Switch controller and linear regulator for 3.3V SDRAM
Provides SDRAM and RAMBUS power simultaneously
Adaptive Break-before-Make
Integrated Power Good
Drives all N-Channel MOSFETs plus NPN
Latched overcurrent protection for outputs
Power-up softstarts for the linear regulators
UVLO guarantees correct operation for all conditions
20 pin SOIC package
Applications
Camino Platform ACPI Controller
Whitney Platform ACPI Controller
Tehama Platform ACPI Controller
Description
The RC5060 is an ACPI Switch Controller for the Camino,
Whitney and Tehama Platforms. It is controlled by PWROK,
SLP_S3# and SLP_S5#, and provides 3.3V Dual for PCI, 3.3V
for SDRAM, 2.5V Dual for RAMBUS, and 5V Dual voltages.
An on-board precision low TC reference achieves tight toler-
ance voltage regulation without expensive external components.
The RC5060 also offers integrated Power Good and Current
Limiting that protects each output, and softstart for the linear
regulators. The RC5060 is available in a 20 pin SOIC.
Block Diagram
+5V Main
+5V Standby
+5V Dual (USB)
+3.3V Main
+5V Standby
+3.3V Dual (PCI)
19
18
17
6
7
8
+12V
20
-
+
-
+
REF
REF
Over Current
PWRGD
+5V Standby
PWROK
SLP_S3#
12
10
5
2
1
14
16
Softstart
13
3.3V MAIN
2.5V Dual
(RAMBUS)
REF
Over Current
9
15
11
SLP_S5#
REF
3.3V Main
3.3V SDRAM
Over Current
-
+
Ref
4
3
Osc
-
+
-
+
-
+
-
+
RC5060
ACPI Switch Controller
RC5060
PRODUCT SPECIFICATION
2
REV. 1.0.2 9/14/01
Pin Assignments
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1
QCAP
Charge pump cap.
Attach flying capacitor between this pin and PUMP to
generate high voltage from standby power.
2
PUMP
Charge pump switcher.
3
SDRAMOUT
3.3V SDRAM gate control.
Attach this pin to a transistor powering 3.3V SDRAM
from the 3.3V main supply.
4
SDRAMFB
3.3V SDRAM voltage feedback.
Pin 4 is used as the input for the voltage
feedback control loop for 3.3V SDRAM, and also sources 3.3V SDRAM in
standby.
5
5VSTBY
5V Standby.
Apply +5V standby on this pin to run the circuit in standby mode.
6
3VOUT1
3.3V main gate control.
Attach this pin to a transistor powering 3.3V dual from
the 3.3V main supply.
7
3VOUT2
3.3V standby gate control.
Attach this pin to a transistor powering 3.3V dual
from the 5V standby supply.
8
3VFB
3.3V voltage Feedback.
Pin 8 is used as the input for the voltage feedback
control loop for 3.3V dual.
9
PWRGD
Power Good.
Open collector output is high when all outputs are valid.
10
SLP_S3#
SLP_S3#.
Control signal governing the Soft Off state S3. Internal current source
pulls this line high if left open.
11
SLP_S5#
SLP_S5#.
Control signal governing the Soft Off state S5. Internal current source
pulls this line high if left open.
12
PWROK
PWROK.
Control signal for switches. Internal current source pulls this line high if left
open.
13
SS
Softstart.
Attach a capacitor to this pin to determine the softstart rate.
14
GND
Ground.
Connect this pin to ground.
15
RAMBUSFB
2.5V feedback.
Pin 15 is used as the input for the voltage feedback control loop for
2.5V dual (RAMBUS), and also sources 2.5V dual in standby.
16
RAMBUSOUT
2.5V base drive control.
Attach this pin to an NPN transistor powering 2.5V dual
(RAMBUS) from the 3.3V main supply.
17
5VFB
5V Voltage Feedback.
Pin 17 is used to sense undervoltage to protect the 5V dual
from overcurrent.
18
5VOUT2
5V standby gate control.
Attach this pin to a transistor powering 5V dual from the
5V standby supply.
19
5VOUT1
5V main gate control.
Attach this pin to a transistor powering 5V dual from the 5V
main supply.
20
VCCP
Main Power.
Apply +12V through a diode on this pin to run the circuit in normal
mode. Bypass with a 0.1F capacitor. When 12V is not present, this pin produces
voltage doubled 5V standby.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RC5060
QCAP
PUMP
SDRAMOUT
SDRAMFB
5VSTBY
3VOUT1
3VOUT2
3VFB
PWRGD
SLP_S3#
VCCP
5VOUT1
5VOUT2
5VFB
RAMBUSOUT
RAMBUSFB
GND
SS
PWROK
SLP_S5#
PRODUCT SPECIFICATION
RC5060
REV. 1.0.2 9/14/01
3
Absolute Maximum Ratings
Recommended Operating Conditions
VCCP
15V
All Other Pins
13.5V
Junction Temperature, T
J
150C
Storage Temperature
-65 to 150C
Lead Soldering Temperature, 10 seconds
300C
Thermal Resistance Junction to Ambient
JA
85C/W
Thermal Resistance Junction-to-case,
JC
24C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
+3.3VMAIN
3.135
3.3
3.465
V
+5VMAIN
4.75
5
5.25
V
+5VSTBY
4.75
5
5.25
V
+12V
11.4
12
12.6
V
Ambient Operating Temperature
0
70
C
RC5060
PRODUCT SPECIFICATION
4
REV. 1.0.2 9/14/01
Electrical Specifications
(V
+5VSTBY
= V
+5VMAIN
=5V, V
+3.3V
= 3.3V, V
+12V
= 12V and T
A
= +25C using circuit in Figure 4, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
+5V DUAL
V
Out1
, On
10
V
V
Out1
, Off
I = 10A
200
mV
V
GS
,
Out2
Standby
2.7
V
V
Out2
, Off
I = 10A
200
mV
Maximum Drive Current, Each
10
mA
Overcurrent Limit: Undervoltage
80
%V
out
Overcurrent Delay Time
150
sec
Output Driver Overlap Time
See Figure 2
1
5
sec
+3.3V DUAL
V
Out1
, On
10
V
V
Out1
, Off
I = 10A
200
mV
V
Out2
, On
Standby
5
mA
Total Output Voltage Variation
1
3VOUT2 On
3.135
3.3
3.465
V
Maximum Drive Current
3VOUT1 On
90
mA
Minimum Load Current
3VOUT2 On
50
mA
Overcurrent Limit: Undervoltage
80
%Vout
Overcurrent Delay Time
150
sec
Output Driver Deadtime
See Figure 2: Main
Standby
2
6
sec
: Standby
Main
200
1000
nsec
+2.5V DUAL
I
B
, On
RAMBUSOUT On
200
mA
I
Out
RAMBUSOUT Off
144
mA
Total Output Voltage Variation
1
2.375
2.5
2.625
V
Overcurrent Limit
80
%Vout
Overcurrent Delay Time
150
sec
Output Driver Overlap Time
See Figure 2
1
5
sec
+3.3V SDRAM
V
out
, On
10
V
V
out
, Off
I = 10A
200
mV
I
Out
SDRAMOUT Off
100
mA
Overcurrent Limit
80
%Vout
Total Output Voltage Variation
1
SDRAMFB On
3.135
3.3
3.465
V
Overcurrent Delay Time
150
sec
Output Driver Dead Time
200
1500
nsec
Common Functions
PWRGD Threshold
80
%Vout
PWRGD Delay Time
150
sec
PWRGD Sink Current
1
mA
Charge Pump Frequency
250
KHz
+5VSTBY UVLO
4.5
V
PRODUCT SPECIFICATION
RC5060
REV. 1.0.2 9/14/01
5
Note:
1. Voltage Regulation includes Initial Voltage Setpoint and Output Temperature Drift.
Table 1. Power Descriptors
*When PWROK = SLP_S3# = 0 and SLP_S5# transitions from 0 to 1, the RC5060 remains in the S5 state. See Table 2.
+5VSTBY UVLO Hysteresis
0.5
V
+12V UVLO
7.5
V
+12V UVLO Hysteresis
1
V
+5VSTBY Current
MAIN Power Present
10
25
mA
+12V Current
2.5
10
mA
Input Logic HIGH
2.0
V
Input Logic LOW
0.8
V
Softstart Current
3
6
9
A
Control Line Input Current
SLP_S5#, SLP_S3#, PWROK
10
A
Over Temperature Shutdown
150
C
PWROK SLP_S3# SLP_S5# Main
5V/3.3V Duals
2.5V RAMBUS/
3.3V SDRAM
State
Usage
1
1
1
ON
ON, Powered from MAIN ON, Powered from MAIN
S0
S0
1
0
1
OFF
ON, Powered from
STANDBY
ON, Powered from
STANDBY
S3
S0
S3
0
0
1
OFF
ON, Powered from
STANDBY
ON, Powered from
STANDBY
S3
S3
0
1
1
OFF
ON, Powered from
STANDBY
ON, Powered from
STANDBY
S3
S3
S0
1
0
0
OFF
ON, Powered from
STANDBY
OFF
S5
S0
S5
0
0
0
OFF
ON, Powered from
STANDBY
OFF
S5
S5
0
1
0
OFF
ON, Powered from
STANDBY
OFF
S5
S5
S0
1
1
0
ON
ON, Powered from MAIN OFF
S5
Not Used
0
0
0
1
OFF
ON, Powered from
STANDBY
OFF
S5*
*
Electrical Specifications (continued)
(V
+5VSTBY
= V
+5VMAIN
=5V, V
+3.3V
= 3.3V, V
+12V
= 12V and T
A
= +25C using circuit in Figure 4, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
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