2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
RFD3055LE, RFD3055LESM, RFP3055LE
11A, 60V, 0.107 Ohm, Logic Level,
N-Channel Power MOSFETs
These N-Channel enhancement-mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers and relay
drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49158.
Features
11A, 60V
r
DS(ON)
= 0.107
Temperature Compensating PSPICE
Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD3055LE
TO-251AA
F3055L
RFD3055LESM
TO-252AA
F3055L
RFP3055LE
TO-220AB
FP3055LE
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252 variant in tape and reel, e.g. RFD3055LESM9A.
D
G
S
JEDEC TO-220AB
JEDEC TO-251AA
JEDEC TO-252AA
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
SOURCE
DRAIN (FLANGE)
GATE
DRAIN
GATE
SOURCE
DRAIN (FLANGE)
Data Sheet
January 2002
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFD3055LE, RFD3055LESM,
RFP3055LE
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
60
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
16
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
11
Refer to Peak Current Curve
A
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
0.25
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V
60
-
-
V
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A
1
-
3
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 55V, V
GS
= 0V
-
-
1
A
V
DS
= 50V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
=
16V
-
-
100
nA
Drain to Source On Resistance (Note 2)
r
DS(ON)
I
D
= 8A, V
GS
= 5V (Figure 11)
-
-
0.107
Turn-On Time
t
ON
V
DD
30V, I
D
= 8A,
V
GS
= 4.5V, R
GS
= 32
(Figures 10, 18, 19)
-
-
170
ns
Turn-On Delay Time
t
d(ON)
-
8
-
ns
Rise Time
t
r
-
105
-
ns
Turn-Off Delay Time
t
d(OFF)
-
22
-
ns
Fall Time
t
f
-
39
-
ns
Turn-Off Time
t
OFF
-
-
92
ns
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 10V
V
DD
= 30V, I
D
= 8A,
I
g(REF)
= 1.0mA
(Figures 20, 21)
-
9.4
11.3
nC
Gate Charge at 5V
Q
g(5)
V
GS
= 0V to 5V
-
5.2
6.2
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 1V
-
0.36
0.43
nC
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 14)
-
350
-
pF
Output Capacitance
C
OSS
-
105
-
pF
Reverse Transfer Capacitance
C
RSS
-
23
-
pF
Thermal Resistance Junction to Case
R
JC
-
-
3.94
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-220AB
-
-
62
o
C/W
TO-251AA, TO-252AA
-
-
100
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 8A
-
1.25
V
Diode Reverse Recovery Time
t
rr
I
SD
= 8A, dI
SD
/dt = 100A/
s
-
66
ns
NOTES:
2. Pulse Test: Pulse Width
300ms, Duty Cycle
2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
RFD3055LE, RFD3055LESM, RFP3055LE
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
T
C
, CASE TEMPERATURE (
o
C)
25
50
75
100
125
150
175
0
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
0.2
0.4
0.6
0.8
1.0
1.2
5
10
15
25
50
75
100
125
150
175
0
I
D
,
DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
V
GS
= 4.5V
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t, RECTANGULAR PULSE DURATION (s)
Z
JC
,
NORMALIZED
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
THERMAL IMPED
ANCE
1
10
100
1
10
100
0.1
200
100
s
10ms
1ms
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
T
J
= MAX RATED T
C
= 25
o
C
SINGLE PULSE
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
200
10
I
DM
,
PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 5V
RFD3055LE, RFD3055LESM, RFP3055LE
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
10
100
0.001
0.01
0.1
1
10
1
I
AS
,
A
V
ALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 150
o
C
I
D
,
DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 3V
V
GS
= 5V
V
GS
= 10V
V
GS
= 4V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
3
6
9
12
15
0
1
2
3
4
0
V
GS
= 3.5V
T
C
= 25
o
C
3
6
9
12
15
2
3
4
5
0
I
D,
DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
90
120
150
2
4
6
8
10
60
I
D
= 3A
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(ON)
,
DRAIN
T
O
SOURCE
ON RESIST
ANCE (m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
I
D
= 11A
I
D
= 5A
50
100
150
0
10
20
30
40
50
0
SWITCHING TIME
(ns)
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 4.5V, V
DD
= 30V, I
D
= 8A
t
r
t
f
t
d(ON)
t
d(OFF)
1.0
1.5
2.0
2.5
-80
-40
0
40
80
120
160
200
0.5
NORMALIZED DRAIN
T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESIST
ANCE
V
GS
= 10V, I
D
= 11A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
RFD3055LE, RFD3055LESM, RFP3055LE
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
0.8
1.0
1.2
-80
-40
0
40
80
120
160
200
0.6
NORMALIZED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
THRESHOLD V
O
L
T
A
G
E
1.0
1.1
1.2
-80
-40
0
40
80
120
160
200
0.9
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN
T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
I
D
= 250
A
100
1000
0.1
1
10
60
10
C,
CAP
A
CIT
ANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
= C
GD
2
4
6
8
10
0
2
4
6
8
10
0
V
GS
,
GA
TE
T
O
SOURCE
V
O
L
T
A
G
E (V)
Q
g
, GATE CHARGE (nC)
V
DD
= 30V
I
D
= 11A
I
D
= 5A
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 3A
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
RFD3055LE, RFD3055LESM, RFP3055LE
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
FIGURE 18. SWITCHING TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
OR Q
g(5)
V
GS
= 5V FOR
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
V
GS
= 1V FOR
L
2
DEVICES
L
2
DEVICES
V
GS
= 10V
V
GS
= 10V FOR
L
2
DEVICES
RFD3055LE, RFD3055LESM, RFP3055LE
2002 Fairchild Semiconductor Corporation
RFD3055LE, RFD3055LESM, RFP3055LE Rev. B
PSPICE Electrical Model
.SUBCKT RFD3055LE 2 1 3 ;
rev 1/30/95
CA 12 8 3.9e-9
CB 15 14 4.9e-9
CIN 6 8 3.25e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 2.57e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.7e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 25.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))}
.MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6)
.MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81)
.MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RFD3055LE, RFD3055LESM, RFP3055LE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGICTM
OPTOPLANARTM
PACMANTM
POPTM
Power247TM
PowerTrench
QFETTM
QSTM
QT OptoelectronicsTM
Quiet SeriesTM
SILENT SWITCHER
FAST
FASTrTM
FRFETTM
GlobalOptoisolatorTM
GTOTM
HiSeCTM
ISOPLANARTM
LittleFETTM
MicroFETTM
MicroPakTM
MICROWIRETM
Rev. H4
ACExTM
BottomlessTM
CoolFETTM
CROSSVOLTTM
DenseTrenchTM
DOMETM
EcoSPARKTM
E
2
CMOS
TM
EnSigna
TM
FACTTM
FACT Quiet SeriesTM
SMART STARTTM
STAR*POWERTM
StealthTM
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
SyncFETTM
TinyLogicTM
TruTranslationTM
UHCTM
UltraFET
STAR*POWER is used under license
VCXTM
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