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Электронный компонент: RFP12N10L

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2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
RFP12N10L
12A, 100V, 0.200 Ohm, Logic Level,
N-Channel Power MOSFET
These are N-Channel enhancement mode silicon gate
power field effect transistors specifically designed for use
with logic level (5V) driving sources in applications such as
programmable controllers, automotive switching and
solenoid drivers. This performance is accomplished through
a special gate oxide design which provides full rated
conduction at gate biases in the 3V to 5V range, thereby
facilitating true on-off power control directly from logic circuit
supply voltages.
Formerly developmental type TA09526.
Features
12A, 100V
r
DS(ON)
= 0.200
Design Optimized for 5V Gate Drives
Can be Driven Directly from QMOS, NMOS,
TTL Circuits
Compatible with Automotive Drive Requirements
SOA is Power-Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Majority Carrier Device
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFP12N10L
TO-220AB
F12N10L
NOTE: When ordering, include the entire part number.
D
G
S
SOURCE
DRAIN
GATE
DRAIN
(TAB)
Data Sheet
January 2002
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2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFP12N10L
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
100
V
Drain to Gate Voltage (R
GS
= 1M
)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
12
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
30
A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
10
V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
60
W
Above T
C
= 25
o
C, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.48
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250mA, V
GS
= 0V
100
-
-
V
Gate to Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250mA (Figure 7)
1
-
2
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 65V, V
DS
= 80V
-
-
1
A
V
DS
= 65V, V
DS
= 80V
T
C
= 125
o
C
-
-
50
A
Gate to Source Leakage Current
I
GSS
V
GS
= 10V, V
DS
= 0V
-
-
100
A
Drain to Source On Resistance (Note 2)
r
DS(ON)
I
D
= 12A, V
GS
= 5V (Figures 5, 6)
-
-
0.2
Input Capacitance
C
ISS
V
GS
= 0V, V
DS
= 25V, f = 1MHz
(Figure 8)
-
-
900
pF
Output Capacitance
C
OSS
-
-
325
pF
Reverse-Transfer Capacitance
C
RSS
-
-
170
pF
Turn-On Delay Time
t
d(ON)
I
D
= 6A, V
DD
= 50V, R
G
= 6.25
,
V
GS
= 5V
(Figures 9, 10, 11)
-
15
50
ns
Rise Time
t
r
-
70
150
ns
Turn-Off Delay Time
t
d(OFF)
-
100
130
ns
Fall Time
t
f
-
80
150
ns
Thermal Resistance Junction to Case
R
JC
RFP12N10L
2.083
oC/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage (Note 2)
V
SD
I
SD
= 6A
-
-
1.4
V
Diode Reverse Recovery Time
t
rr
I
SD
= 4A, dI
SD
/dt = 50A/
s
-
150
-
ns
NOTES:
2. Pulsed: pulse duration = 80
s max, duty cycle = 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature.
RFP12N10L
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2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. FORWARD BIAS OPERATING AREA
FIGURE 3. SATURATION CHARACTERISTICS
FIGURE 4. TRANSFER CHARACTERISTICS
FIGURE 5. DRAIN TO SOURCE ON RESISTANCE vs DRAIN
CURRENT
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
0
50
100
150
0
T
C
, CASE TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
100
10
1
1000
1
10
100
OPERATION IN THIS
REGION IS LIMITED
BY r
DS(ON)
0.1
I
D
,
DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T
C
= 25
o
C
DC OPERATION
60W
I
D
(MAX) CONTINUOUS
TJ = MAX RATED
40
30
20
0
10
1
2
3
4
0
5
V
GS
= 10V
PULSE DURATION = 80
s
DUTY CYCLE
0.5%
T
C
= 25
o
C
5V
4V
3V
2V
I
D
,
DRAIN CURRENT (A)
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
20
15
10
0
5
1
2
3
4
0
V
DS
= 10V
5
25
o
C
125
o
C
-40
o
C
PULSE DURATION = 80
s
DUTY CYCLE
0.5%
-40
o
C
I
D(ON)
,
ON-ST
A
TE DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
125
o
C
r
DS
(ON)
,
DRAIN
T
O
SOURCE ON
I
D,
DRAIN CURRENT (A)
0.3
0.2
0.1
0
0
5
10
15
20
25
30
RESIST
ANCE (
)
-40
o
C
25
o
C
V
GS
= 5V
PULSE DURATION = 80
s
DUTY CYCLE
0.5%
125
o
C
2.0
1.5
1.0
0
0.5
0
50
100
150
-50
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN
T
O
SOURCE
ON RESIST
ANCE
V
GS
= 5V, I
D
= 12A
PULSE DURATION = 80
s
DUTY CYCLE
0.5%
RFP12N10L
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2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Applications Notes AN7254 and AN7260
FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 10. SWITCHING TIME TEST CIRCUIT
FIGURE 11. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified
(Continued)
1.3
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0
50
100
150
-50
V
DS
= V
GS
I
D
= 250
A
NORMALIZED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
THRESHOLD V
O
L
T
A
GE
(V)
1.2
800
600
400
200
0
0
10
20
30
40
50
C
ISS
C
OSS
C
RSS
C,
CAP
A
CIT
ANCE (pF)
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
0.75BV
DSS
0.50BV
DSS
0.25BV
DSS
DRAIN SOURCE
VOLTAGE
GATE
SOURCE
VOLTAGE
R
L
= 8.33
I
G (REF)
= 0.56mA
V
GS
= 5V
V
DD
= BV
DSS
V
DD
= BV
DSS
BV
DSS
I
G
(REF)
I
G
(ACT)
20
80
I
G
(REF)
I
G
(ACT)
t, TIME (
s)
GA
TE
T
O
SOURCE
V
O
L
T
A
GE (V)
DRAIN
T
O
SOURCE
V
O
L
T
A
GE (V)
100
75
50
25
0
10
8
6
4
0
2
V
GS
R
L
R
G
DUT
+
-
V
DD
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
RFP12N10L
background image
2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
FIGURE 12. GATE CHARGE TEST CIRCUIT
FIGURE 13. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
G(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
G(REF)
0
0
RFP12N10L