CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright
Harris Corporation 1996
1
S E M I C O N D U C T O R
RLD03N06CLE,
RLD03N06CLESM, RLP03N06CLE
0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped
Logic Level N-Channel Enhancement-Mode Power MOSFETs
July 1996
Absolute Maximum Ratings
T
C
= +25
o
C
RLD03N06CLE,
RLD03N06CLESM,
RLP03N06CLE
UNITS
Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DSS
60
V
Drain Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60
V
Gate Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Reverse Voltage Gate Bias Not Allowed
+5.5
V
Drain Current
RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Self Limited
Power Dissipation
T
C
= +25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate above +25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
T
30
0.2
W
W/
o
C
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . ESD
2
KV
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
STG
, T
J
-55 to +175
o
C
File Number
3948.3
Packages
JEDEC TO-220AB
JEDEC TO-251AA
JEDEC TO-252AA
Symbol
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
SOURCE
GATE
DRAIN
(FLANGE)
G
S
D
Features
0.30A, 60V
r
DS(ON)
= 6.0
Built in Current Limit I
LIMIT
0.140 to 0.210A at 150
o
C
Built in Voltage Clamp
Temperature Compensating PSPICE Model
2kV ESD Protected
Controlled Switching Limits EMI and RFI
Description
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
are intelligent monolithic power circuits which incorporate a lat-
eral bipolar transistor, resistors, zener diodes and a power MOS
transistor. The current limiting of these devices allow it to be used
safely in circuits where a shorted load condition may be encoun-
tered. The drain-source voltage clamping offers precision control
of the circuit voltage when switching inductive loads. The "Logic
Level" gate allows this device to be fully biased on with only 5.0V
from gate to source, thereby facilitating true on-off power control
directly from logic level (5V) integrated circuits.
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
incorporate ESD protection and are designed to withstand 2kV
(Human Body Model) of ESD.
Formerly developmental type TA49026.
PACKAGING AVAILABILITY
PART NUMBER
PACKAGE
BRAND
RLD03N06CLE
TO-251AA
03N06C
RLD03N06CLESM
TO-252AA
03N06C
RLP03N06CLE
TO-220AB
03N06CLE
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e.
RLD03N06CLESM9A.
2
Specifications RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Electrical Specifications
T
C
= +25
o
C, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain-Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V
60
-
85
V
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A
1
-
2.5
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 45V,
V
GS
= 0V
T
J
= +25
o
C
-
-
50
A
T
J
= +150
o
C
-
-
200
A
Gate-Source Leakage Current
I
GSS
V
GS
= 5V
T
J
= +25
o
C
-
-
5
A
T
J
= +150
o
C
-
-
20
A
On Resistance
r
DS(ON)
I
D
= 0.100A,
V
GS
= 5V
T
J
= +25
o
C
-
-
6.0
T
J
= +150
o
C
-
-
12.0
Limiting Current
I
DS(LIMIT)
V
DS
= 15V,
V
GS
= 5V
T
J
= +25
o
C
280
-
420
mA
T
J
= +150
o
C
140
-
210
mA
Turn-On Time
t
ON
V
DD
= 30V, I
D
= 0.10A,
R
L
= 3
00
, V
GS
= 5V,
R
GS
= 25
-
-
7.5
s
Turn-On Delay Time
t
D(ON)
-
-
2.5
s
Rise Time
t
R
-
-
5.0
s
Turn-Off Delay Time
t
D(OFF)
-
-
7.5
s
Fall Time
t
F
-
-
5.0
s
Turn-Off Time
t
OFF
-
-
12.5
s
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
100
-
pF
Output Capacitance
C
OSS
-
65
-
pF
Reverse Transfer Capacitance
C
RSS
-
3.0
-
pF
Thermal Resistance Junction to Case
R
JC
-
-
5.0
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-220 Package
-
-
80
o
C/W
TO-251 and TO-252 Packages
-
-
100
o
C/W
Source-Drain Diode Ratings and Specifications
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Forward Voltage
V
SD
I
SD
= 0.1A
-
-
1.5
V
Reverse Recovery Time
t
RR
I
SD
= 0.1A, dI
SD
/dt = 100A/
s
-
-
1.0
ms
3
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Typical Performance Curves
FIGURE 1. SAFE OPERATING AREA CURVE
FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL
IMPEDANCE
FIGURE 3. TYPICAL NORMALIZED DRAIN CURRENT vs
JUNCTION TEMPERATURE
FIGURE 4. NORMALIZED POWER DISSIPATION vs
TEMPERATURE DERATING CURVE
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS
FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
1
10
100
I
D
,
DRAIN CURRENT
(A)
0.1
1
175
o
C
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
T
C
= +25
o
C
OPERATION IN THIS
AREA IS LIMITED BY
JUNCTION TEMPERATURE
25
o
C
DC
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NORMALIZED
THERMAL RESPONSE
0.01
0.02
0.05
0.1
0.2
0.5
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
+ T
C
P
DM
t
1
t
2
10
1
0.1
0.01
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
I
D
, NORMALIZED DRAIN CURRENT
2.0
1.0
0.5
0
1.5
T
J
, JUNCTION TEMPERATURE (
o
C)
-80
-40
0
40
80
120
160
200
T
C
, CASE TEMPERATURE (
o
C)
25
50
75
100
125
150
175
0
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
PULSE DURATION = 250
s, T
C
= +25
o
C
0
0.10
0.20
0.30
0
1.0
2.0
3.0
4.0
5.0
V
GS
= 3V
V
GS
= 4V
V
GS
= 7.5V
V
GS
= 5V
0.40
+25
o
C
+175
o
C
V
DD
= 15V
V
GS
, GATE-TO-SOURCE VOLTAGE (V)
0.0
2.0
3.0
4.0
5.0
1.0
0
0.30
0.40
I
D(ON)
, ON ST
A
TE DRAIN CURRENT (A)
PULSE TEST
PULSE DURATION = 250
s
DUTY CYCLE = 0.5% MAX
-55
o
C
0.50
0.60
0.20
0.10
4
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
FIGURE 7. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
TEMPERATURE
FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN
VOLTAGE vs TEMPERATURE
FIGURE 10. SELF-CLAMPED INDUCTIVE SWITCHING
FIGURE 11. TYPICAL CAPACITANCE vs DRAIN-TO-SOURCE
VOLTAGE
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT. REFER TO HARRIS
APPLICATION NOTES AN7254 AND AN7260
Typical Performance Curves
(Continued)
T
J
, JUNCTION TEMPERATURE (
o
C)
I
D
= 0.30A
V
GS
= 5V,
PULSE DURATION = 250
s,
0.0
0.5
1.0
1.5
2.0
2.5
-80
-40
0
40
80
120
160
200
r
DS(ON)
, NORMALIZED ON RESIST
ANCE
T
J
, JUNCTION TEMPERATURE (
o
C)
-80
-40
0
40
80
120
200
160
0.0
0.5
1.0
1.5
2.0
V
GS(TH)
, NORMALIZED GA
TE
V
GS
= V
DS
,
I
D
= 250
A
THRESHOLD V
O
L
T
A
G
E
I
D
= 20mA
2.0
1.5
1.0
0.5
0.0
-80
-40
0
40
80
120
160
200
BV
DSS
, NORMALIZED DRAIN-T
O-
SOURCE BREAKDO
WN V
O
L
T
A
G
E
T
J
, JUNCTION TEMPERATURE (
o
C)
t
AV
, TIME IN CLAMP (s)
0.01
0.1
1
10
I
(CLAMP)
,
CLAMPED DRAIN CURRENT (A)
0.1
1
+25
o
C
0.001
+50
o
C
+100
o
C
+125
o
C
+150
o
C
TEMPERATURES LISTED ARE STARTING
JUNCTION TEMPERATURES
T
C
= +25
o
C
+75
o
C
V
GS
= 0V,
FREQUENCY (f) = 1MHz
300
100
0
0
5
10
15
20
25
C
,
CAP
A
CIT
ANCE (pF)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
C
RSS
200
C
OSS
C
ISS
60
45
30
15
0
I
G REF
(
)
I
G AC T
(
)
----------------------
t, TIME (
s)
I
G REF
(
)
I
G AC T
(
)
----------------------
5.00
3.75
2.50
1.25
0.00
V
DS
, DRAIN SOURCE V
O
L
T
A
GE (V)
V
GS
, GA
TE SOURCE V
O
L
T
A
GE (V)
V
DD
= BV
DSS
R
L
= 600
I
G(REF)
= 0.1mA
V
GS
= 5V
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
10
40
5
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Test Circuit and Waveform
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
V
DD
V
DS
V
GS
0V
R
GS
DUT
R
L
t
ON
t
D(ON)
t
R
90%
10%
V
DS
90%
10%
t
F
t
D(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
Detailed Description
Temperature Dependence of Current Limiting and
Switching Speed Performance
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
are a monolithic power device which incorporates a Logic Level
power MOSFET transistor with a current sensing scheme and
control circuitry to enable the device to self limit the drain
source current flow. The current sensing scheme supplies cur-
rent to a resistor that is connected across the base to emitter of
a bipolar transistor in the control section. The collector of this
bipolar transistor is connected to the gate of the power MOS-
FET transistor. When the ratiometric current from the current
sensing reaches the value required to forward bias the base
emitter junction of this bipolar transistor, the bipolar "turns on".
A resistor is incorporated in series with the gate of the power
MOSFET transistor allowing the bipolar transistor to adjust the
drive on the gate of the power MOSFET transistor to a voltage
which then maintains a constant current in the power MOSFET
transistor. Since both the ratiometric current sensing scheme
and the base emitter unction voltage of the bipolar transistor
vary with temperature, the current at which the device limits is a
function of temperature. This dependence is shown in Figure 3.
The resistor in series with the gate of the power MOSFET
transistor also results in much slower switching performance
than in standard power MOSFET transistors. This is an
advantage where fast switching can cause EMI or RFI. The
switching speed is very predictable.
DC Operation
The limit on the drain to source voltage for operation in cur-
rent limiting on a steady state (DC) basis is shown in the
equation below. The dissipation in the device is simply the
applied drain to source voltage multiplied by the limiting cur-
rent. This device, like most power MOSFET devices today, is
limited to 175
o
C. The maximum voltage allowable can,
therefore, be expressed as shown in Equation 1:
(EQ. 1)
The results of this equation are plotted in Figure 15 for vari-
ous heatsinks.
V
DS
150
C T
A MBIENT
(
)
I
LM
R
JC
R
JA
+
(
)
-------------------------------------------------------
=
Duty Cycle Operation
In many applications either the drain to source voltage or the
gate drive is not available 100% of the time. The copper
header on which the RLD03N06CLE, RLD03N06CLESM
and RLP03N06CLE is mounted has a very large thermal
storage capability, so for pulse widths of less then 1ms, the
temperature of the header can be considered a constant,
thereby the junction temperature can be calculated simply as
shown in Equation 2:
(EQ. 2)
Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations. Mak-
ing this assumption, limiting junction temperature to 175
o
C
and using the T
C
calculated in Equation 2, the expression for
maximum V
DS
under duty cycle operation is shown in Equa-
tion 3:
(EQ. 3)
These values are plotted as Figures 16 through 21 for vari-
ous heatsink thermal resistances.
Limited Time Operations
Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10 ms,
thereby the thermal equivalent circuit reduces to a simple
enough circuit to allow easy computation on the limiting con-
ditions. The variation in limiting current with temperature
complicates the calculation of junction temperature, but a
simple straight line approximation of the variation is accurate
enough to allow meaningful computations. The curves
shown as Figures 22 through 25 (RLP03N06CLE) and Fig-
ure 26 through 29 (RLD03N06CLE and RLD03N06CLESM)
give an accurate indication of how long the specified voltage
can be applied to the device in the current limiting mode
without exceeding the maximum specified 175
o
C junction
temperature. In practice this tells you how long you have to
alleviate the condition causing the current limiting to occur.
T
C
V
DS
I
D
D
R
CA
(
)
T
A MBIENT
+
=
V
DS
150 C
T
C
o
I
LM
D
R
JC
------------------------------------------
=
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