September 2004
RMPA0951AT
2004 Fairchild Semiconductor Corporation
RMPA0951AT Rev. D
RMPA0951AT
3V Cellular CDMA PowerEdgeTM Power Amplifier Module
General Description
The RMPA0951AT is a dual mode, small-outline Power
Amplifier Module (PAM) for Cellular CDMA personal
communication system applications. The PA is internally-
matched to 50
and DC blocked which minimizes the use
of external components and reduces circuit complexity for
system designers. High AMPS/CDMA efficiency and good
linearity are achieved using our InGaP Heterojunction
Bipolar Transistor (HBT) process.
Features
Single positive-supply operation
High dual-mode (AMPS/CDMA) efficiency
Excellent linearity
Small size: 6.0 x 6.0 x 1.5 mm
3
LCC package
50
matched input and output module
Adjustable quiescent current and power-down mode
Suitable for CDMA and CDMA2000 1X systems
Absolute Ratings
1
Notes:
1:
No permanent damage with only one parameter set at extreme limit and other parameters typical.
2:
Typical RF input powers for (+28dBm, CDMA) is -3dBm and for (+31dBm, AMPS) is +2dBm.
Symbol
Parameter
Ratings
Units
Vc1, Vc2
Supply Voltage
6.0
V
Vref
Reference Voltage
1.5 to 4.0
V
Pin
RF Input Power
2
+7
dBm
VSWR
Load VSWR
6:1
Tc
Case Operating Temperature
-30 to +85
C
Tstg
Storage Temperature
-55 to +150
C
Device
2004 Fairchild Semiconductor Corporation
RMPA0951AT Rev. D
RMPA0951AT
Electrical Characteristics
3
Notes:
3:
All parameters to be met at Ta = +25C, Vcc = +3.4V, Vref = 3.0V and load VSWR
1.2:1.
4:
Load VSWR
6:1 all phase angles.
5:
CDMA waveform measured using the ratio of the average power within the 1.23 MHz signal channel to the power within a 30 kHz resolution bandwidth,
at a 885 KHz offset, Pout = 28dBm, offset is 885 KHz, 1.98 MHz.
6:
No applied RF signal. Vcc = +3.4V nominal, Vref = +0.2V maximum.
7:
Guaranteed by design.
Parameter
Min
Typ
Max
Units
Frequency Range
824
849
MHz
Gain (Pout = +28dBm)
30
dB
Gain (Pout = +31dBm)
29
dB
Analog Output Power
31
dBm
Power-Added Efficiency
CDMA (Pout = +28dBm)
Analog (Pout = +31.5dBm)
32
44
35
50
%
%
ACPR1
5
-52
-46
dBc
ACPR2
5
-58
-55
dBc
Rx-Band Noise Power (All Power Levels)
-135
dBm/Hz
Noise Figure
3
dB
Input VSWR (50
)
1.5:1
2.5:1
--
Output VSWR (50
)
2.5:1
--
Stability (All spurious)
4,7
-60
dBc
Harmonics (Po < 28dBm)
2fo, 3fo, 4fo
7
-30
dBc
Quiescent Current
80
120
mA
Power Shutdown Current
6
2
10
A
Vcc
3.0
3.4
4.0
V
Vref
2.0
3.0
3.2
V
Iref
16
mA
2004 Fairchild Semiconductor Corporation
RMPA0951AT Rev. D
RMPA0951AT
With device marking oriented right side up, RF IN is on the left and RF OUT is on the right.
Vcc = +3.4V nominal. Vref = +3.0V nominal to obtain Iccq = 80 mA. Operation at lower or higher quiescent currents can be
achieved by decreasing or increasing Vref voltage relative to +3.0V.
First ground the PCB (GND terminal) and apply +3.4V to the collector supply terminals (Vcc1, Vcc2). Next apply +3.0V to
the reference supply (Vref terminal). Quiescent collector current with no RF applied will be about 80 mA. Reference supply
current with or without RF applied will be about 15 mA. When turning amplifier off, reverse power supply sequence.
Apply -20dBm RF input power at Cellular frequency (824-849 MHz). After making any initial small signal measurements at
this drive level, input power may be increased up to a maximum of +7dBm for large signal, analog (AMPS) or digital CDMA
measurements. Do not exceed +7dBm input power.
Figure 3. Evaluation Board Layout and Instructions
PCB Schematic
Figure 4. Evaluation Board Schematic
Vcc1
Vref
Vcc2
PCB Specifications:
Material: Rogers R04003
Dimensions: 2.0"x1.5"x0.032"
Metallization: 1/2 oz
Copper Cladding
C1*
3.3
F
C2*
3.3
F
(package base)
* Minimum bypass capacitance recommended for best linearity/low-noise performance.
Note: Addition of C3 bypass
capacitor on Vref pin
recommended to minimize
Rx band noise
1
2
3
6
5
4
7
C3*
1000 pF
Vcc1
Vcc2
N/C
50
TRL
RMPA0951AT
50
TRL
Vref
SMA1
RF IN
SMA2
RF OUT
2004 Fairchild Semiconductor Corporation
RMPA0951AT Rev. D
RMPA0951AT
Application Information
Precautions to Avoid Permanent Device Damage:
Cleanliness:
Observe proper handling procedures to
ensure clean devices and PCBs. Devices should remain
in their original packaging until component placement to
ensure no contamination or damage to RF, DC & ground
contact areas.
Device Cleaning:
Standard board cleaning techniques
should not present device problems provided that the
boards are properly dried to remove solvents or water
residues.
Static Sensitivity:
Follow ESD precautions to protect
against ESD damage:
A properly grounded static-dissipative surface on
which to place devices.
Static-dissipative floor or mat.
A properly grounded conductive wrist strap for each
person to wear while handling devices.
General Handling:
Handle the package on the top
with a vacuum collet or along the edges with a sharp
pair of bent tweezers. Avoiding damaging the RF, DC,
& ground contacts on the package bottom. Do not
apply excessive pressure to the top of the lid.
Device Storage:
Devices are supplied in heat-sealed,
moisture-barrier bags. In this condition, devices are
protected and require no special storage conditions.
Once the sealed bag has been opened, devices
should be stored in a dry nitrogen environment.
Device Usage:
Fairchild recommends the following procedures prior to
assembly.
Dry-bake devices at 125C for 24 hours minimum. Note:
The shipping trays cannot withstand 125C baking
temperature.
Assemble the dry-baked devices within 7 days of
removal from the oven.
During the 7-day period, the devices must be stored in an
environment of less than 60% relative humidity and a
maximum temperature of 30C
If the 7-day period or the environmental conditions have
been exceeded, then the dry-bake procedure must be
repeated.
Solder Materials & Temperature Profile:
Reflow soldering is the preferred method of SMT
attachment. Hand soldering is not recommended.
Reflow Profile
Ramp-up: During this stage the solvents are evaporated
from the solder paste. Care should be taken to prevent
rapid oxidation (or paste slump) and solder bursts
caused by violent solvent out-gassing. A typical heating
rate is 1 - 2C/sec.
Pre-heat/soak: The soak temperature stage serves two
purposes; the flux is activated and the board and devices
achieve a uniform temperature. The recommended soak
condition is: 120 -150 seconds at 150C.
Reflow Zone: If the temperature is too high, then devices
may be damaged by mechanical stress due to thermal
mismatch or there may be problems due to excessive
solder oxidation. Excessive time at temperature can
enhance the formation of inter-metallic compounds at
the lead/board interface and may lead to early
mechanical failure of the joint. Reflow must occur prior to
the flux being completely driven off. The duration of peak
reflow temperature should not exceed 10 seconds.
Maximum soldering temperatures should be in the range
215 -220C, with a maximum limit of 225C.
Cooling Zone: Steep thermal gradients may give rise to
excessive thermal shock. However, rapid cooling
promotes a finer grain structure and a more crack-
resistant solder joint. Figure 4 indicates the
recommended soldering profile.
Solder Joint Characteristics:
Proper operation of this device depends on a reliable void-
free attachment of the heatsink to the PWB. The solder joint
should be 95% void-free and be a consistent thickness.
Rework Considerations:
Rework of a device attached to a board is limited to reflow
of the solder with a heat gun. The device should not be
subjected to more than 225C and reflow solder in the
molten state for more than 5 seconds. No more than 2
rework operations should be performed.
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