April 2001
SI3948DV
Dual N-Channel Logic Level PowerTrench
MOSFET
General Description
Features
Absolute Maximum Ratings
T
A
= 25C unless otherwise note
Symbol Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
30
V
V
GSS
Gate-Source Voltage - Continuous
20
V
I
D
Drain Current - Continuous
2.5
A
- Pulsed
10
P
D
Maximum Power Dissipation
(Note 1a)
0.96
W
(Note 1b)
0.9
(Note 1c)
0.7
T
J
,T
STG
Operating and Storage Temperature Range
-55 to 150
C
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
130
C/W
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
60
C/W
SI3948DV Rev.A
These N-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
These devices are well suited for all applications where
small size is desireable but especially low cost DC/DC
conversion in battery powered systems.
2.5 A, 30 V. R
DS(ON)
= 0.095
@ V
GS
= 10 V
R
DS(ON)
= 0.145
@ V
GS
= 4.5 V
Very fast switching.
Low gate charge (2.1nC typical).
SuperSOT
TM
-6 package: small footprint (72% smaller than
standard SO-8); low profile (1mm thick).
SOIC-16
SOT-23
SuperSOT
TM
-8
SO-8
SOT-223
SuperSOT
TM
-6
D1
S2
G1
D2
S1
G2
SuperSOT -6
TM
pin
1
.561
1
5
3
2
6
4
2001 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 25C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 A
30
V
BV
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
I
D
= 250 A, Referenced to 25
o
C
23.6
mV/
o
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
A
T
J
= 55
o
C
10
A
I
GSSF
Gate - Body Leakage, Forward
V
GS
= 20 V, V
DS
= 0 V
100
nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 A
1
1.8
3
V
V
GS(th)
/
T
J
Gate Threshold VoltageTemp.Coefficient
I
D
= 250 A, Referenced to 25
o
C
-4
mV/
o
C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 2.5 A
0.082
0.095
T
J
= 125
o
C
0.122
0.152
V
GS
= 4.5 V, I
D
= 2.0 A
0.113
0.145
I
D(on)
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
10
A
g
FS
Forward Transconductance
V
DS
= 5 V, I
D
= 2.5 A
5
S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance
V
DS
= 15 V, V
GS
= 0 V,
220
pF
C
oss
Output Capacitance
f = 1.0 MHz
50
pF
C
rss
Reverse Transfer Capacitance
25
pF
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= 5 V, I
D
= 1 A,
6
12
ns
t
r
Turn - On Rise Time
V
GS
= 10 V, R
GEN
= 6
10
18
ns
t
D(off)
Turn - Off Delay Time
12
22
ns
t
f
Turn - Off Fall Time
2
6
ns
Q
g
Total Gate Charge
V
DS
= 15 V, I
D
= 2.5 A
2.3
3.2
nC
Q
gs
Gate-Source Charge
V
GS
= 5 V
0.7
1
nC
Q
gd
Gate-Drain Charge
0.9
1.3
nC
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
Continuous Source Diode Current
0.75
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.75 A
(Note 2)
0.78
1.2
V
Notes:
1. R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JC
is guaranteed
by design while R
CA
is determined by the user's board design.
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
SI3948DV Rev.A
c. 180
O
C/W on a minimum pad.
b. 140
O
C/W on a 0.005 in
2
pad of
2oz copper.
a. 130
O
C/W on a 0.125 in
2
pad of
2oz copper.
SI3948DV Rev.A
0
1
2
3
4
0
2
4
6
8
10
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V =10V
GS
3.5V
4.5V
4.0V
DS
D
6.0V
3.0V
0
2
4
6
8
10
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 4.0V
GS
10V
6.0V
4.5V
D
7.0V
R , NORMALIZED
5.0V
DS(ON)
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 3. On-Resistance Variation
with Temperature.
Figure 5.Transfer Characteristics.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.0001
0.001
0.01
0.1
1
10
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125C
A
25C
-55C
V = 0V
GS
SD
S
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
-50
-25
0
25
50
75
100
125
150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 10 V
GS
I = 2.5 A
D
R , NORMALIZED
DS(ON)
2
4
6
8
10
0.05
0.1
0.15
0.2
0.25
0.3
V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
T = 25C
A
I = 1.3A
D
T = 125C
A
1
2
3
4
5
6
0
2
4
6
8
10
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
GS
25C
125C
V = 5V
DS
D
T = -55C
A
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
SI3948DV Rev.A
Figure 10. Single Pulse Maximum Power
Dissipation.
0.1
0.5
1
2
5
10
30
10
20
50
100
200
500
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C iss
f = 1 MHz
V = 0V
GS
C oss
C rss
Figure 8. Capacitance Characteristics
.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics
(continued)
0
1
2
3
4
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 2.5A
D
10V
15V
V = 5V
DS
0.1
0.3
1
3
10
30
50
0.01
0.03
0.1
0.3
1
3
10
30
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
RDS(ON) LIMIT
V = 10V
SINGLE PULSE
R =180C/W
T = 25C
GS
A
JA
DC
1s
10ms
100ms
1ms
100us
0.01
0.1
1
10
100
300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =180C/W
T = 25C
A
JA
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
0.0001
0.001
0.01
0.1
1
10
100
300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(t), NORMALIZED EFFECTIVE
Duty Cycle, D = t / t
1
2
T - T = P * R (t)
JA
A
J
P(pk)
t
1
t
2
R (t) = r(t) * R
R =180C/W
JA
JA
JA
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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