SPT5400
13-BIT, OCTAL VOLTAGE-OUTPUT DAC
WITH PARALLEL INTERFACE
FEATURES
Full 13-bit performance without external adjustments
Eight DACs in one package
Buffered voltage outputs
Guaranteed monotonic to 13 bits
Unipolar or bipolar output swing to
4.5 V
Output settling time of 7
s to
1/2 LSB
Double-buffered digital inputs
APPLICATIONS
Automatic test equipment
Flat-panel displays
Arbitrary function generators
Instrumentation
Process control
DESCRIPTION
The SPT5400 has eight 13-bit voltage output digital-to-
analog converters on one chip. It operates from
5 V
power supplies and has maximum voltage output swings
of up to
4.5 V without the addition of external compo-
nents. Novel circuit topology allows for a guaranteed
monotonicity of 13 bits without the need for additional
circuitry. The SPT5400 has four separate reference volt-
age inputs, one for each pair of DACs. Four separate
analog ground pins allow for separate offset voltages for
each DAC pair. Each DAC can be asynchronously loaded
through a common 13-bit bus into a double-buffered set
of latches. All logic inputs are TTL/CMOS compatible.
The SPT5400 is available in a 44-lead PLCC package
over the commercial temperature range of 0
C to
+70
C.
+
DAC H
DAC
LATCH H
INPUT
LATCH H
+
DAC G
DAC
LATCH G
INPUT
LATCH G
+
DAC F
DAC
LATCH F
INPUT
LATCH F
+
DAC E
DAC
LATCH E
INPUT
LATCH E
+
DAC D
DAC
LATCH D
INPUT
LATCH D
+
DAC C
DAC
LATCH C
INPUT
LATCH C
+
DAC B
DAC
LATCH B
INPUT
LATCH B
+
DAC A
DAC
LATCH A
INPUT
LATCH A
D12D0
CS
WR
A0A2
LDAB
LDCD
LDEF
LDGH
CLR
V
SS
GND
V
OUT
A
AGNDAB
V
OUT
B
V
OUT
C
AGNDCD
V
OUT
D
V
OUT
E
AGNDEF
V
OUT
F
V
OUT
G
AGNDGH
V
OUT
H
REFAB
REFCD
REFEF REFGH
V
DD
CONTROL
LOGIC
DATA BUS
BLOCK DIAGRAM
2
5/15/00
SPT5400
ELECTRICAL SPECIFICATIONS
V
DD
= +5 V, V
SS
= 5 V, REFxx = 4.096 V, AGNDxx = GND = 0 V, R
L
= 10 k
, C
L
= 50 pF, T
A
= T
MIN
to T
MAX
, unless otherwise
specified. Typical values are at T
A
= +25
C.
TEST
TEST
SPT5400
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
DC Performance
Resolution
13
Bits
Integral Linearity
VI
0.5
4.0
LSB
Differential Linearity
Guaranteed Monotonic
VI
1.0
LSB
Zero Code Error
1
VI
10.0
20
LSB
Gain Error
2
VI
1.0
15
LSB
Power Supply Rejection Ratio
3
Gain/
V
DD
VI
0.0025
%/%
Gain/
V
SS
VI
0.0025
%/%
Load Regulation
R
L
=
to 10 k
V
0.4
LSB
Reference Input
Ref Input Range
4,5
IV
AGND
V
DD
V
Ref Input Resistance
5
VI
5
k
Analog Output
Maximum Output Voltage
V
V
DD
0.5
V
Minimum Output Voltage
V
V
SS
+ 0.5
V
Output Slew Rate
V
2.4
V/
s
Output Settling Time
6
To
1/2 LSB of Full Scale
V
7.0
s
Digital Feedthrough
V
5
nV-s
Digital Crosstalk
V
50
nV-s
Digital Inputs (V
DD
= 5 V
5%)
Input Voltage High
VI
2.4
V
Input Voltage Low
VI
0.8
V
Input Current (V
IN
= 0 V or V
DD
)
VI
10.0
A
Input Capacitance
IV
10
pF
Power Supplies
Positive Supply Range (V
DD
)
VI
4.75
5.25
V
Negative Supply Range (V
SS
)
VI
5.25
4.75
V
Positive Supply Current
VI
15
25
mA
Negative Supply Current
VI
16
25
mA
Power Dissipation
7
VI
155
250
mW
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
C
Note 1: Operation at any Absolute Maximum Rating is not implied. Operation beyond the ratings may cause damage to the
device. See Electrical Specifications for proper nominal applied conditions in typical applications.
Supply Voltages
V
DD
to GND ............................................. 0.3 to +6 V
V
SS
to GND ............................................. 6 to +0.3 V
AGNDxx ..................... (GND 0.3 V) to (V
DD
+ 0.3 V)
Input Voltages
Digital Input Voltage to GND .. 0.3 V to (V
DD
+ 0.3 V)
REFxx .................. (AGNDxx 0.3 V) to (V
DD
+ 0.3 V)
Maximum Current into REFxx Pin .................
10 mA
Output
V
OUT
xx ...................................................... V
DD
to V
SS
Temperature
Operating Temperature, Ambient .............. 0 to +70
C
Junction Temperature .................................... +165
C
Lead Temperature, (soldering 10 seconds) ... +300
C
Storage Temperature .......................... 65 to +150
C
Power Dissipation ....................................... 1000 mW
1
Deviation of actual DAC output when all 0s are loaded to the DAC from the ideal output of 4.096 V.
2
Deviation of actual DAC output span from the ideal span of 8.191 V.
3
PSSR is tested by changing the respective supply voltage by
5%.
4
For best performance, REF should be greater than AGND + 2 V and less than V
DD
0.6 V. The device operates
with reference inputs outside this range, but performance may degrade.
5
Reference input resistance is code dependent.
6
Typical settling time with 1000 pF capacitive load is 8
s.
7
Does not include reference power.
3
5/15/00
SPT5400
TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifi-
cations are guaranteed. The Test Level
column indicates the specific device
testing actually performed during pro-
duction and Quality Assurance inspec-
tion. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at T
A
= +25
C, and sample tested at the
specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at T
A
= +25
C. Parameter is guaranteed over
specified temperature range.
Figure 1 Timing Diagram
t
5
t
1
t
6
t
2
t
9
t
10
t
7
t
8
t
4
t
3
A0A2
D0D12
LD
CS
WR
NOTES:
1. All input rise and fall times
are measured from 10% to
90% of +5 V. t
R
= t
F
= 5 ns.
2. If
LD
is activated while
WR
is
low,
LD
must stay low for t
3
or
longer after
WR
goes high.
Table I Timing Parameters
PARAMETER
SYMBOL
MIN TYP MAX
UNIT
CS
Pulse Width Low
t
1
50
ns
WR
Pulse Width Low
t
2
50
ns
LD
Pulse Width Low
t
3
50
ns
CLR
Pulse Width Low
t
4
100
ns
CS
to
WR
Low
t
5
0
ns
CS
High to
WR
High
t
6
0
ns
Data Valid to
WR
Setup
t
7
20
ns
Data Valid to
WR
Hold
t
8
0
ns
Address Valid to
WR
Setup
t
9
10
ns
Address Valid to
WR
Hold
t
10
0
ns
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5/15/00
SPT5400
GENERAL CIRCUIT DESCRIPTION
The SPT5400 contains eight 13-bit, voltage-output
DACs. It uses a novel circuit topology to convert the
13-bit digital inputs into equivalent output voltages that
are proportionate to the applied reference voltages. The
SPT5400 has four separate reference voltage (REFxx)
and analog ground (AGNDxx) inputs for each DAC pair.
The REFxx inputs allow for separate full-scale output
voltages for each DAC pair. The AGNDxx inputs allow for
separate offset voltages for each DAC pair.
VOLTAGE REFERENCE AND ANALOG
GROUND INPUTS
The REFxx and AGNDxx inputs set the output range of
the corresponding DAC pair. For a detailed description of
the relationship between the DAC output range and the
REFxx and AGNDxx input voltages, see the Analog Out-
puts section of this datasheet.
The reference input impedance is code dependent. It is at
its highest value when the input code of the correspond-
ing DAC pair is all 1s. It is at its lowest value when the
input code is all 0s. Because the input impedance is code
dependent, load regulation of the reference is critical.
MULTIPLYING OPERATION
Because the reference of the SPT5400 accepts both AC
and DC signals, it can be used for multiplying applica-
tions. The REFxx inputs (which set the full-scale output
voltage for the respective DACs) only accept positive
voltages, so the multiplying operation is limited to two
quadrants. Note that when applying AC signals to the ref-
erence, do not bypass the inputs.
DIGITAL INPUTS AND
MICROPROCESSOR INTERFACE
All digital inputs are TTL/CMOS compatible. The
SPT5400 is compatible with microprocessors having a
minimum 13-bit-wide data bus. The microprocessor inter-
face is double-buffered to allow all the DACs to be simul-
taneously updated.
DAC ADDRESSING AND LATCHING
Each DAC has an input latch that receives data from the
data bus, and a DAC latch that receives data from the
input latch. The address lines (A0A2) for each DAC in-
put latch are shown in table II. Data is transferred from
the input latch to the DAC latch when
LD
xx is asserted.
The analog output of each DAC reflects the data held in
its corresponding DAC latch. In addition to being latched,
data can be transferred to the DAC directly through
transparent latches.
Table II DAC Addressing
A2
A1
A0
Function
0
0
0
DAC A input latch
0
0
1
DAC B input latch
0
1
0
DAC C input latch
0
1
1
DAC D input latch
1
0
0
DAC E input latch
1
0
1
DAC F input latch
1
1
0
DAC G input latch
1
1
1
DAC H input latch
The control inputs of the SPT5400 are level triggered,
and are shown in table III. The input latch is controlled by
CS
and
WR
, and the transfer of data to the DAC latch is
controlled by
LD
xx. When
CS
and
WR
are low, the input
latch is transparent. When
LD
xx is low the DAC latch is
transparent. To avoid transferring data to the wrong DAC,
the address lines (A0A2) must be valid through the time
CS
and
WR
are low. See the timing diagram for specific
timing values. When
CS
and
WR
are high, the data is
latched into the input latch. When
LD
xx is high, the data is
latched into the DAC latch. If
LD
xx is low when
CS
and
WR
are low, then it must be held low for t
3
or longer after
CS
or
WR
goes high.
When
CLR
is low, all DAC outputs are set to their corre-
sponding AGNDxx. When
CLR
toggles from low to high,
1000hex is latched into all input and DAC latches.
Table III Interface Truth Table
CLR LD
xx
WR
CS
Function
1
0
0
0
Both latches transparent
1
1
1
x
Both latches latched
1
1
x
1
Both latches latched
1
x
0
0
Input latch transparent
1
x
1
x
Input latch latched
1
x
x
1
Input latch latched
1
0
x
x
DAC latch transparent
0
x
x
x
All input and DAC latches at
1000hex, outputs at AGNDxx
DIGITAL CODE
The SPT5400 uses offset binary coding. Conversion to a
13-bit offset binary code from a 13-bit twos-complement
code can be achieved by adding 2
12
= 4096.
5
5/15/00
SPT5400
POWER SUPPLY SEQUENCING
The required power-up sequence is as follows: V
SS
(or
V
DD
) first, V
DD
(or V
SS
) second, and then REF_. The
sequence in which V
DD
and V
SS
come up is not critical.
However, REF_ must come up after V
DD
and V
SS
are
established.
Fairchild strongly recommends that the digital input pins
be driven only after V
DD
and V
SS
are established. Driving
a digital input prior to establishing supplies will violate a
condition outlined in the Input Voltages section (see the
Absolute Maximum Ratings on page 2 of this data sheet)
and cause damage to the part. If either REF_ or the digi-
tal inputs must come up before V
DD
and V
SS
, due to sys-
tem constraints, limit the current to the REF_ or digital
input pins to less than 1 mA.
This recommended power-up sequence must be
executed in reversed order for power-down. It should be
noted that none of the Absolute Maximum Rating condi-
tions are violated during power-up and power-down.
ANALOG OUTPUTS
The voltage outputs to the SPT5400 are buffered inter-
nally by precision amplifiers with a 2.4 V/
s typical slew
rate. The typical settling time to
1/2 LSB, with a full-
scale transition at the outputs, is 7
s. Each DAC output
is protected against a short to GND or AGNDxx. The typi-
cal short-circuit currents are 25 mA when the DAC is
at positive full scale, and 2.5 mA when the DAC is at
negative full scale.
BIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = 0 V)
For symmetrical bipolar operation, AGNDxx should be
tied to the system ground. The relationship between the
output voltage and the digital code is shown in table IV.
The output voltage of the DAC ladder (VDAC) is multi-
plied by 2 and level-shifted by the reference voltage. The
output voltage of the amplifier is given by the following
equation:
V
OUT
= 2(VDAC) REFxx
Where VDAC is the voltage at the noninverting input of
the amplifier and REFxx is the voltage at the reference
input of the DAC.
With AGNDxx connected to the system ground, the out-
put voltage of the DAC ladder is:
VDAC = (D/2
13)
REFxx
Where D is the numeric value of the DAC's binary input
code.
Replacing VDAC in the equation gives the output
voltage.
V
OUT
xx=2
D
2
REFxx
REFxx
REFxx
D
2
REFxx
D
4096
13
12
(
)
-
=
-
=
-
1
1
1 LSB = REFxx
1
4096
D ranges from 0 to 8191 (2
13
1).
Table IV Input Code/Output Tables
Bipolar (AGNDxx = 0 V)
Input
Output
1 1111 1111 1111
+REFxx (4095/4096)
1 0000 0000 0001
+REFxx (1/4096)
1 0000 0000 0000
0 V
0 1111 1111 1111
REFxx (1/4096)
0 0000 0000 0001
REFxx (4095/4096)
0 0000 0000 0000
REFxx
Positive Unipolar (AGNDxx = REFxx/2)
Input
Output
1 1111 1111 1111
+REFxx (8191/8192)
1 0000 0000 0000
+REFxx/2
0 0000 0000 0000
0 V
POSITIVE UNIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = REFxx/2)
For positive unipolar operation, AGNDxx should be set to
REFxx/2. The relationship between the output voltage
and the digital code is shown in table IV. For example, if a
4.096 V reference is used, AGNDxx should be offset by
2.048 V. This results in a unipolar output voltage of 0 to
4.0955 V, where 1 LSB = 500
V. the maximum current
out of any AGNDxx pin is:
I
REFxx
AGNDxx
5 k
AGNDXX
=
-
CUSTOM OUTPUT VOLTAGE RANGE
If the voltage at the REFxx input is higher than the volt-
age at the AGNDxx input, the AGNDxx inputs can be off-
set by any voltage within the supply rails. One way to
achieve this is to add positive offset to AGNDxx by select-
ing the reference voltage and the voltage at AGNDxx
such that the resulting output voltages do not come within
0.5 V of the supply rails. Another way is to digitally offset
AGNDxx by connecting one DAC output to one or more
AGNDxx inputs. Note that a DAC output should not be
connected to its own AGNDxx input.
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