VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

LEA7

LEA6

LEA5

LEA4

LEA3

LEA2

LEA1

LEA0

Control

Logic

A0A2

LDAC

LEA0LEA7

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

REFT01

REFB01

CLR

RGND

D0D12

LDAC

REFT2345

REFB2345

REFT67

REFB67

LDAC

SPT5420

13-BIT, OCTAL D/A CONVERTER

TECHNICAL DATA

JUNE 26, 2001

FEATURES

� 13-bit resolution
� Pin compatible with AD7839
� Eight DACs in one package
� Buffered voltage outputs
� Wide output voltage swing V

�2.5 V to V

+2.5 V

� 15 �s settling time to �0.5 LSB
� Double-buffered digital inputs
� Microprocessor and TTL/CMOS compatible

APPLICATIONS

� Automatic test equipment
� Instrumentation
� Process control

GENERAL DESCRIPTION

The SPT5420 contains eight 13-bit digital-to-analog
CMOS converters designed primarily for automatic test
equipment applications. It uses novel circuit topology to
convert the 13-bit digital inputs into output voltages which
are proportionate to the applied reference voltages. Each

DAC's full-scale output voltage and output voltage offset
are adjustable with analog inputs (RGND, V

REFB

, V

REFT

The SPT5420 operates over an industrial temperature
range of �40 �C to +85 �C and is available in a 10 x 10 mm,
44-lead metric quad flat pack (MQFP) plastic package.

BLOCK DIAGRAM

6/26/01

SPT5420

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)

25 �C

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions
in typical applications.

ELECTRICAL SPECIFICATIONS

= T

MIN

to T

MAX

, V

= +5.0 V, V

= +11.5 V, V

= �8.0 V, V

REFT

=3.5 V, V

REFB

= �1.5 V, R

= +10 k

, C

= 50 pF, unless otherwise specified.

TEST

SPT5420

PARAMETERS

CONDITIONS

LEVEL

MIN

TYP

MAX

UNITS

Accuracy

Resolution

Bits

Integral Linearity Error (ILE)

�2.0

�0.5

+2.0

LSB

Differential Linearity Error (DLE)

�1.0

�0.3

+1.0

LSB

Zero-Scale Error

�25

+25

Full Scale Error

�25

+25

Gain Error

�25

+25

Reference Inputs

Input Current

�100

REFT1

+3.5

+5.0

REFB2

�5.0

�1.5

RGND Inputs

DC Input Impedance

Input Range

�2.0

2.0

Output Characteristics

Output Swing

3,4

+7/�3

Short Circuit Current

Resistive Load

DC Output Impedance

1.0

Digital Inputs

Logic 1 Voltage

2.4

Logic 0 Voltage

0.8

Maximum Input Current

�10

�A/pin

Input Capacitance

Supply Voltages

........................................................................ +6 V

...................................................................... +15 V

...................................................................... �15 V

Input Voltages

REFT

.................................... V

�0.3 V to V

+0.3 V

REFB

................................... V

+0.3 V to V

�0.3 V

Digital inputs .................................... �0.3 V to V

+0.3 V

Temperature

Operating Temperature .......................... �40 to +85 �C
Storage ................................................ �65 to +150 �C

Notes:
1. V

REFT

< 8 V + (V

x 0.5); e.g., if V

= �8 V, then V

REFT

< 4 V

2. V

REFB

> (V

x 0.5) � 9.5 V; e.g., if V

= 11 V, then V

REFB

> �4 V

3. V

+ 2.5 V

OUT

+ 16.0 V for 18.5 V

� V

20.0 V

+ 2.5 V

OUT

� 2.5 V for V

� V

18.5 V

4. V

OUT

= 2 X (V

REFB

+[V

REFT

� V

REFB

] X

INPUT CODE

8192

) � V

RGND

6/26/01

SPT5420

TEST LEVEL CODES

All electrical characteristics are subject to the
following conditions:

All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.

LEVEL

TEST PROCEDURE

100% production tested at the specified temperature.

100% production tested at T

= +25 �C, and sample tested at the

specified temperatures.

III

QA sample tested only at the specified temperatures.

Parameter is guaranteed (but not tested) by design and characteri-
zation data.

Parameter is a typical value for information purposes only.

100% production tested at T

= +25 �C. Parameter is guaranteed

over specified temperature range.

ELECTRICAL SPECIFICATIONS

= T

MIN

to T

MAX

, V

= +5.0 V, V

= +11.5 V, V

= �8.0 V, V

REFT

=3.5 V, V

REFB

=�1.5 V, R

= +10 k

, C

= 50 pF, unless otherwise specified.

TEST

SPT5420

PARAMETERS

CONDITIONS

LEVEL

MIN

TYP

MAX

UNITS

Power Requirements

Supply Voltage (Digital)

4.75

5.25

Supply Voltage (Analog)

1,2

11.5

12.5

Supply Voltage (Analog)

1,2

�12.5

�8

�5

Supply Current

0.5

Supply Current

Outputs Unloaded

Supply Current

Outputs Unloaded

Power Supply Rejection Ratio

Full Scale

Dynamic Performance

Output Settling Time

(Full Scale Change to �0.5 LSB) C

220 pF

�s

Slew Rate

2.0

V/�s

Glitch Impulse

nV-s

Channel to Channel Isolation

100

DAC to DAC Crosstalk

nV-s

Digital Crosstalk

nV-s

Digital Feedthrough

nV-s

Timing Characteristics

(See page 4)

1. Supplies should provide 2.5 V headroom above and below max output swing.
2. V

� V

20 V

3. Output can drive 10,000 pF without oscillation, but with settling time degradation.

DEFINITION OF SELECTED TERMINOLOGY

Channel-to-Channel Isolation

Channel-to-Channel isolation refers to the proportion of input signal from one DAC's reference input that appears at the output of
the other DAC. It is expressed in dBs.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is defined as the glitch impulse that appears at one DAC's output due to both the digital change and subse-
quent analog output change at any other DAC. It is specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to one DAC's output due to a change in digital input code of any other DAC. It is specified in nV-s.

Digital Feedthrough

Digital feedthrough is the noise at a DAC's output caused by changes to D0�D12 while

is high.

6/26/01

SPT5420

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Address Valid to

Setup

Address Valid to

Hold

Pulse Width Low

Setup

Hold

Data Setup

Data Hold

Settling Time

LDAC

Pulse Width Low

CLR

Pulse Activation

300

NOTES:
All digital input rise and fall times are measured from 10% to 90% of +5 V.
t

= t

= 5 ns.

1. R

= 10 k

220 pF

TIMING CHARACTERISTICS

A0A2

D0D12

LDAC

OUT

A0A2

D0D12

OUT

CLR

OUT

Figure 1a � Timing Diagram: Latched Mode

(

LDAC

Strobed)

Figure 1b � Timing Diagram: Transparent Mode

(

LDAC

Held Low)

6/26/01

SPT5420

VOLTAGE REFERENCES AND
ANALOG GROUND INPUTS

Three V

REFTXX

and three V

REFBXX

inputs set the output

range of the three corresponding groups of DACs
(0 and 1; 2 through 5; 6 and 7). Four RGND

inputs set

the output offset voltage of the four corresponding groups
of DACs (0 and 1; 2 and 3; 4 and 5; 6 and 7). The formula
for output swing and offset is presented in the "Analog
Outputs" section below.

DAC ADDRESSING AND LATCHING

Each DAC has an input latch which receives data from the
data bus, and a DAC latch which receives data from the
input latch. The analog output of each DAC corresponds
to the data in its DAC latch. One of the eight input latches
is addressed by the address lines A(2:0) according to
Table I. While

and

are low, the addressed input

latch is transparent and the seven other input latches are
latched. Bringing

high latches data into the ad-

dressed input latch. While

LDAC

is low, all eight DAC

latches are transparent. Bringing

LDAC

high latches data

into the DAC latches. While

and

LDAC

are low, both

latches are transparent and input data is transferred
directly to the selected DAC. While

CLR

is low, all DAC out-

puts are set to their corresponding RGND

. Bringing

CLR

high returns each DAC's output to the voltage correspond-
ing to the data in each DAC latch.

Table II summarizes this information, and figures 1a and
1b should be referenced for timing limitations.

POWER SUPPLY SEQUENCING

The sequence in which V

, V

and V

come up is not

critical. The reference inputs, V

REFTXX

and V

REFBXX

, must

come on only after V

and V

have been established.

However, they may be turned on prior to V

. The digital

inputs must be driven only after V

, V

and V

have

been established. Reverse the power-on sequence for
power-down.

ANALOG OUTPUTS VS DIGITAL INPUT
CODE

The output voltage range is equal to twice the difference
between V

REFTXX

and V

REFBXX

. The output voltage is

given by:

OUT

= 2 X (V

REFB

+[V

REFT

� V

REFB

] X

INPUT CODE

8192

) � V

RGND

CODE = 0 � 8191

Table I � DAC Addressing

Addressed Input

Latch DAC#

Table II � Control Logic Table

LDAC

CLR

Input Latch DAC Latch

transparent

latched

transparent

latched

DAC outputs at RGND

Note:
1. Only the input latch addressed by A(2:0) is transparent.

The other input latches are latched.

Электронный компонент: SPT5420SIM