SPT7610
6-BIT, 1 GSPS FLASH A/D CONVERTER
JANUARY 21, 2002
FEATURES
1:2 demuxed ECL-compatible outputs
1.0 GSPS conversion rate
Wide input bandwidth: 1.4 GHz
Low input capacitance: 8 pF
Metastable errors reduced to 1 LSB
Monolithic construction
Binary/Two's complement output
APPLICATIONS
Radar, EW, ECM
Direct RF down-conversion
Microwave modems
Industrial ultrasound
Transient capture
Test and measurement
GENERAL DESCRIPTION
The SPT7610 is a full parallel (flash) analog-to-digital con-
verter capable of digitizing full-scale (0 to 1 V) inputs into
six-bit digital words at an update rate of 1 GSPS. The
ECL-compatible outputs are demultiplexed into two sepa-
rate output banks, each with differential data-ready out-
puts to ease the task of data capture. The SPT7610's wide
input bandwidth and low capacitance eliminate the need
for external track-and-hold amplifiers for most applica-
tions. A proprietary decoding scheme reduces metastable
errors to the 1 LSB level. The SPT7610 operates from a
single 5.2 V supply, with a nominal power dissipation of
2.75 W.
The SPT7610 is available in a 44L hermetic cerquad
surface-mount package in the industrial temperature
range (40 C to +85 C).
64
63
49
48
33
32
17
16
2
1
CLOCK
BUFFER
64
T
O
6 BIT DECODER
WITH MET
AST
ABLE ERR
OR CORRECTION
DO
(LSB)
D1
D2
D3
D4
D5
(MSB)
D6
(OVR)
V
RT
Analog
Input
Preamp
Comparator
V
RM
V
RB
CLKCLK
DEMUX
CLOCK
BUFFER
1:2 DEMUL
TIPLEXER
ECL OUTPUT B
UFFERS AND LA
TCHES
DRB (DATA READY)
DRB (DATA READY)
D6B (OVR)
D5B (MSB)
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D6A (OVR)
D5A (MSB)
D4A
D3A
D2A
D1A
D0A (LSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B
D6A
D5A
D4A
D3A
D2A
D1A
D0A
BANK B
BANK A
V
R1
V
R3
MINV
LINV
TESTA-
BILITY
TEST
BLOCK DIAGRAM
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1/21/02
SPT7610
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 C
Supply Voltages
Negative Supply Voltage (AV
EE
TO GND) . 7.0 to +0.5 V
Ground Voltage Differential ........................ 0.5 to +0.5 V
Input Voltage
Analog Input Voltage ................................ +0.5 V to AV
EE
Reference Input Voltage ........................... +0.5 V to AV
EE
Digital Input Voltage .................................. +0.5 V to AV
EE
Reference Current V
RT
to V
RB
............................ +20 mA
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
Output
Digital Output Current ................................... 0 to 25 mA
Temperature
Operating Temperature, Ambient ............... 40 to +85 C
Lead Temperature, (soldering 10 seconds) ........ +300 C
Storage Temperature ............................... 65 to +150 C
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, AV
EE
= 5.2 V, V
RB
= 1.00 V, V
RM
= 0.5 V, V
RT
= 0.00 V,
CLK
= 1000 MSPS, Duty Cycle = 50%, unless otherwise specified.
TEST
TEST
SPT7610
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Resolution
6
Bits
DC Accuracy
Integral Linearity
VI
0.5
+0.5
LSB
Differential Linearity
VI
0.5
+0.5
LSB
No missing codes
VI
Guaranteed
Analog Input
Offset Error V
RT
VI
30
+30
mV
Offset Error V
RB
VI
30
+30
mV
Input Voltage Range
VI
1
0.0
Volts
Input Capacitance
Over Full Input Range
V
8
pF
Input Resistance
V
50
k
Input Bias Current
VI
200
400
A
Bandwidth
Small Signal
V
1.4
GHz
Input Slew Rate
V
5
V/ns
Clock Synchronous Input Currents
V
2
A
Power Supply Requirements
Supply Current
VI
550
770
mA
Power Dissipation
VI
2.85
4.0
W
Reference Inputs
Ladder Resistance
VI
60
80
120
Reference Bandwidth
V
100
MHz
Digital Outputs
Digital Output High Voltage
R
1
= 50
to 2 V
VI
1.2
0.9
Volts
Digital Output Low Voltage
R
1
= 50
to 2 V
VI
1.8
1.5
Volts
Digital Inputs
Digital Input High Voltage
(CLK, NCLK)
VI
1.1
0.7
Volts
Digital Input Low Voltage
(CLK, NCLK)
VI
2.0
1.5
Volts
Clock Input Swing
(CLK, NCLK)
IV
100
700
mV
Maximum Sample Rate
VI
1000
1200
MSPS
Clock Low Width, TPW0
VI
0.5
0.4
ns
Clock High Width, TPW1
VI
0.5
0.4
ns
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1/21/02
SPT7610
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, AV
EE
= 5.2 V, V
RB
= 1.00 V, V
RM
= 0.5 V, V
RT
= 0.00 V,
CLK
= 1000 MSPS, Duty Cycle = 50%, unless otherwise specified.
TEST
TEST
SPT7610
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Timing Characteristics
Clock to Data Ready delay (t
dr
)
Data Bank A
+25 C case
V
1.68
ns
Data Bank B
+25 C case
V
1.73
ns
Clock to Output Data (t
od
)
Data Bank A
+25 C case
V
2.14
ns
Data Bank B
+25 C case
V
2.00
ns
Output Data to Data Ready (t
odr
)
Data Bank A
40 to 85 C case
IV
1.54
ns
Data Bank B
40 to 85 C case
IV
1.73
ns
Output Data Skew (t
osk
)
40 to 85 C case
IV
150
150
ps
Aperture Jitter
V
2
ps
Acquisition Time
V
250
ps
Dynamic Performance
Spurious Free Dynamic Range (SFDR)
IN
= 250 MHz
V
45
dB
IN
= 400 MHz
V
34
dB
Signal-to-Noise and Distortion (SINAD)
IN
= 250 MHz
VI
31
34
dB
IN
= 400 MHz
VI
28
32
dB
Signal to Noise Ratio (SNR)
IN
= 250 MHz
VI
33
36
dB
IN
= 400 MHz
VI
32
36
dB
Total Harmonic Distortion (THD)
IN
= 250 MHz
VI
40
37
dB
IN
= 400 MHz
VI
34
30
dB
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all test are pulsed
tests; therefore, T
J
= T
C
= T
A
.
LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at T
A
= +25 C, and sample tested at the
specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at T
A
= +25 C. Parameter is guaranteed
over specified temperature range.
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1/21/02
SPT7610
GENERAL OVERVIEW
The SPT7610 is an ultra high-speed monolithic 6-bit
parallel flash A/D converter. The nominal conversion rate
is 1 GSPS, and the analog bandwidth is typically 1.4 GHz.
A major advance over previous flash converters is the
inclusion of 64 input preamplifiers between the reference
ladder and input comparators. (See the block diagram.)
This not only reduces clock transient kickback to the input
and reference ladder due to a low AC beta but also
reduces the effect of the dynamic state of the input signal
on the latching characteristics of the input comparators.
The preamplifiers act as buffers and stabilize the input
capacitance so that it remains constant over different
input voltage and frequency ranges. This makes the part
easier to drive than previous flash converters. The pre-
amplifiers also add a gain of two to the input signal so that
each comparator has a wider overdrive or threshold range
to "trip" into or out of the active state. This gain reduces
metastable states that can cause errors at the output.
The SPT7610 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise. Signature errors are also
reduced by careful layout of the analog circuitry. The out-
put drive capability of the device can provide full ECL
swings into 50
loads.
Only one 5.2 V power supply is required. Two external
references are applied across the internal reference lad-
der that has a resistance of 80
typical (60
minimum).
The top reference is typically 0 V or connected to AGND
(analog ground). The device has top force and sense pins
(V
RFT
and V
RST
) that are internally connected together.
These voltage force and sense pins can be used to mini-
mize the voltage drop across the parasitic line resistance.
The bottom reference is typically 1 V. The device also has
bottom force and sense pins (V
RFB
and V
RSB
) that are
internally connected together. These can also be used to
minimize the voltage drop across the parasitic line resis-
tance. Three additional reference taps (V
R3
= 0.25 V typ,
V
RM
= 0.5 V typ, and V
R1
= 0.75 V typ) are brought out.
These taps can be used to control the linearity error.
All logic levels are compatible with both 10K ECL or 100K
ECL. It is recommended that the clock input be driven
differentially (CLK and NCLK) to improve noise immunity
and reduce aperture jitter.
The digital outputs are split into two banks of 6-bit words
and an overrange bit. Each bank is updated at 1/2 of the
clock rate and is 180 out of phase from the other. The dif-
ferential data ready signals for each bank are provided to
accurately latch each data bank into the register. The out-
put data is in a straight binary, inverted binary, two's
complement or inverted two's complement format. Figure
1 shows a timing diagram of the device and shows the in-
put-to-output relationship, clock-to-output delay and out-
put latency. The SPT7610 has a built-in offset in the 2
clock divider (D Flip-Flop) to assure that output bank A will
come up first after power turn on.
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1/21/02
SPT7610
Figure 1 Timing Diagram
2
FIRST
RISING EDGE
POWER
ON
8
OUTPUT
BANK A
(DA0-6)
OUTPUT
BANK B
(DB0-6)
DRA
CLK IN
DRB
VIN
NDRA
NDRB
TEST
3
5
4
2
1
6
INVALID DATA
1
ADC (Normal Operation)
9
10
11
8
TEST MODE
7
t
su
t
dr
t
od
t
dr
t
od
ADC (Normal Operation)
INVALID DATA
INVALID DATA
INVALID DATA
7
9
Bank A Test Pattern 1:
- Even Bits = Hi
- Odd Bits = Low
Bank B Test Pattern 1:
- Even Bits = Hi
- Odd Bits = Low
Bank A Test Pattern 2:
- Even Bits = Low
- Odd Bits = Hi
Bank B Test Pattern 2:
- Even Bits = Low
- Odd Bits = Hi
LOGIC LOW
Figure 2 Test Mode Timing Diagram
CLK (1 GHz)
DRA
DRA
Data Bank A
DRB
DRB
Data Bank B
V
IN
N
N+1
N+2
N+3
N+4
1 nsec
t
odB
t
drB
t
drA
N2
N
t
odA
N1
N3
OutputB Skew
(t
oskB
)
N+1
N+2
DOBDRB Delay
(t
odrB
)
OutputA Skew
(t
oskA
)
DOADRA Delay
(t
odrA
)
N+5
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