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2004 Fairchild Semiconductor Corporation
S
S
M1N45B
Rev. A, May 2004
SSM1N45B
450V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic ballasts based on half bridge
configuration.
Features
0.5A, 450V, R
DS(on)
= 4.25
@V
GS
= 10 V
Low gate charge ( typical 6.5 nC)
Low Crss ( typical 6.5 pF)
100% avalanche tested
Improved dv/dt capability
Gate-Source Voltage
50V guaranteed
Absolute Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Symbol
Parameter
SSM1N45B
Units
V
DSS
Drain-Source Voltage
450
V
I
D
Drain Current
- Continuous (T
C
= 25C)
0.5
A
- Continuous (T
C
= 100C)
0.32
A
I
DM
Drain Current
- Pulsed
(Note 1)
4.0
A
V
GSS
Gate-Source Voltage
50
V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
108
mJ
I
AR
Avalanche Current
(Note 1)
0.5
A
E
AR
Repetitive Avalanche Energy
(Note 1)
0.25
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
5.5
V/ns
P
D
Power Dissipation (T
A
= 25C)
0.9
W
Power Dissipation (T
L
= 25C)
2.5
W
- Derate above 25C
0.02
W/C
T
J
, T
stg
Operating and Storage Temperature Range
-55 to +150
C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300
C
Symbol
Parameter
Typ
Max
Units
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 6b)
--
63
C/W
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S
D
G
SOT-223
SSM Series
G
D
S
Rev. A, May 2004
S
S
M1N45B
2004 Fairchild Semiconductor Corporation
Electrical Characteristics
T
C
= 25C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 75mH, I
AS
= 1.6A, V
DD
= 50V, R
G
= 25
,
Starting T
J
= 25C
3. I
SD
0.5A, di/dt
300A/
s, V
DD
BV
DSS,
Starting T
J
= 25C
4. Pulse Test : Pulse width
300
s, Duty cycle
2%
5. Essentially independent of operating temperature
6. a) Reference point of the R
JL
is the drain lead
b) When mounted on the minimum pad size recommended (PCB Mount)
(R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance. R
CA
is determined by the user's board design)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250
A
450
--
--
V
BV
DSS
/
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25C
--
0.5
--
V/C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 450 V, V
GS
= 0 V
--
--
10
A
V
DS
= 360 V, T
C
= 125C
--
--
100
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 50 V, V
DS
= 0 V
--
--
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -50 V, V
DS
= 0 V
--
--
-100
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
2.3
3.0
3.7
V
V
DS
= V
GS
, I
D
= 250 mA
3.5
4.2
4.9
V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, I
D
= 0.25 A
--
3.4
4.25
g
FS
Forward Transconductance
V
DS
= 50 V, I
D
= 0.25 A
(Note 4)
--
0.7
--
S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
185
240
pF
C
oss
Output Capacitance
--
29
40
pF
C
rss
Reverse Transfer Capacitance
--
6.5
8.5
pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 225 V, I
D
= 0.5 A,
R
G
= 25
(Note 4,5)
--
7.5
25
ns
t
r
Turn-On Rise Time
--
21
50
ns
t
d(off)
Turn-Off Delay Time
--
23
55
ns
t
f
Turn-Off Fall Time
--
36
80
ns
Q
g
Total Gate Charge
V
DS
= 360 V, I
D
= 0.5 A,
V
GS
= 10 V
(Note 4,5)
--
6.5
8.5
nC
Q
gs
Gate-Source Charge
--
0.9
--
nC
Q
gd
Gate-Drain Charge
--
3.2
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
--
--
0.5
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
--
--
4.0
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.5 A
--
--
1.4
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
S
= 0.5 A,
dI
F
/ dt = 100 A/
s
(Note 4)
--
102
--
ns
Q
rr
Reverse Recovery Charge
--
0.26
--
C
Rev. A, May 2004
S
S
M1N45B
2004 Fairchild Semiconductor Corporation
10
-1
10
0
10
1
0
100
200
300
400
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
Note ;
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
Capaci
t
ance [
p
F]
V
DS
, Drain-Source Voltage [V]
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
V
DS
= 225V
V
DS
= 90V
V
DS
= 360V
Note : I
D
= 0.5 A
V
GS
,
G
a
t
e
-
S
our
ce
Vo
l
t
age [
V
]
Q
G
, Total Gate Charge [nC]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
10
-1
10
0
150
Notes :
1. V
GS
= 0V
2. 250s Pulse Test
25
I
DR
,
R
e
v
e
rs
e D
r
ai
n
Cur
r
ent
[
A
]
V
SD
, Source-Drain voltage [V]
0
1
2
3
4
5
0
2
4
6
8
10
12
V
GS
= 20V
V
GS
= 10V
Note : T
J
= 25
R
DS
(
O
N)
[
],
Dr
ai
n-
Sour
ce O
n
-
R
esi
s
t
anc
e
I
D
, Drain Current [A]
2
4
6
8
10
10
-1
10
0
Notes :
1. V
DS
= 50V
2. 250s Pulse Test
-55
150
25
I
D
, D
r
ain C
u
rren
t
[A]
V
GS
, Gate-Source Voltage [V]
10
-1
10
0
10
1
10
-1
10
0
V
GS
Top : 15.0 V
10.0 V
8.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Notes :
1. 250s Pulse Test
2. T
C
= 25
I
D
,
Dr
ai
n Cur
r
en
t
[
A
]
V
DS
, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
Figure 2. Transfer Characteristics
Figure 1. On-Region Characteristics
2004 Fairchild Semiconductor Corporation
S
S
M1N45B
Rev. A, May 2004
10
0
10
1
10
2
10
3
10
-3
10
-2
10
-1
10
0
10
1
10 ms
100 ms
1 s
100
s
DC
1 ms
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
,
D
r
ai
n Curr
ent
[
A
]
V
DS
, Drain-Source Voltage [V]
1 0
-5
1 0
-4
1 0
-3
1 0
-2
1 0
-1
1 0
0
1 0
1
1 0
2
1 0
3
1 0
- 1
1 0
0
1 0
1
1 0
2
N o te s :
1 . Z
JL
(t) = 5 0
/W M a x .
2 . D u ty F a c to r, D = t
1
/t
2
3 . T
JM
- T
L
= P
D M
* Z
J L
(t)
s in g le p u ls e
D = 0 .5
0 .0 2
0 .2
0 .0 5
0 .1
0 .0 1
Z
JL
(
t
),
Ther
m
a
l
Respon
se
t
1
, S q u a re W a v e P u ls e D u ra tio n [s e c ]
25
50
75
100
125
150
0.0
0.1
0.2
0.3
0.4
0.5
0.6
I
D
, D
r
ain
C
u
r
r
en
t [
A
]
T
C
, Case Temperature [ ]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS
= 10 V
2. I
D
= 0.25 A
R
DS
(
O
N)
, (N
o
r
m
a
li
ze
d)
Dr
a
i
n
-
So
ur
c
e
On
-R
es
i
s
t
a
nc
e
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS
= 0 V
2. I
D
= 250 A
BV
DSS
, (N
orm
a
li
z
e
d
)
D
r
ain-S
o
u
r
ce
B
r
ea
kdo
w
n V
o
l
t
a
g
e
T
J
, Junction Temperature [
o
C]
Typical Characteristics
(Continued)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Response Curve
t
1
P
DM
t
2
Rev. A, May 2004
S
S
M1N45B
2004 Fairchild Semiconductor Corporation
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=
L I
AS
2
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=
L I
AS
2
----
2
1
E
AS
=
L I
AS
2
----
2
1
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
L
I
D
I
D
t
p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
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