www.fairchildsemi.com

REV. 1.0.0 8/13/03

Features

· Multiple input formats

20 bit CCIR601
10 bit CCIR656
10 bit Digital Composite

· Synchronization modes

Master
Slave
Genlock
CCIR656

· Subcarrier modes

Free-run
Subcarrier reset
Genlock
DRS-lock

· Ancillary Data Control (ANC)
· Pixel rates from 10 MHz to 15 MHz
· Programmable horizontal timing
· Programmable vertical blanking interval (VBI)
· Line-by-line pedestal enable
· Programmable pedestal height from -20 IRE to 20 IRE
· Programmable burst amplitude and phase
· Controlled edge rates for

Sync
Burst
Active video

· Programmable color space matrix
· 8:8:8 video reconstruction
· Three 10 bit D/A's with independent trim
· Individual power down modes for each D/A
· Multiple output formats

S-video
Composite
Digital composite output

· Pin-driven and data-driven, window keying
· Closed Caption waveform generation (13.5 MHz only)
· Sin(X)/X compensation filter
· 5 bit VBI line counter
· 3 bit field counter
· Internal test pattern generation

100% Color Bars
75% Color Bars
Modulated Ramp

Applications

· Broadcast Television
· Nonlinear Video Processing

TMC2192

10 Bit Encoder

Block Diagram

PRE-

PROCESSER

SYNC

INSERT

KEY

MIX

PD[23:0]

OL[4:0]

CVBS[9:0]

Gain

Adjustment

KEY

FVHGEN

PXCK

HSIN

VSIN

DCVEN\

HSOUT

VSOUT

LINE[4:0]

FLD[2:0]

PDCIN/PDCOUT

MPU

RESET

SERB

D[7:0]

A[1:0]/SA[1:0]

CS/SCL

R/W\/SD

VREF

C BYPCOMP

CBYPLUMA

DAC
REF.

OVERLAY

MIXER

LUMA

CHROMA

COMPOSITE

RREF COMP

RREFCHROMA

RREF LUMA

Chroma

Modulator

2194001a

INTERP.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications. . . . . . . . . . . . . . . . . . . . . . . . .1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . .1

10 Bit Encoder . . . . . . . . . . . . . . . . . . . . . . .1

List of Figures . . . . . . . . . . . . . . . . . . . . . . .3

List of Tables . . . . . . . . . . . . . . . . . . . . . . . .3

Pin Assignments . . . . . . . . . . . . . . . . . . . . .4

Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .4

Functional Description . . . . . . . . . . . . . . . .7

Input Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Color Space Matrix . . . . . . . . . . . . . . . . . . . . . . 9

Synchronization Modes . . . . . . . . . . . . . . . . . 10

Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 10

Blanking Control . . . . . . . . . . . . . . . . . . . . . . . 11

Pixel Data Control . . . . . . . . . . . . . . . . . . . . . . 11

Edge Shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Horizontal Programming. . . . . . . . . . . . . . . . . 12

Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chrominance Processor . . . . . . . . . . . . . . . . . 21

Subcarrier Programming . . . . . . . . . . . . . . . 21

NTSC Subcarrier . . . . . . . . . . . . . . . . . 21
PAL Subcarrier . . . . . . . . . . . . . . . . . . . 21
PAL-M Subcarrier . . . . . . . . . . . . . . . . . 21

Subcarrier Synchronization . . . . . . . . . . . . . 22
SCH Phase Error Correction. . . . . . . . . . . . 22
Burst Envelope . . . . . . . . . . . . . . . . . . . . . . 23
Color-Difference Low-Pass Filters. . . . . . . . 23

Sync and Pedestal Insertion. . . . . . . . . . . . . . 23

Pedestal Enable . . . . . . . . . . . . . . . . . . . . . 23
Pedestal Height . . . . . . . . . . . . . . . . . . . . . . 24
Sync and Blank Insertion . . . . . . . . . . . . . . 24

Closed Caption Insertion . . . . . . . . . . . . . . . . 24

Line Selection . . . . . . . . . . . . . . . . . . . . . . . 24
Parity Generation . . . . . . . . . . . . . . . . . . . . 24
Operating Sequence . . . . . . . . . . . . . . . . . . 24

Interpolation Filters . . . . . . . . . . . . . . . . . . . . . 25

x/Sin(x) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Data Formats . . . . . . . . . . . . . . . . . . . . 25

Digital Composite Output . . . . . . . . . . . . . . . . 26

Ancillary Data. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Operating Modes. . . . . . . . . . . . . . . . . . . . . 27

Layering Engine. . . . . . . . . . . . . . . . . . . . . . . . 28

Overlay Mixer . . . . . . . . . . . . . . . . . . . . . . . 28

Hardware Keying . . . . . . . . . . . . . . . . . . . . . . . 29

Data Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Parallel Microprocessor Interface . . . . . . . . . 29

Serial Control Port (R-Bus) . . . . . . . . . . . . . . . 31

Data Transfer via Serial Interface . . . . . . . . 31
Serial Interface Read/Write Examples . . . . 31

Control Register Map . . . . . . . . . . . . . . . . 33

Control Register Definitions . . . . . . . . . . 35

Absolute Maximum Ratings . . . . . . . . . . . 60

Operating Conditions . . . . . . . . . . . . . . . . 60

Electrical Characteristics . . . . . . . . . . . . . 62

Switching Characteristics . . . . . . . . . . . . 62

System Performance Characteristics . . . 63

Applications Discussion . . . . . . . . . . . . . 63

Layout Considerations . . . . . . . . . . . . . . . . . . 64

Output Low-Pass Filters . . . . . . . . . . . . . . . . . 67

Mechanical Dimensions . . . . . . . . . . . . . . 71

100-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 71

Ordering Information . . . . . . . . . . . . . . . . 72

Life Support Policy . . . . . . . . . . . . . . . . . . 72

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

List of Figures

Figure 1.

Input Formats . . . . . . . . . . . . . . . . . . . . . .7

Figure 2.

24 bit Input Format . . . . . . . . . . . . . . . . . .7

Figure 3.

CCIR656 Input Format . . . . . . . . . . . . . . .8

Figure 4.

10 bit Input Format . . . . . . . . . . . . . . . . . .8

Figure 5.

20 bit 4:2:2 Input Format . . . . . . . . . . . . .8

Figure 6.

20 bit 4:4:4 Input Format . . . . . . . . . . . . .8

Figure 7.

Propagation Delay through the
Encoder . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 8.

Horizontal Timing . . . . . . . . . . . . . . . . . .13

Figure 9.

Horizontal Timing Vertical Blanking . . .13

Figure 10. Horizontal Timing 1st Half-line. . . . . . .14
Figure 11. Horizontal Timing 2nd Half-line . . . . . .14
Figure 12. NTSC Vertical Interval . . . . . . . . . . . . . .15
Figure 13. PAL Vertical Interval . . . . . . . . . . . . . . . .17
Figure 14. PAL-M Vertical Interval . . . . . . . . . . . . . .19
Figure 15. Burst Envelope . . . . . . . . . . . . . . . . . . . .23
Figure 16. Gaussian Filter Response . . . . . . . . . . .23
Figure 17. Interpolation Filter. . . . . . . . . . . . . . . . . .25
Figure 18. Interpolation Filter Passband

Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 19. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .25
Figure 20. Layering Engine . . . . . . . . . . . . . . . . . . .28
Figure 21. Overlay Outputs . . . . . . . . . . . . . . . . . . .29
Figure 22. Data Keying . . . . . . . . . . . . . . . . . . . . . .29
Figure 23. Microprocessor Parallel Port

Write Timing . . . . . . . . . . . . . . . . . . . . . .30

Figure 24. Microprocessor Parallel Port

Read Timing . . . . . . . . . . . . . . . . . . . . . .30

Figure 25. Serial Port Read/Write Timing . . . . . . . .31
Figure 26. Serial Interface Typical Byte

Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 27. Serial Interface Chip Address . . . . . . .32
Figure 28. Typical Analog Reconstruction Filter . . .63
Figure 29. Overall Response . . . . . . . . . . . . . . . . . .63
Figure 30. Typical Layout . . . . . . . . . . . . . . . . . . . . .65
Figure 31. ST-163E Layout . . . . . . . . . . . . . . . . . . .66
Figure 32. Pass Band . . . . . . . . . . . . . . . . . . . . . . .67
Figure 33. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .67
Figure 34. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 35. Group Delay . . . . . . . . . . . . . . . . . . . . . .67

List of Tables

Table 1.

CSM Coefficient Range . . . . . . . . . . . . . 9

Table 2.

Expected Output Values for the
CSM with YCBCR Inputs . . . . . . . . . . . . 9

Table 3.

PDC Edge Control . . . . . . . . . . . . . . . . 11

Table 4.

Horizontal Line Equations. . . . . . . . . . . 12

Table 5.

Horizontal Timing Specifications. . . . . . 13

Table 6.

Vertical Interval Timing
Specifications . . . . . . . . . . . . . . . . . . . . 14

Table 7.

Default Horizontal Timing
Parameters . . . . . . . . . . . . . . . . . . . . . . 15

Table 8.

NTSC Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 16

Table 9.

PAL Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 18

Table 10.

PAL-M Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 20

Table 11.

Standard Subcarrier Parameters . . . . . 22

Table 12.

Line by Line Pedestal Enable . . . . . . . . 23

Table 13.

Closed Caption Line Selection . . . . . . . 24

Table 14.

D/A Outputs . . . . . . . . . . . . . . . . . . . . . 25

Table 15.

Ancillary Data Format . . . . . . . . . . . . . . 26

Table 16.

Ancillary Data Control Phase . . . . . . 27

Table 17.

Ancillary Data Control Frequency. . . . . 27

Table 18.

Field Identification and Subcarrier
Reset Modes . . . . . . . . . . . . . . . . . . . . 27

Table 19.

Layering and Keying Modes . . . . . . . . . 28

Table 20.

Overlay Address Map . . . . . . . . . . . . . . 29

Table 21.

Parallel Port Control . . . . . . . . . . . . . . . 30

Table 22.

Serial Port Addresses. . . . . . . . . . . . . . 31

Table 23.

Control Register Map . . . . . . . . . . . . . . 33

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Pin Assignments

Pin Definitions

Pin Name

Pin Number

Value

Description

CLOCK, SYNC, & CONTROL INPUTS (6 pins)

DCVEN

TTL

Digital CVBS Output Enable. When DCVEN is LOW, the
Comp2 output prior to the D/A is routed to D7-0, FLD2-1
providing a digital composite output. When DCVEN is HIGH,
D7-0 and FLD2-1 operate in their normal mode.

HSIN

TTL

Horizontal Sync Input. When operating in slave, Genlock, or
DRS-Lock the TMC2192 will start a new horizontal line with
each falling edge of HSIN.

KEY

TTL

Hard Key selection. When the control register bit HKEN is set
HIGH and the hardware KEY pin is high, the video data
considered to be the foreground. is routed to the COMP2
output. This control signal is data aligned so that the pixel that is
present on the PD port when KEY signal is latched is at the
midpoint of the key transition. When HKEN is LOW, Key is
ignored.

GND

VSIN

HSIN

DCVEN

SER

CS\/SCL

R/W\/SDA

A1/SA1

A0/SA0

GND

PDC

HSOUT

VSOUT

LINE4

LINE3

LINE2

LINE1

LINE0

DDA

COMP

BYPCOMP

GND

CHROMA

BYPCHROM

DDA

REFCHROM

GND

LUMA

BYPLUMA

DDA

REFLUMA

GND

DDA

GND

KEY

GND

65-6294-14

100

Pin

Function

Pin

Function

GND

Pin

Function

Pin

100

Function

FLD2

FLD1

FLD0

CVBS9

CVBS8

CVBS7

CVBS6

CVBS5

CVBS4

CVBS3

CVBS2

CVBS1

CVBS0

RESET

PXCK

GND

REF

REFCOMP

AGND

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

PXCK

TTL

Pixel Clock Input. PXCK is a clock signal that period is twice
the sample rate of the pixel data. The operating range is 20 to
30 MHz. The clock is internally divided by 2 to generate the
internal pixel clock, PCK. PXCK drives the entire TMC2192
except the asynchronous microprocessor interface.

RESET

TTL

Master Chip Reset. When LOW, All outputs are tri-stated and
the internal state machines and control registers are reset. At
rising edge of RESET, all outputs are active, the preset values
will be loaded into the control registers and the internal states
machines start to operate.

VSIN

TTL

Vertical Sync Input. When operating in slave, Genlock, or
DRS-Lock the TMC2192 will start a new vertical field with each
falling edge of VSIN that is coincident with HSIN.

SYNC & CONTROL OUTPUTS (11 pins)

FLD[2:0]

8183

TTL

Field Identifier. Field Identifier outputs the current field number.
For all video standards the field identifier will cycle through the
eight counts.

HSOUT

TTL

Horizontal Sync Output. The alignment of HSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.

LINE[4:0]

7680

TTL

Vertical Blanking Interval Line Identifier. LINE identifies the
current line number for the first 31 lines. If the line count is
greater than 31 then LINE is 11111b. The first line with a vertical
serration is considered to be line 0.

PDC

TTL

Pixel Data Control.

When PDCDIR = LOW: At a rising edge, The next pixel starts a
controlled ramp of the PD data. At a falling edge, the pixel prior
is the last PD used in the ramp. The rising edge is determined
by the PDCCNT control register, the falling edge of PDC is
determined by the horizontal timing registers.

When PDCDIR = HIGH: PDCIN is used to override the internal
PDC. When HIGH, the internal PDC controls the blank and
unblank window. When LOW, the video remains blanked
regardless of the internal PDC. All edges have the same ramp
control as the internal PDC.

VSOUT

TTL

Vertical Sync Output. The alignment of VSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.

DATA INPUTS (39 pins)

CVBS[9:0]

8493

TTL

Composite Data Input

OL[4:0]

2125

TTL

Overlay Control

PD[23:0]

2738, 4152

TTL

Component Data Input

ANALOG INTERFACE Video Out (5 pins)

LUMA

1.35Vp-p

Luma

CHROMA

1.35Vp-p

Chroma

COMP

1.35Vp-p

Composite D/A with optional keying

Pin Definitions

(continued)

Pin Name

Pin Number

Value

Description

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

ANALOG INTERFACE Support (9 pins)

BYPLUMA

0.1

µF

Reference Bypass Capacitor for LUMA DAC. Connection
point for 0.1

µF Capacitor.

BYPCHROM

0.1

µF

Reference Bypass Capacitor for CHROMA DAC. Connection
point for 0.1

µF Capacitor.

BYPCOMP

0.1

µF

Reference Bypass Capacitor for COMPOSITE DAC.
Connection point for 0.1

µF Capacitor.

REFLUMA

1210 Ohm

Current Setting Resistor. Connection point for external current
setting resistor for LUMA DAC. The resistor is connected
between R

REFLUMA

and GND. Output video levels are

inversely proportional to the value of R

REF2

REFCHROM

1210 Ohm

Current Setting Resistor. Connection point for external current
setting resistor for CHROMA DAC. The resistor is connected
between R

REFCHROM

and GND. Output video levels are

inversely proportional to the value of R

REFCHROM

REFCOMP

1210 Ohm

Current Setting Resistor. Connection point for external current
setting resistor for COMPOSITE DAC. The resistor is connected
between R

REFCOMP

and GND. Output video levels are

inversely proportional to the value of R

REFCOMP

REF

1.235 V

Voltage Reference Input. External voltage reference input,
internal voltage reference output, nominally 1.235V.

MPU INTERFACE (13 pins)

A[1:0]/S

[1:0]

61, 62

TTL

When SER (HIGH), OLUT/control/pointer address.
When SER (LOW), SA[1:0] of serial chip address SA[6:0].

CS/SCL

TTL/R-BUS

When SER (HIGH), microprocessor port clock.
When SER (LOW), serial bus clock.

D[7:0]

6370

TTL

Bi-directional Data Bus.

RW/SDA

TTL/R-BUS

When SER (HIGH), read/write control.
When SER (LOW), serial bus bi-directional data.

SER

TTL

Microprocessor Select. When LOW, the serial interface is
enabled. When HIGH, the parallel interface is enabled.

POWER & GROUND (17 pins)

GND

4, 9, 14, 15, 18,

19, 100

0.0V

Analog ground

GND

26, 40, 53, 71, 97

0.0V

Digital ground

39, 54, 72, 96

+5.0V

Digital positive power supply

DDA

1, 7, 12, 16, 17

+5.0V

Analog positive power supply

Pin Definitions

(continued)

Pin Name

Pin Number

Value

Description

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Functional Description

Input Formats

Control Registers for this section

The TMC2192 supports YC

component sources on the

pixel data port. YC

input sources are supported in 10 bit

4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2
cases the color difference components are linearly interpo-
lated to 4:4:4 internally.

Demuxing of multiplexed data streams depends on which
synchronization mode the encoder is operating in. For slave
and genlock modes the falling edge of HSIN must be LOW
prior to the C

data in order to demux the data correctly. For

master mode synchronization the falling edge of HSOUT
must be LOW prior to the Y data in order to demux the data
correctly. Finally, in 656 mode the demuxing of the data
stream is determined by the TRS codes, the first sample after
the TRS is considered a C

sample of the C

Y C

packet.

The control register D1OFF controls the formatting of the
incoming luminance data at the pixel data port. When
D1OFF is HIGH a blanking level of 64

is subtracted from

the luminance and when D1OFF is LOW the incoming the
pixel data is passed through. The inversion of the MSB's on
the C

and C

components is controlled by the INMODE

control register.

Figure 1. Input Formats

INMODE = 00, PD[7:0] = PD[23:16] = C

, PD[15:8] = C

Figure 2. 24 Bit Input Format

Address

Bit(s)

Name

0x05

D1OFF

0x05

6-4

INMODE

0x06

TSOUT

YC C

INMODE

2192002A

PD[7:0]

PD[15:8]

PD[23:16]

PXCK

HSOUT

(TSOUT = 1)

2192003A

n-1

Rn-1

Bn-1

x+1

x+2

x = (SY+BR+BU+CBP)*2

128

n = (SY+BR+BU+CBP+AV)*2

HSIN

Bx+1

Bx+2

Rx+1

Rx+2

INMODE = 01, PD[23:14] = YC

running at 27MHz.

The PD port is clocked at twice the pixel rate, with the data
organized as C

Y C

Y, with the cosited Y's following the

's. In its CCIR-656 time base mode, the demuxed C

, Y,

and C

data is synchronized to the SAV preamble. The first

data value, after the SAV preamble, is treated as a C

data

point in the multiplexed C

, Y, C

Y , D1 data stream.

Note: Figure 3, pixel numbering, reflects the SMPTE-125M
pixel numbering.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Figure 3. CCIR656 Input Format

Figure 4. 10 bit Input Format

INMODE = 11, PD[9:0] = Y, PD[23:14] = C

Figure 5. 20 bit 4:2:2 Input Format

INMODE = 10, PD[9:0] = Y at PCK, PD[23:14] = C

-C

at PXCK

Figure 6. 20 bit 4:4:4 Input Format

PD[23:14]

PXCK

HSOUT

(TSOUT = 1)

65-6294-04

B736

B718

EAV

SAV

736

718

R718

719

128

(SY+BR+BU+CBP)*2

PD[23:14]

PXCK

HSOUT

(TSOUT = 1)

65-6294-05

x+1

x+2

n+1

Bx+2

128

n = (SY+BR+BU+CBP+AV)*2

x = (SY+BR+BU+CBP)*2

HSIN

Bx+2

PD[9:0]

PD[23:14]

PXCK

HSOUT

HSIN

(TSOUT = 1)

65-6294-06

x+1

x+2

n+1

128

x = (SY+BR+BU+CBP)*2

n = (SY+BR+BU+CBP+AV)*2

PD[9:0]

PD[23:14]

PXCK

HSOUT

(TSOUT = 1)

65-6294-07

n+1

128

x = (SY+BR+BU+CBP)*2

n = (SY+BR+BU+CBP+AV)*2

n+1

Rn+1

HSIN

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Color Space Matrix

Control Registers for this section

Matrix configuration:

composite

= MCF1 * Y

= MCF2 * C

= MCF3 * C

The color space matrix consists of 3 multipliers with inde-
pendently adjustable coefficients, and a resolution of
0.00049 (1/2048). The amount of gain varies among coeffi-
cients, Table 1 summarizes the gain for each coefficient.

To aid in the programming of the color space matrix Table 2
provides a set of default input and output values for 100%
color bars. The component values given will be after the pre-

processing block and prior to the sync and pedestal insertion.
The blank, pedestal, and sync values are given as a reference.
Table 4 gives the default coefficients values for the CSM.

Address

Bit(s)

Name

0x30

7-0

MCF1L

0x33

7-0

MCF2L

0x35

7-0

MCF3L

0x3A

7-4

MCF1M

0x3B

2-0

MCF2M

0x3C

2-0

MCF3M

Table 1. CSM Coefficient Range

Coefficient

Gain Range

Comment

MCF1

0 to 2

MCF2

0 to 1

11 bit coefficient.

MCF3

0 to 1

11 bit coefficient.

Table 2. Expected Output Values for the CSM with YC

Inputs

Color

Inputs

5:2 Outputs

7:3 Outputs

White

876

536

568

Yellow

776

-448

475

-235

503

-249

Cyan

614

151

448

376

-332

407

-351

Green

514

-297

-375

315

-156

-278

340

-165

-294

Magenta

362

297

375

222

156

278

240

165

294

Red

262

-151

448

160

-79

332

173

-84

351

Blue

100

448

-73

235

-54

249

-57

Black

Blank

240

256

Pedestal

Sync

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Synchronization Modes

Control Registers for this section

The TMC2192 offers a variety of synchronization modes;
these are master, slave, genlock, 656 mode, and DRS-Lock.
In master mode, the TMC2192 generates its own timing and
the synchronization is supplied externally by HSOUT and
VSOUT signals. In slave and genlock modes the TMC2192
derives its timing from the input pins HSIN, VSIN. In 656
mode the timing is driven by the synchronization codes
embedded into the data stream.

Master

The TMC2192 drives the output pins HSOUT and VSOUT
to synchronize the incoming video. A new color frame starts
at the rising edge of RESET. The encoder always starts at the
1

vertical serration in field 8 and will freerun the field and

line sequence. The control register bit SRESET can be used
to synchronize the start of the field and line sequence in mas-
ter mode by resetting the FVHGEN state machine. Output
synchronization signal VSOUT can operate in a traditional
sync mode or in a MPEG style field toggle mode.

Slave

CCIR656

The TMC2192 derives all synchronization from the embed-
ded TRS (timing reference signals) information. Blanking of
selected lines is determined by the v bit of the TRS. However
the control registers VBIENx can override and blank the
active video portion of VBI lines regardless of the state of the
v-bit.

Genlock

The TMC2192 is driven by the input synchronization pins
HSIN and VSIN. When the falling edge of HSIN and VSIN
occurs at the same rising edge of PXCK the TMC2192 will
start a new field.VSIN can be either a traditional pulse or the
MPEG style field toggle. In both cases the TMC2192 will
flywheel through fields 2, 4, 6, and 8 synchronizing only to
fields 1, 3, 5, and 7. The TMC2192 collects GRS data and
resets its subcarrier phase and frequency to the data embed-
ded in the GRS stream. The GRS detection occurs only on
the CBVS port.

DRS

The TMC2192 is driven by the input synchronization pins
HSIN and VSIN. When the falling edge of HSIN and VSIN
occurs at the same rising edge of PXCK the TMC2192 will
start a new field.VSIN can be either a traditional pulse or the
MPEG style field toggle. In both cases the TMC2192 will
flywheel through fields 2, 4, 6, and 8 synchronizing only to
fields 1, 3, 5, and 7. Subcarrier phase adjustment is deter-
mined by the DRS data. The DRS detection can occur on
either the CBVS port or the pixel data port.

Propagation Delay

The propagation delay from the pixel data (PD) input to the
D/A output is 64 PXCK's. Figure 8 shows the propagation
delay for both master and slave synchronization modes. For
CCIR656 data streams, pixel 736 (pixel 0 in Figure 8) is the
midpoint of sync and is 32 PXCK's (24 PXCK's in PAL)
after the EAV TRS.

Figure 7. Propagation Delay through the Encoder

Address

Bit(s)

Name

0x06

5-3

MODE

0x06

TOUT

0x06

TSOUT

PD[23:14]

PXCK

DACx

(ANALOG)

DCVBS

(D[7:0],FLD[2:1])

65-6294-09

COMP

n+1

128

n = (SY+BR+BU+CBP+AV)*2

Midpoint of the
Falling Edge of Sync

HSOUT

HSIN

(TSOUT = 1)

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Blanking Control

Control Registers for this section

The content of VBIENFx[4:0] selects the first line to contain
an active video region in each field, all subsequent lines for
the remainder of the field are active. To blank an entire field,
the user zeroes the VBIENFx[4:0] control register. In
CCIR656 slave mode, the user can selectively blank any
enabled line by setting its TRS V bit HIGH. For 525-line
systems, NTSC line numbering is employed, with the first
vertical serration starting on line 4. PAL line numbering is
used with 625-line systems, with each field's line 1 being the
start of the first vertical serration.

Any line(s) enabled by the closed caption control are auto-
matically unblanked for the closed caption waveform, irre-
spective of the corresponding values of VBIENF.

Pixel Data Control

The pixel data control has two modes of operation, as an
input or as an output. The mode of operation is determined
by the PDCDIR control register. When PDC is an input the
internally generated PDC is ANDed with the PDC pin. This
allows the user to blank any active video regions. When PDC
is an output, the internally generated PDC is the output for
the PDC pin.

The internal PDC control will toggle to a logic HIGH at the
pixel specified by PDCNT and toggle to a logic LOW four
pixels prior to the end of the active video region. The starting
point and ending point of the active video region (VA) are
determined by the control registers 10h to 1Fh. When PDC is
used as an input, the sloped edge of the active video region
will occur on the next four pixels following the toggle point.

Edge Shaping

The TMC2192 has three modes of sloped edges on the active
video region and are controlled by PDRM control register.

Address

Bit(s)

Name

0x04

1-0

PDRM

0x06

PDCDIR

0x18

4-0

VBIENF1

0x19

4-0

VBIENF2

0x1F

7-0

PDCCNT

Table 3. PDC Edge Control

PDRM[1:0]

Slope type at PDC (HIGH)

Slope type at PDC (LOW)

The following four pixels have the weighting of
1/8, 1/2, 7/8 and 1 for NTSC and 1/8, 3/8, 5/8,
and 7/8 for PAL.

The following four pixels have the weighting of
1, 7/8, 1/2, and 1/8 for NTSC and 7/8, 5/8, 3/8,
and 1/8 for PAL.

The fifth pixel is sampled and scaled 1/8, 1/2,
7/8 and 1 over the next four pixels for NTSC
and 1/8, 3/8, 5/8, and 7/8 over the next four
pixels for PAL.

The fifth pixel s sampled and scaled 1, 7/8, 1/2
and 1/8 over the next four pixels for NTSC and
7/8, 5/8, 3/8, and 1/8 over the next four pixels
for PAL.

Slope is off, edge control is dictated by the PD
stream from active video start

Slope is off, edge control is dictated by the PD
stream to active video end

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Horizontal Programming

Control registers for this section

Horizontal interval timing is fully programmable and is
established by loading the timing registers with the duration
of each horizontal element. The duration is expressed in
PCK clock cycles. In this way, any pixel clock rate between
10 MHz and 15 MHz can be accommodated, and any desired
standard or non-standard horizontal video timing may be
produced.

Horizontal timing parameters can be calculated as follows:

t = N x ( PCK period )

= N x ( 2 x PXCK period )

where N is the value loaded into the appropriate timing
register, and PCK is the pixel clock period.

When programming horizontal timing, subtract 5 PCK
periods from the calculated values of CBP and add 5 PCK
periods to the calculated value for VA. The control register
HALFEN enables the 1

half line (UBV) on line 283 for

NTSC, PAL-M and line 23 for all other PAL standards when
it is LOW.

Address

Bit(s)

Name

0x06

7-6

FORMAT

0x19

SHORT

0x19

T512

0x19

HALFEN

0x20

7-0

0x21

7-0

0x22

7-0

0x23

7-0

CBP

0x24

7-0

XBP

0x25

7-0

0x26

7-0

0x27

7-0

0x28

7-0

0x29

7-0

0x2A

7-0

0x2B

7-0

0x2C

7-0

0x2D

7-6

XBP (MSB's)

0x2D

5-4

VA (MSB's)

0x2D

3-2

VB (MSB's)

0x2D

1-0

VC (MSB's)

Table 4. Horizontal Line Equations

Line Type

Line ID

Line Length Equals

EL + EH + EL + EH

SL + SH + EL + EH

SL + SH + SL + SH

EL + EH + SL + SH

EL + EH + EL + EH

UBB, -BB

0D, 05

SY + BR + BU + CBP + VA + FP

UVV, -VV

0F, 07

SY + BR + BU + CBP + VA + FP

UVE, -VE

0C, 04

SY + BR + BU + CBP + VC + FP + EL + EH

UBV

SY + BR + BU + XBP + VB + FP

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Figure 8. Horizontal Timing

Vertical interval timing is also fully programmable, and is
established by loading the timing registers with the dura-
tion's of each vertical timing element, the duration expressed
in PCK clock cycles. In this way as with horizontal program-

ming, any pixel rate between 10 and 15 Mpps can be accom-
modated, and any desired standard or non-standard vertical
video timing may be produced.

Like horizontal timing parameters, vertical timing parame-
ters are calculated as follows:

t = N x ( PCK period )

= N x ( 2 x PXCK period )

where N is the value loaded into the appropriate timing reg-
ister, and PCK is the pixel clock period.

The vertical interval comprises several different line types
based upon H, the Horizontal line time.

H = (2 x SL) + (2 x SH) [Vertical sync pulses]

= (2 x EL) + (2 x EH) [Equalization pulses]

Figure 9. Horizontal Timing Vertical Blanking

The VB and VC control registers are added to produce the
half-lines needed in the vertical interval at the beginning and
end of some fields. These must properly mate with compo-
nents of the normal lines.

CBP

65-6294-10

Table 5. Horizontal Timing Specifications

Parameter

NTSC-M

(

µs)

PAL-I

(

µs)

PAL-M

(

µs)

1.5

1.65

1.9

4.7

4.95

0.6

0.9

2.5

2.25

CBP

1.6

2.55

1.8

52.6556

51.95

51.692

63.5556

64.0

63.492

H/2

65-6294-11

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Notes:
1. XBP, VA, VC, and VB are 10 bit values. The 2 MSBs for these four variables are in Timing Register 2D.
2. EH and SL are 9 bit values. A most significant "1" is forced by the TMC2192 since EH and SL must range from 256 to 511.

EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 29 and 2A.

3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.

Vertical Timing

The vertical timing is controlled by the FORMAT control
register, which dictates the field and line sequence.

Figure 12. NTSC Vertical Interval

Table 7. Default Horizontal Timing Parameters

Standard

Field

Rate

(Hz)

Horizontal

Freq.

(KHz)

Pixel

Rate

(Mpps)

PXCK

Freq.

(MHz)

Timing Register (hex)

CBP XBP

Note CBL

NTSC sqr. pixel

59.94

15.734266

12.27

24.54

NTSC CCIR-601

59.94

15.734266

13.50

27.00

NTSC 4x F

59.94

15.734266

14.32

28.64

PAL sqr. pixel

50.00

15.625000

14.75

29.50

PAL CCIR-601

50.00

15.625000

13.50

27.00

PAL 15 Mpps

50.00

15.625000

15.00

30.00

PAL-M sqr.pixel

60.00

15.750000

12.50

25.01

PAL-M CCIR-601

60.00

15,750000

13.50

27.00

PAL-M 4x F

60.00

15,750000

14.30

28.60

262

524

263

525

FIELDS 2 AND 4

FIELDS 1 AND 3

UVV

UVE

UVV

UBB

UVV

UBB

UBV

UVV

264

265

266

267

268

269

270

271

272

273

···

282

283

284

285

HSOUT

VSOUT

(TOUT = 1)

65-6294-15

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

Black burst

UVV

Active video

UVE

Half-line video, half-line equalization pulse

UBV

half-line black, half-line video

Table 8. NTSC Field/Line Sequence and Identification

Field 1

FIELD ID = x00

Field 2

FIELD ID = x01

Field 3

FIELD ID = x10

Field 4

FIELD ID = x11

Line

LTYPE

Line

LTYPE

Line

LTYPE

Line

LTYPE

266

267

268

269

270

271

UBB

272

UBB

272

...

UBB

273

UBB

...

UBB

273

UBB

...

UBB

...

UBB

282

UBB

282

UBB

UVV

283

UBV

UVV

283

UBV

UVV

284

UVV

284

UVV

...

UVV

...

UVV

...

UVV

...

UVV

262

UVV

524

UVV

262

UVV

524

UVV

0F.

263

UVE

525

UVV

263

UVE

525

UVV

264

265

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Figure 13. PAL Vertical Interval

65-6294-16

FIELDS 4 AND 8

309

310

UVV

-BB

···

UBB

UVV

311

312

313

314

315

316

317

318

319

···

320

334

335

UBB

336

337

622

623

FIELDS 3 AND 7

-VV

-VE

UBB

···

UBV

UBB

UVV

624

625

···

UVV

FIELDS 2 AND 6

309

310

UVV

-VV

UBB

···

UBB

UVV

311

312

313

314

315

316

317

318

319

···

320

334

335

UBB

336

337

622

623

FIELDS 1 AND 5

UVV

-VE

-BB

UBB

···

UBV

UBB

UVV

624

625

···

UVV

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

Black burst

-BB

Black burst with color burst suppressed

UVV

Active video

-VV

Active video with color burst suppressed

UVE

Half-line video, half-line equalization pulse

-VE

Half-line video, half-line equalization pulse, color burst suppressed.

UBV

half-line black, half-line video

Table 9. PAL Field/Line Sequence and Identification

Field 1 & 5

FIELD ID = 000, 100

Field 2 & 6

FIELD ID = 001, 111

Field 3 & 7

FIELD ID = 010, 110

Field 4 & 8

FIELD ID = 011, 111

Line

LTYPE

Line

LTYPE

Line

LTYPE

Line

LTYPE

313

314

315

316

317

-BB

318

UBB

318

UBB

319

UBB

319

-BB

...

UBB

320

UBB

...

UBB

320

UBB

...

UBB

...

UBB

UBV

334

UBB

UBV

334

UBB

UVV

335

UBB

UVV

335

UVV

0F.

UVV

336

UVV

336

UVV

337

UVV

337

UVV

...

UVV

...

UVV

...

UVV

...

UVV

309

UVV

622

-VV

309

UVV

622

UVV

310

-VV

623

-VE

310

UVV

623

-VE

311

624

311

624

312

625

312

625

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Figure 14. PAL-M Vertical Interval

65-6294-17

259

260

FIELDS 2 AND 6

UVV

-VE

-BB

UBB

UBV

UVV

261

262

263

264

265

266

267

268

269

270

···

271

279

280

281

259

258

260

FIELDS 4 AND 8

-VV

UVV

-VE

UBB

UBV

UVV

261

262

263

264

265

266

267

268

269

270

···

271

279

280

281

521

522

FIELDS 1 AND 5

UVV

-BB

UBB

-BB

UBB

UVV

523

524

525

···

521

522

FIELDS 3 AND 7

UVV

-VV

-BB

UBB

UVV

523

524

525

···

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

HSOUT

VSOUT

(TOUT = 1)

VSOUT

(TOUT = 0)

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Equalization pulse

Half-line vertical sync pulse, half-line equalization pulse

Vertical sync pulse

Half-line equalization pulse, half-line vertical sync pulse

Equalization broad pulse

UBB

Black burst

-BB

Black burst with color burst suppressed

UVV

Active video

-VV

Active video with color burst suppressed

UVE

Half-line video, half-line equalization pulse

-VE

Half-line video, half-line equalization pulse, color burst suppressed.

UBV

half-line black, half-line video

Table 10. PAL-M Field/Line Sequence and Identification

Field 1 & 5

FIELD ID = 000, 100

Field 2 & 6

FIELD ID = 001, 111

Field 3 & 7

FIELD ID = 010, 110

Field 4 & 8

FIELD ID = 011, 111

Line

LTYPE

Line

LTYPE

Line

LTYPE

Line

LTYPE

263

264

265

266

267

268

-BB

269

-BB

269

-BB

270

-BB

UBB

270

UBB

271

UBB

271

UBB

...

UBB

279

UBB

279

UBB

UVV

280

UBV

0E.

UVV

280

UBV

0E.

...

281

UVV

...

UVV

281

UVV

259

UVV

...

258

UVV

...

260

-VE

521

UVV

259

-VV

521

UVV

261

522

-VV

260

-VE

522

UVV

262

523

00.

261

523

524

262

524

525

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Chrominance Processor

Control registers for this section:

Subcarrier Programming

The color subcarrier is produced by an internal 32 bit digital
frequency synthesizer which is completely programmable in
frequency and phase. Separate registers, FREQx, SYSPHx,
BSTPHx, are provided for phase adjustment of the color
burst and of the active video, permitting external delay com-
pensation, color adjustment, etc. FREQx is the subcarrier
phase step per pixel and SYSPHx is phase offset at field 1,
line 1 (line 4 for NTSC), pixel 1.

NTSC Subcarrier

For NTSC encoding, the subcarrier synthesizer frequency
has a simple relationship to the pixel clock period, repeating
over 2 lines: The decimal value for the subcarrier phase step
is:

Where the number of pixels/line is:

This value must be converted to binary and split into four 8
bit registers, FREQM, FREQ2, FREQ3, and FREQL.

PAL Subcarrier

The PAL relationship is more complex, repeating only once
in 8 fields (the well-known 25 Hz offset):

This value must be converted to binary and split as described
previously for NTSC. The number of pixels/line is found as
in NTSC.

PAL-M Subcarrier

SYSPHx establishes the appropriate phase relationship
between the internal synthesizer and the chroma modulator.
The nominal value for SYSPHx is zero.

Other values for SYSPHx must be converted to binary and
split into two 8 bit registers, SYSPHM and SYSPHL.

Burst Phase (BURPHx) sets up the correct relative NTSC
modulation angle. The value for BURPH is:

BURPHx = SYSPHx

This value must be converted to binary and split into two 8
bit registers, BURPHM and BURPHL.

Address

Bit(s)

Name

0x06

7-6

FORMAT

0x06

5-3

MODE

0x07

DDSRST

0x11

DRSSEL

0x18

GLKCTL1

0x18

GLKCTL0

0x3F

GAUSS_BYP

0x40

7-0

FREQL

0x41

7-0

FREQ3

0x42

7-0

FREQ2

0x43

7-0

FREQM

0x44

7-4

SYSPHL

0x45

3-0

SYSPHM

0x46

7-4

BURPHL

0x47

3-0

BURPHM

0x48

7-4

BRSTFULL

0x49

3-0

BRST1

0x4A

7-4

BRST2

FREQx

455 2

pixels line

---------------------------

pixels line

PXCK Frequency

H Period

------------------------------------------

FREQx

1135 4

(

)

1 625

(

)

pixels line

---------------------------------------------------

FREQ

909 4

pixels line

---------------------------

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Subcarrier Synchronization

There are 5 modes of subcarrier synchronization in the
TMC2192, freerun, subcarrier reset, Genlock, DRS-lock and
Ancillary Data Control (ANC).

Freerun

At the rising edge of RESET the DDS starts to generate the
subcarrier reference and will continue to freerun the subcar-
rier. When setting the control register DDSRST is HIGH, the
TMC2192 will reset the DDS to the SYSPH value on the
next field 1, line 1 (line 4 for NTSC), pixel 1 occurrence and
will reset this bit to be LOW. This allows the encoder to start
with the correct SCH relationship. The phase of the subcar-
rier reference will drift over time since a 32 bit accumulator
has a error of

±0.5 Hz when generating the subcarrier refer-

ence for NTSC 13.5 MHz.

Subcarrier Reset

At the rising edge of RESET the DDS starts to generate the
subcarrier reference and will reset the DDS to the SYSPH
value every field 1, line 1 (line 4 for NTSC), pixel 1 occur-
rence. This enables the encoder to maintain the proper SCH
relationship.

Genlock

The Genlock mode allows the TMC2192 to lock to a com-
posite reference when used in conjunction with the
TMC22071A Genlocking Video Digitizer. The TMC22071A
produces a genlock reference signal (GRS) which contains
field identification, PALODD status, relative phase and rela-
tive frequency of the composite reference. The GRS is sam-
pled on the CVBS bus 60 PXCK's after the falling edge of
HSIN. The phase and frequency values are used to update
the DDS on a line to line basis, thus synchronizing the sub-
carrier to an external composite reference.

DRS-Lock

The DRS-Lock mode allows the TMC2192 to lock its com-
posite output to the decoded composite or S-video input of

the TMC22x5y. The TMC22x5y produces a decoder refer-
ence signal (DRS) which contains field identification, PAL-
ODD status, relative phase and relative frequency of the
composite or S-video input. The DRS is sampled on either
the CVBS bus or the PD port, depending on DRSSEL, 60
PXCK's after the falling edge of HSIN. The phase and fre-
quency values are used to update the DDS on a line to line
basis, thus synchronizing the subcarrier to an external com-
posite reference.

Ancillary Data Control (ANC)

Subcarrier synchronization in ANC mode is covered in the
Ancillary Data Control section of this data sheet.

SCH Phase Error Correction

SCH refers to the timing relationship between the 50% point
of the leading edge of horizontal sync and the positive or
negative zero-crossing of the color burst subcarrier refer-
ence. SCH error is usually expressed in degrees of subcarrier
phase. In PAL, SCH is defined for line 1 of field 1, but since
there is no color burst on line 1, SCH is usually measured at
line 7 of field 1. The need to specify SCH relative to a partic-
ular line in PAL is due to the 25 Hz offset of PAL subcarrier
frequency. Since NTSC has no such 25 Hz offset, SCH
applies to all lines.

The SCH relationship is important in the TMC2192 when
two video sources are being combined or if the composite
video output is externally combined with another video
source. In these cases, improper SCH phasing will result in a
noticeable horizontal jump of one image with respect to
another and/or a change in hue proportional to the SCH error
between the two sources.

SCH phasing can be adjusted by modifying BURPH and
SYSPH values by equal amounts. SCH is advanced/delayed
by one degree by increasing/decreasing the value of BURPH
and SYSPH by approximately B6

. An SCH error of 15

corrected with SYSPH and BURPH offsets of AAA

Table 11. Standard Subcarrier Parameters

Standard

Field

Rate

(Hz)

Horizontal

Freq.
(kHz)

Pixel

Rate

(Mpps)

PXCK

Freq.

(MHz)

Subcarrier

Freq.

(MHz)

Subcarrier Register (hex)

BURPHM BURPHL

SYSPHM

SYSPHL

FREQM

FREQ2 FREQ3 FREQL

NTSC sqr. pixel

59.94

15.734266

12.27

24.54

3.57954500

NTSC CCIR-601

59.94

15.734266

13.50

27.00

3.57954500

NTSC 4x F

59.94

15.734266

14.32

28.64

3.57954500

PAL sqr. pixel

50.00

15.625000

14.75

29.50

4.43361875

PAL CCIR-601

50.00

15.625000

13.50

27.00

4.43361875

PAL 15 Mpps

50.00

15.625000

15.00

30.00

4.43361875

PAL-M sqr.pixel

60.00

15.750000

12.50

25.01

3.57561149

PAL-M CCIR-601

60.00

15,750000

13.50

27.00

3.57561149

PAL-M 4x F

60.00

15,750000

14.30

28.60

3.57561149

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Burst Envelope

The TMC2192 includes the ability to adjust the burst ampli-
tude and the shape of the burst. The Control Registers
BRSTFULL, BRST1 and BRST2 hold the magnitude of the
burst vector. BRSTFULL is the maximum amplitude of the
burst vector. BRST1 and BRST2 determine the intermediate
values of the burst vector for the burst envelope shaping. A 5
pixel burst envelope shaping occurs at the rising and falling
edges of burst. At the rising edge of burst the next 5 pixels
have the following weighting; BRSTFULL BRST1,
BRSTFULL BRST2, BRSTFULL/2, BRST2, and BRST1.
At the falling edge of burst the next 5 pixels have the follow-
ing weighting; BRST1, BRST2, BRSTFULL/2, BRSTFULL
BRST2, and BRSTFULL BRST1. With this flexibility
the user determine the shape, amplitude and width of the
burst signal.

Figure 15. Burst Envelope

Color-Difference Low-Pass Filters

The chrominance portion of a composite video signal must
be sufficiently bandlimited to avoid cross-color and cross-
luminance distortion, and to preclude exceeding the allow-
able bandwidth of a video channel.

The color-difference low-pass filters on the TMC2192
establish chrominance bandwidths which meet the specifica-
tions outlined in CCIR Report 624-3, Table II, Item 2.6, for
system I over a range of pixel rates from 12.27 Mpps to
14.75 Mpps. Equal bandwidth is established for both color-
difference channels.

Figure 16. Gaussian Filter Response

Sync and Pedestal Insertion

Control Registers for this section

Pedestal Enable

The TMC2192 has the ability to independently select lines
for pedestal insertion during the vertical blanking interval
(VBI). For 525-line systems and using the NTSC line num-
bering convention, in which the first vertical serration is on
line 4 for field 1 and line 266 for field 2, the vertical interval
lines map to the control registers VBIPEDxy as shown in
Table 15.

BRSTFULL

BRST1

BRST2

BRSTFULL/2

BRSTFULL - BRST2

BRSTFULL - BRST1

BLANK

65-6294-18

Address

Bit(s)

Name

0x06

7-6

MODE

0x11

COMP2DB

0x14

7-0

VBIPEDEM

0x15

7-0

VBIPEDEL

0x16

7-0

VBIPEDOM

0x17

7-0

VBIPENOL

0x1A

6-0

PEDHGT1

0x3F

C2DB_OFF

-80

-70

-60

-50

-40

-30

-20

-10

0.1

0.2

0.3

0.4

0.5

65-6294-19

Normalized Frequency (Pixel rate)

Atten

uation (db)

Table 12. Line by Line Pedestal Enable

Bit

VBIPEDEL

VBIPEDEM

25*

VBIPEDOL

279

278

277

276

275

274

273

VBIPEDOM

287*

286

285

284

283

282

281

280

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Enabling the pedestal on line 25 enables it for the remainder
of field 1, to line 262. Likewise, enabling the pedestal on line
288 enables it for the remainder of field 2.

Pedestal Height

PEDHGT1 determines the height of the pedestal for the
luminance channel on the composite path. The range of the
pedestal height is from -22.1 to 21.74 IRE in .345 IRE incre-
ments.

Sync and Blank Insertion

The composite paths blank and sync D/A codes are deter-
mined by the FORMAT control register. For NTSC and
PAL-M formats the blank D/A code is 240 (295 mV) and the
sync D/A code is 8 (9 mV). For all other PAL formats the
blank D/A code is 256 (314 mV) and the sync D/A code is
12 (14 mV).

In all cases the sync edges are sloped to insure the proper rise
and fall times in all video standards.

Closed Caption Insertion

Control Registers for this section

The TMC2192 includes a flexible closed-caption processor.
It may be programmed to insert a closed caption signal on
any line within a range of 16 lines on ODD and/or EVEN
fields. Closed Caption insertion overrides all other configura-
tions of the encoder: if it is specified on an active video line,
it takes precedence over the video data and removes NTSC
setup if setup has been programmed for the active video
lines. Closed Caption is only available when the TMC2192
is in a 13.5 MHz pixel rate.

Closed caption is turned on by setting CCON HIGH. When-
ever the encoder begins producing a line specified by
CCFLD and CCLINE, it will insert a closed caption line in
its place. If CCRTS is HIGH, the data contained in CCDx
will be sent. IF CCRTS is LOW, Null bytes (hex 00 with
ODD parity) will be sent.

Line Selection

The line to contain CC data is selected by a combination of
the CCFLD bit and the CCLINE bits. CCLINE is added to
the offset shown in Table 16 to specify the line.

Parity Generation

Standard Closed-Caption signals employ ODD parity, which
may be automatically generated by setting CCPAR HIGH.
Alternatively, parity may be generated externally as part of
the bytes to be transmitted, and, with CCPAR LOW, the
entire 16 bits loaded into the CCDx registers will be sent
unchanged.

Operating Sequence

A typical operational sequence for closed-caption insertion
on line xx is:

Read Register 1E and check that bit 7 is LOW, indicat-
ing that the CCDx registers are ready to accept data.

If ready, write two bytes of CC data into registers 1C
and 1D.

Write into register 1E the proper combination of
CCFLD and CCLINE. CCPAR may be written as
desired. Set CCRTS HIGH.

The CC data is transmitted during the specified line.

As soon as CCDx s transferred into the CC processor (and
CCRTS goes LOW), new data may be loaded into registers
1C and 1D. This allows the user to transmit CC data on sev-
eral consecutive lines by loading data for line n+1 while data
is being sent on line n.

Address

Bit(s)

Name

0x1C

7-6

CCD1

0x1D

1-0

CCD2

0x1E

CCON

0x1E

CCRTS

0x1E

CCPAR

0x1E

CCFLD

0x1E

CCLINE

Table 13. Closed Caption Line Selection

Standard

Offset

Field

Lines

525

ODD

12-27

274

EVEN

274-289

625

ODD

16-31

328

EVEN

328-343

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Interpolation Filters

Each video output on the TMC2192 is digitally filtered with
sharp-cutoff low-pass interpolation filters. These filters
ensure that the frequency band above base-band video and
below the pixel frequency (f

/4 to 3f

/4, where f

is the

PXCK frequency) are sufficiently suppressed.

Since these are fixed-coefficient digital filters, their filter
characteristics depend upon clock rate.

Figure 17. Interpolation Filter

Figure 18. Interpolation Filter Passband Detail

x/Sin(x) Filter

Control Registers for this section

The TMC2192 contains a selectable X/sin(X) filter prior to
each DAC. The X/sin(X) filter boosts the high frequency
data to negate the sin(X)/X roll-off associated with D/A con-
verters.

Figure 19. X/SIN(X) Filter

Output Data Formats

Control Registers for this section

-80

-70

-60

-50

-40

-30

-20

-10

65-6294-21

0.2

0.4

0.6

0.8

Frequency (Pixel rate)

Atten

uation (db)

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0.5

0.1

0.2

0.3

0.4

0.5

Frequency (Pixel rate)

Atten

uation (db)

65-6294-20

Address

Bit(s)

Name

0x11

SINEN

Address

Bit(s)

Name

0x10

LUMADIS

0x10

CHROMADIS

0x10

COMPDIS

0x3F

SEL_CLK

0x3F

SEL_PIX

-2

-1.5

-1

-0.5

0.5

1.5

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (PXCK)

Atten

uation (db)

65-6294-22

Compensated

D/A Output

Sin(x)/x D/A Roll-Off

X/Sin(x) Filter

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Analog outputs of the TMC2192 are driven by three 10 bit
D/A converters, operating at twice the pixel rate. The outputs
drive standard video levels into 37.5 or 75 Ohm loads. An
internal voltage reference is used to provide reference cur-
rent for the D/A converters. For more accurate levels, an
external fixed or variable voltage reference source is accom-
modated. The video signal levels from the TMC2192 may be
adjusted by varying the common Vref or the 3 independent
Rrefs. Each video D/A converter has an independent refer-
ence resistor that can adjust the output gain. D/A Matching
is achieved by trimming the each external reference resistor
of each D/A.

Digital Composite Output

In addition, the TMC2192 supplies a 10 bit digital composite
signal on pins D[7:0] and FLD[2:1]. The digital composite
output can be either an interpolated signal on a non-interpo-
lated signal, this controlled by the control register
SEL_CLK.

Ancillary Data

Control Registers for this section

The TMC2192 is designed to accept 15 words of ancillary
data after the active video pixels at the end of each horizontal
line. Ancillary data may occur once per line, once per field,
once per eight fields, on random lines, or not al all. The
TMC2192 does not assume ancillary data is present on a reg-
ular basis.

Note:
1. P = odd parity bit, x = reserved bit will be ignored

The first three words of ancillary data comprise the TRS sig-
nal (ANC2-0) which indicates the end of active video. Also
known as the Ancillary data header, the TRS signal is a 00

, FF

sequence. Except for the TRS words, ancillary data

bit 0 (B

, LSB) is odd parity for B

7-1

The data type word (TT) is used to specify the ancillary data
type. The TMC2192 compares this 7 bit value with the con-
tents of the ANCID control register. If there is a match, the
ancillary data will be processed. If there is no match, the
TMC2192 ignores ancillary data.

The word count data (D

11-0

in MM, LL) in the ancillary data

packet indicate the number of words in ancillary data.

Ancillary phase data is used to program the MSBs of the
PHASE register. ANCPHEN and PHV determine how ancil-
lary phase data is used. When ancillary data is not present,
the TMC2192 assumes PHV = LOW.

Address

Bit(s)

Name

0x07

ANCFREN

0x07

ANCPHEN

0x07

ANCTREN

0x08

7-0

ANCID

Table 14. Ancillary Data Format

Word ID

Description

ANC2

Ancillary Data Header (Timing
Reference Signal)

ANC1

ANC0

Data Type

TT6

TT5

TT4

TT3

TT2

TT1

TT0

Word

D11

D10

Count

FIELD

Field ID/Synchronous Video Flag

SVF

reserved

PH1

Subcarrier Phase

PHV

PH0

FR4

Subcarrier Frequency

FRV

FR3

FR2

FR1

FR0

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Ancillary frequency data is used to program the 32 bits of the
FREQ3-0 registers. ANCFREN and FRV determine how

ancillary frequency data is used. When ancillary data is not
present, the TMC2192 assumes FRV = LOW.

Note:
1. The F bit is part of the EAV timing reference code and tracks the F0 bit.

Operating Modes

The field number bits (F

2-0

) from the ancillary data packet

FIELD word, are used to program the encoder's field counter
depending upon the state of the synchronous video flag
(SVF) and the ANCTREN bit in the control register.

In the basic operating mode (ANCTREN = LOW), all timing
is found in the F bit of EAV. F

2-0

and SVF are ignored and

the encoder subcarrier synthesizer is reset to the PHASE
value every eight fields (when the field counter transitions
from 111 (field 8) to 000 (field 1).

In the basic mode, ANCFREN and ANCPHEN are typically
set LOW, ignoring ancillary frequency and phase data. If
ANCFREN and ANCPHEN are HIGH, the TMC2192 uses
the incoming ancillary frequency and phase data on a line-
by-line basis.

In genlocking mode (ANCTREN and SVF = HIGH), the
subcarrier synthesizer is allowed to free run, with phase and
frequency being set from the ancillary data packet PH

12-0

and FR

31-0

data. The field counter increments just like it

does in basic mode.

Field sequence mode (ANCTREN = HIGH and SVF =
LOW), is the same as basic mode except that the field
counter is set by the F

2-0

bits in the FIELD word of ancillary

data. If ancillary data is not present on a line, the field
counter will continue to count as it does in basic mode.
When ancillary data is present, the contents of the field
counter are loaded with field data (F

2-0

). In this way, the

TMC2192 may be synchronized with an external source by
sending field data only once.

Table 15. Ancillary Data Control Phase

ANCPHEN

PHV

Description

Ignore ancillary phase data,
set PHASE = 0

Ignore ancillary phase data,
no change to PHASE

Load ancillary phase data into
PHASE registers

Table 16. Ancillary Data Control Frequency

ANCFREN

FRV

Description

Ignore ancillary frequency
data

Load ancillary frequency data
into FREQ3-0 registers

Table 17. Field Identification and Subcarrier Reset Modes

ANCTREN

SVF

F (EAV)

Field ID / Subcarrier Reset Mode

Basic Mode

Odd field, reset subcarrier every 8 fields

Even field

Genlocking Mode

Odd field, subcarrier free run

Even field

Field Sequence Mode

Field 1, reset subcarrier at field 1

Field 2

Field 3

Field 4

Field 5

Field 6

Field 7

Field 8

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Layering Engine

Control Registers for this section

The TMC2192 features a robust layering engine with three
possible input layers controlled by two keying controls. The
layer assignments are shown in Table 22, along with the key-
ing control. The keying controls, KEY pin or OL4-0 are
aligned with the incoming pixel data stream and are then
delayed throughout the chip to be continuously aligned with
the input video streams. A generic overview of the keying
and layering features is shown in Figure 21.

Figure 20. Layering Engine

Overlay Mixer

The OL[4:0] bus provides the ability to overlay 30 different
24 bit values onto the pixel data path. The 24 bit overlay col-
ors must be the same format as the incoming Pixel data. For
Y,Cb,Cr input formats the range of Y values spans the entire
range of the format, 1 to 254, this enables super whites and
super blacks in the overlay palette.

When OL[4:0] is equal to 00h the pixel data port to be the
output of the overlay mixer. If OL[4:0] is in the range of 1 to
31 then the output source is one of 30 possible overlay col-

ors, see Table 22. Overlay Address Map. When OL4-0 equal
to 16, the overlay mixer produces a pixel data output with
half the luminance magnitude and chrominance magnitude.
Any OL4-0 value greater than 16 will result in a overlay mix
with a full amplitude overlay and the pixel data with half
amplitude pixel data (PD) or half amplitude CVBS data as its
values. This allows for transparent overlays or produce
shadow boxes around overlaid text.

The midpoint of the rising and falling edges on the mixed
output is determined by the transition of the OL[4:0] pins in

Address

Bit(s)

Name

0x04

SKEN

0x05

3-2

OMIX

0x07

SKFLIP

0x09

HKEN

0x09

BUKEN

0x09

SKEXT

0x09

DKDIS

0x09

EKDIS

0x09

FKDIS

0x09

1-0

LAYMODE

0x0A

7-0

DKEYMAX

0x0B

7-0

DKEYMIN

0x0C

7-0

EKEYMAX

0x0D

7-0

EKEYMIN

0x0E

7-0

FKEYMAX

0x0F

7-0

FKEYMIN

Address

Bit(s)

Name

Table 18. Layering and Keying Modes

LAYMODE

BACKGROUND

MIDGROUND

FOREGROUND

Image Source

Keying Control

Image Source

Keying Control

OVERLAY

OL4-0

CVBS

KEY or Data Key

CVBS

KEY or Data Key

OVERLAY

OL4-0

CVBS

OVERLAY

OL4-0

KEY or Data Key

CVBS

KEY or Data Key

OVERLAY

OL4-0

DATA KEY

KEY

OVERLAY

MIXER

OLUT

OL4-0

KEYING

MIXER

CVBS

COMP

LOGIC

1/2AMP

65-6294-23

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

relation to the PD port. Control register OMIX chooses
among the following set of coefficients; either 0 1/8 1/2 7/8
1, 0 1/2 1 , or 0 1 to switch between the PD port and the over-

lay color. The timing diagram in Figure 22 identifies the
three possible output formats that the mixer can produce.

Figure 21. Overlay Outputs

Hardware Keying

The KEY input switches the input to the Comp data path
between the composite video generated from the PD port and
the CVBS data bus on a pixel-by-pixel basis. This is a "soft"
switch is executed over 3 PCK periods to minimize out-of-
band transients. Keying is accomplished in the digital com-
posite video domain. The coefficients for the mix are 0, 1/8,
1/2, 7/8, and 1 . The COMP output is the final output for all
overlay functions.

Hardware keying is enabled by the key Control Register
HKEN. Normally, keying is only effective during the active
video portion of the encoded video line (as determined by
Control Register VA). That is, the horizontal blanking inter-
val is generated by the encoder even if the KEY signal is
held HIGH through horizontal blanking. However, it is pos-
sible to allow digital horizontal blanking to be passed
through from the CVBS bus to the COMP output by setting
key Control Register BUKEN HIGH. In this mode, KEY is
always active, and may be exercised at will.

The KEY input is registered into the encoder just as Pixel
data is clocked into the PD port. It is internally pipelined, so
the midpoint of the KEY transition occurs at the output of
the pixel that was input at the same time at the KEY signal.

Data Keying

Data keying for each channel Y, C

, and C

, is separately

enabled or disabled by the control registers DKEYDIS,
EKEYDIS, and FKEYDIS. On each channel the eight (8)
MSBs of the pixel data are compared against a maximum

key value and a minimum key value. If the pixel data is
greater than xKEYMIN and less than or equal to xKEY-
MAX, then a key match is signaled for that channel.

Figure 22. Data Keying

By allowing a window of possible key values on each chan-
nel the TMC2192 opens a key cube in the color space.

Parallel Microprocessor Interface

The parallel microprocessor interface is active when SER is
HIGH and employs a 12-line interface; an 8 bit data bus and
2 bit address location, 1 bit read/write select, and a chip
select controlling the timing. Two addresses are required for
device programming, one to the pointer and one to the data
location. When writing, the address is presented along with a
LOW on the R/W pin during the falling edge of CS. Eight
bits of data are presented on D7-0 during the subsequent ris-
ing edge of CS.

Table 19. Overlay Address Map

OL4-0

Result

Pixel data is passed through overlay mixer.

1-15

Overlay is mixed with PD or CVBS at the transitions.

Half amplitude PD or half amplitude CVBS is the output of COMP2.

17-31

Overlay is mixed with half amplitude PD or half amplitude CVBS at the transitions.

OL[4:0]

PDx

1/2C, 1/2OL

1/2G, 1/2OL

MixOUT (OMIX = 3)

7/8B, 1/8OL 1/2C, 1/2OL 1/8D, 7/8OL

1/8F, 7/8OL 1/2G, 1/2OL 7/8H, 1/8OL

MixOUT (OMIX = 2)

MixOUT (OMIX = 1)

65-6294-24

xKEYMAX

A<=B

KEY
MATCH

xKEYMIN

xCHANNEL

65-6294-25

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t

DOZ

after CS falls. Valid data are

present on D7-0 t

DOM

after the falling edge of CS. Because

this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to t

DOZ

Writing data to specific control registers of the TMC2192
requires that the 8 bit address of the control register of inter-
est be written prior to the data. This control register address
is the base address for subsequent write operations. The base
address auto increments by one for each byte of data written
after the data byte intended for the base address. If more
bytes are transferred than there are available addresses, the
address will not increment and remain at its maximum value
of 4Ch.

Writing data to specific OLUT location of the TMC2192
requires that the 8 bit address of the OLUT location of inter-
est be written prior to the data sequence. This OLUT loca-
tion address is the base address for subsequent write
operations. The base address auto increments by one for
each sequence of three (3) bytes of data written after the data
byte intended for the base address. The sequence of data

transfer is Y, C

, C

, after the C

byte is transferred the base

address will increment by one (1).

Figure 23. Microprocessor Parallel Port Write Timing

Figure 24. Microprocessor Parallel Port Read Timing

Table 20. Parallel Port Control

1-0

R/W

Action

Load D

7-0

into Control Register

pointer (block 0)

Read Control Register pointer on
D

7-0

Load D

7-0

into addressed OLUT

Location pointer (block 0)

Read addressed OLUT Location
pointer on D

7-0

Write D

7-0

to addressed Control

Read addressed Control Register
on D

7-0

Write D

7-0

to addressed OLUT

Location

Read addressed OLUT Location on
D

7-0

PWLCS

PWHCS

65-6294-26

R/W

ADR

7-0

PWLCS

DOM

HOM

DOZ

PWHCS

R/W

ADR

7-0

65-6294-27

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Serial Control Port (R-Bus)

In addition to the 12-wire parallel port, a 2-wire serial con-
trol interface is provided, active when SER is LOW. Either
port alone can control the entire chip. Up to four TMC2192
devices may be connected to the 2-wire serial interface with
each device having a unique address.

The 2-wire interface comprises a clock (SCL) and a bi-direc-
tional data (SDA) pin. The encoder acts as a slave for receiv-
ing and transmitting data over the serial interface. When the
serial interface is not active, the logic levels on SCL and
SDA need to be pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA must change only when SCL is LOW. If SDA changes
state while SCL is HIGH, the serial interface interprets that
action as a start or stop sequence.

There are six components to serial bus operation:

· Start signal
· Slave address byte
· Block Pointer
· Offset Pointer
· Data byte to read or write
· Stop signal

When the serial interface is inactive (SCL and SDA are
HIGH) communications are initiated by sending a start sig-
nal. The start signal is a HIGH-to-LOW transition on SDA
while SCL is HIGH. This signal alerts all slaved devices that
a data transfer sequence is coming.

The first eight bits of data transferred after a start signal com-
prise a seven bit slave address and a single R/W bit. The R/W

bit indicates the direction of data transfer, read from or write
to the slave device. If the transmitted slave address matches
the address of the device (set by the state of the SA1-0 input
pins in Table 24), the TMC2192 acknowledges by bringing
SDA LOW on the 9th SCL pulse. If the addresses do not
match, the TMC2192 will not acknowledge.

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit
of the sequence.

If the TMC2192 does not acknowledge the master device
during a write sequence, the SDA remains HIGH so the mas-
ter can generate a stop signal. If the master device does not
acknowledge the TMC2192 during a read sequence, the
encoder interprets this as "end of data".

Writing data to specific control registers of the TMC2192
requires that the 8 bit address of the control register of inter-
est be written after the slave address has been established.
This control register address is the base address for subse-
quent write operations. The base address auto increments by
one for each byte of data written after the data byte intended
for the base address.

Figure 25. Serial Port Read/Write Timing

Data are read from the control registers of the TMC2192 in a
similar manner. Reading requires two data transfer opera-
tions:

The base address must be written with the R/W bit of the
slave address byte LOW to set up a sequential read opera-
tion.

Reading (the R/W bit of the slave address byte HIGH)
begins at the previously established base address. The
address of the read register auto increments after each byte is
transferred.

To terminate a write sequence to the TMC2192, a stop signal
must be sent. A stop signal comprises a LOW-to-HIGH tran-
sition of SDA while SCL is HIGH. To terminate a read

Table 21. Serial Port Addresses

(SA1)

(SA0)

BUFF

STAH

STASU

STOSU

DHO

DSU

DAL

BAH

SCL / CS

SDA / R/W

65-6294-28

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

sequence simply do not acknowledge (NOACK) the last byte
received and the TMC2192 will terminate the sequence.

A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first

generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.

Figure 26. Serial Interface Typical Byte Transfer

Figure 27. Serial Interface Chip Address

Serial Interface Read/Write Examples

Write to one control register
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (00)
· Offset Pointer
· Data byte to base address
· Stop signal

Write to four consecutive control registers
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (00)
· Offset Pointer
· Data byte to base address
· Data byte to (base address + 1)
· Data byte to (base address + 2)
· Data byte to (base address + 3)
· Stop signal

Write to one OLUT location
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (01)
· Offset Pointer (base address)
· Data byte to base address (Y)
· Data byte to base address (Cb)
· Data byte to base address (Cr)
· Stop signal

Write to four consecutive OLUT locations
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (01)
· Offset Pointer (base address)
· Data byte to base address (Y)
· Data byte to base address (Cb)
· Data byte to base address (Cr)
· Data byte to base address +1 (Y)
· Data byte to base address +1 (Cb)
· Data byte to base address +1 (Cr)
· Data byte to base address +2 (Y)
· Data byte to base address +2 (Cb)
· Data byte to base address +2 (Cr)
· Data byte to base address +3 (Y)
· Data byte to base address +3 (Cb)
· Data byte to base address +3 (Cr)
· Stop signal

Read from one control register
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (00)
· Offset Pointer
· Stop signal
· Start signal
· Slave Address byte (R/W bit = HIGH)
· Data byte from base address
· NOACK

SDA

65-6294-29

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACK

SCL

SDA

65-6294-30

R/W

ACK

SCL

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Read from four consecutive control registers
· Start signal
· Slave Address byte (R/W bit = LOW)
· Block Pointer (00)
· Offset Pointer
· Stop signal
· Start signal

· Slave Address byte (R/W bit = HIGH)
· Data byte from base address
· Data byte from (base address + 1)
· Data byte from (base address + 2)
· Data byte from (base address + 3)
· NOACK

Control Register Map

Table 22. Control Register Map

Reg Bit

Mnemonic

Function

TMC2192 Identification Registers (Read only)

7-0

PARTID2

Reads back 97h

7-0

PARTID1

Reads back 21h

7-0

PARTID0

Reads back 92h

7-0

REVID

Silicon revision #

Gamma Filters Register

7-4

Reserved

Set to Low

SRESET

Software RESET

SKEN

Data KEY Enable

1-0

PDRM

Pixel Data Ramping Mode

Input Format Register

D1OFF

YCBCR Input Formatting

Reserved

Program Low

5-4

INMODE

Input Mode Select

3-2

OMIX

Overlay Mixer Select

1-0

SOURCE

Video Input Select

General Control Register

7-6

FORMAT

Video Format

5-3

MODE

Video Mode

PDCDIR

PDC Directional Control

TOUT

External Sync Output Control

TSOUT

External Sync Delay Control

Horizontal Ancillary Data Control Register

LDFID

Field Lock Select

SKFLIP

Soft Key Inversion

DDSRST

DDS Reset

4-3

Reserved

ANCFREN

Ancillary Frequency Enable

ANCPHEN

Ancillary Phase Enable

ANCTREN

Ancillary Timing Enable

Ancillary Data ID Register

7-0

ANCID

Ancillary Data Identification

Keying/Overlay Engine

HKEN

Hardware KEY Enable

BUKEN

Burst KEY Enable

SKEXT

Data KEY Operation Select

DKDIS

Green/Y Data KEY Disable

EKDIS

Blue/C

Data KEY Disable

FKDIS

Red/C

Data KEY Disable

1-0

LAYMODE

Layer Assignment Select

Key Value Registers

7-0 DKEYMAX

Green/Y Maximum Data Key
Value

7-0 DKEYMIN

Green/Y Minimum Data Key
Value

7-0 EKEYMAX

Blue/C

Maximum Data Key

Value

7-0 EKEYMIN

Blue/C

Minimum Data Key

Value

7-0 FKEYMAX

Red/C

Maximum Data Key

Value

7-0 FKEYMIN

Red/C

Minimum Data Key

Value

DAC Control Registers

COMPDIS

D/A #4 Disable

CHROMADIS

D/A #3 Disable

LUMADIS

D/A #2 Disable

4-3

Reserved

Set to 0.

OLUTDIS

Overlay LUT Disable

1-0

Reserved

Program Low

DRSSEL

DRS Selection

Reserved

Program Low

COMP2DB

Composite 2 Overflow Control

SINEN

X/Sin(x) Filter Enable

Reserved

Program Low

LUMDIS

Luma Disable

CHRMDIS

Chroma Disable

BURSTDIS

Burst Disable

Table 22. Control Register Map (continued)

Reg Bit

Mnemonic

Function

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

VBI Ped Enable Registers

7-0

VBIPEDEM

VBI Pedestal Enable, Even Fields

7-0

VBIPEDEL

VBI Pedestal Enable, Even Fields

7-0

VBIPEDOM

VBI Pedestal Enable, Odd Fields

7-1

VBIPEDOL

VBI Pedestal Enable, Odd Fields

HVA

Horizontal and Vertical Sync
Alignment

Vertical Blanking Interval Enable Registers

Reserved

Program Low

GLKCTL1

Genlock Control Register 1

GLKCTL0

Genlock Control Register 0

4-0

VBIENF1

VBI Active Video Enable, Field 1

SHORT

Test Register

T512

EH/SL Offset Control Bit

HALFEN

Half Line Enable

4-0

VBIENF2

VBI Active Video Enable, Field 2

Pedestal Height Register

Reserved

Program Low

6-0

PEDHGT1

Composite Pedestal Height

Closed Caption Registers

7-0

CCD1

First Byte of CC Data

7-0

CCD2

Second Byte of CC Data

CCON

Enable CC Data Packet

CCRTS

Request to Send Data

CCPAR

Auto Parity Generation

CCFLD

CC Field Select

3-0

CCLINE

CC Line Select

Timing Registers

7-0

PDCNT

Pixel Data Control Start

7-0

Horizontal Sync Tip Duration

7-0

Breezeway Duration

7-0

Burst Duration

7-0

CBP

Color Back Porch Duration

Table 22. Control Register Map (continued)

Reg Bit

Mnemonic

Function

7-0

XBP

Extended Color Back Porch
Duration

7-0

Active Video Region Duration

7-0

Active Video Region 2nd Half
Line Duration

7-0

Active Video Region 1st Half
Line Duration

7-0

Equalization Pulse Low Duration

7-0

Equalization Pulse High
Duration

7-0

Vertical Sync Pulse Low
Duration

7-0

Vertical Sync Pulse High
Duration

7-0

Front Proch Duration

7-6

XBP

Extended Color Back Porch
Duration

5-4

Active Video Duration

3-2

Active Video Region 1st Half
Line Duration

1-0

Active Video Region 2nd Half
Line Duration

7-5

FIELD

Field Identification (read only)

4-0

LTYPE

Line Type Identification (read
only)

7-0

CBL

Color Bar Duration

Color Space Matrix Registers

7-0

MCF1L

Matrix Coefficient #1

7-0

Reserved

Program Low

7-0

Reserved

Program Low

7-0

MCF2L

Matrix Coefficient #2

7-0

Reserved

Program Low

7-0

MCF3L

Matrix Coefficient #3

7-0

Reserved

Program Low

7-0

Reserved

Program Low

Table 22. Control Register Map (continued)

Reg Bit

Mnemonic

Function

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Note:
1. For each register listed above, all bits not specified are

reserved and should be set to logic LOW to ensure proper
operation.

Subcarrier Registers

7-0

FREQL

Subcarrier Frequency

7-0

FREQ3

Subcarrier Frequency

7-0

FREQ2

Subcarrier Frequency

7-0

FREQM

Subcarrier Frequency

7-0

SYSPHL

System Phase

7-0

SYSPHM

System Phase

7-0

BURPHL

Burst Phase

7-0

BURPHM

Burst Phase

7-0

BRSTFULL

Burst Height Maximum
Amplitude

7-0

BRST1

Burst Height 1st Intermediate
Value

7-0

BRST2

Burst Height 2nd Intermediate
Value

Table 22. Control Register Map (continued)

Reg Bit

Mnemonic

Function

7-0

Reserved

Program Low

7-0

Reserved

Program Low

7-4

MCF1M

Matrix Coefficient #1

3-0

Reserved

Program Low

7-3

Reserved

Set to 0.

2-0

MCF4M

Matrix Coefficient #4

7-3

Reserved

Set to 0.

2-0

MCF6M

Matrix Coefficient #6

7-4

Reserved

Program Low

3-0

Reserved

Program Low

7-4

Reserved

Program Low

3-0

Reserved

Program Low

SEL_CLK

DCVBS Clock Select

Reserved

Program Low

GAUSS_BVP

Gaussian Bypass Select

SEL_PIX

DCVBS Output Selection

C2DB_OFF

COMP2DB Offset Selection

2-0

Reserved

Program Low

Table 22. Control Register Map (continued)

Reg Bit

Mnemonic

Function

Control Register Definitions

Part Identification Register (0x00)

PARTID2

Reg

Bit

Name

Description

7-0

PARTID2

(Read Only) 0x97

Part Identification Register (0x01)

PARTID1

Reg

Bit

Name

Description

7-0

PARTID1

(Read Only) 0x21

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Part Identification Register (0x02)

PARTID0

Reg

Bit

Name

Description

7-0

PARTID0

(Read Only) 0x92

Revision Identification Register (0x03)

REVID0

Reg

Bit

Name

Description

7-0

REVID0

Reads back the revision number of the part.

Gamma Filters Register (0x04)

RESERVED

SRESET

SKEN

PDRM

Reg

Bit

Name

Description

7-4

RESERVED

Set to Low

SRESET

Software RESET.
When LOW, resets internal state machines and disables outputs.
When HIGH, state machines are active and outputs are enabled.

SKEN

Data KEY Enable.
When SKEN is LOW, Data keying is disabled.
When SKEN is HIGH, Data keying is enabled.

1-0

PDRM

Pixel Data Ramping Mode. Pixel Data weighting for the rising edge of
active video.

NTSC:

1/8

1/2

7/8

PAL:

1/8

3/8

5/8

7/8

Pixels are weighted on the edge.

Sample and hold the 5th pixel for the slope weighting

Hard switch

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Input Format Register (0x05)

D10FF

INMODE

OMIX

SOURCE

Reg

Bit

Name

Description

D1OFF

YCBCR Input Formatting.
When D1OFF is HIGH, 64 is subtracted from Y data path of the PD port.
When D1OFF is LOW, pixel data is passed through.

Reserved

Program Low

5-4

INMODE

Input Mode Select.
00

24 bit YC

(4:4:4)

PD[7:0] = Y PD[23:16] = C

PD[15:8] = C

10 bit D1 (YC

)

PD[23:14] = YC

at 27MHz

20 bit YC

(4:4:4)

PD[9:0] = Y PD[23:14] = C

(at 27MHz)

20 bit YC

(4:2:2)

PD[9:0] = Y PD[23:14] = C

3-2

OMIX

Overlay Mixer Select.
00

No mix PD data is always passed

Hard mix mixer performs a hard switch between PD and Overlay

Set1 mix the pixel data has the following weighting on the
transition; 0, 1/2, 1

Set2 mix the pixel data has the following weighting on the
transition; 0, 1/8, 1/2, 7/8, 1

1-0

SOURCE

Video Input Select. Chooses from internal test patterns or pixel data port.
00 PD

PORT

Modulated Ramp

INTERNAL COLOR BAR (75%)

INTERNAL COLOR BAR (100%)

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

General Control Register (0x06)

FORMAT

MODE

PDCDIR

TOUT

TSOUT

Reg

Bit

Name

Description

7-6

FORMAT

Video Format.
00

NTSC

PAL B,G,H,I,N

PAL M

Reserved

5-3

MODE

Video Mode.
000

MASTER with free-running subcarrier

001

SLAVE with free-running subcarrier

010

CCIR656 with free-running subcarrier

011

GENLOCK with subcarrier phase and frequency locked to the GRS
information.

100

MASTER with subcarrier phase reset every 8 fields

101

SLAVE with subcarrier phase reset every 8 fields

110

CCIR656 with subcarrier phase reset every 8 fields.

111

DRS-Lock with subcarrier phase and frequency locked to the DRS
information.

PDCDIR

PDC Directional Control.
When PDC is LOW, the PDC pin is an output.
When PDCDIR is HIGH, the PDC pin is an input that can override the
internally generated PDC and blank the active video of a line.

TOUT

External Sync Output Control.
When TOUT = LOW, a MPEG style field toggle is the output on pin VSOUT.
When TOUT = HIGH, a traditional vertical sync is the output on pin VSOUT.

TSOUT

External Sync Delay Control.
When the TSOUT is LOW, HSOUT, VSOUT are delayed to match
propagation delay through the chip. When TSOUT is HIGH, HSOUT,
VSOUT are aligned with the incoming data on the PD port.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Horizontal Ancillary Data Control Register (0x07)

LDFID

SKFLIP

DDSRST

RESERVED

ANCFREN

ANCPHEN

ANCTREN

Reg

Bit

Name

Description

LDFID

Field Lock Select. When LDFID is HIGH, the FLD[2:0] pins are used as
inputs to lock the field the that the TMC2192 is encoding. 5 PXCK's after
the falling edge of HSIN the FLD[2:0] pins are sampled. When LDFID is
LOW, the FLD[2:0] pins output the current field that is being encoded.

SKFLIP

Soft Key Inversion.
When SKFLP is LOW, the key generated by the data keying is a normal
state. When SKFLP is HIGH, the key generated by the data keying is a
inverted state.

DDSRST

DDS Reset. By inserting a logic HIGH into this register the DDS
accumulator is reset to SYSPH value at the start of the next field 1 and
DDSRST is reset LOW. This enables the DDS to be reset when the
encoder is operating with a free running subcarrier.

4-3

RESERVED

ANCFREN

Ancillary Frequency Enable.
When HIGH, the encoder gets subcarrier frequency data (FREQ3-0) from
incoming ancillary data (in accordance with FRV bit). When LOW,
FREQ3-0 registers contain the subcarrier frequency data.

ANCPHEN

Ancillary Phase Enable.
When HIGH, the encoder gets subcarrier phase offset data (SCHPHL and
SCHPHM) from incoming ancillary data (in accordance with PHV bit).
When LOW, a default value of 0000h is used for subcarrier phase.

ANCTREN

Ancillary Timing Enable.
When HIGH, the encoder decodes incoming ancillary data to determine
video timing (FIELD and SVF). When LOW, the ancillary timing reference
data is ignored.

Ancillary Data ID Register (0x08)

ANCID

Reg

Bit

Name

Description

7-0

ANCID

Ancillary Data Identification.
Bits 7-0 determine the ancillary data identification. Bit 0 is an odd parity bit.
The value in this register must match that of the incoming ancillary data.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Keying/Overlay Engine Register (0x09)

HKEN

BUKEN

SKEXT

DKDIS

EKDIS

FKDIS

LAYMODE

Reg

Bit

Name

Description

HKEN

Hardware KEY Enable.
When LOW, the KEY pin is ignored.
When HIGH, the KEY pin is enabled.

BUKEN

Burst KEY Enable.
When LOW, the output video burst is generated internally.
When HIGH, the output video burst is taken from the CVBS port.

SKEXT

Data KEY Operation Select.
When LOW, data keying is allowed only during active video window.
When HIGH, data keying is allowed during frame.

DKDIS

Y Data KEY Disable.
When LOW, Y input data is enabled for data keying.
When HIGH, Y input data is ignored for data keying.

EKDIS

Data KEY Disable.

When LOW, C

input data is enabled for data keying.

When HIGH, C

input data is ignored for data keying.

FKDIS

Data KEY Disable.

When LOW, C

input data is enabled for data keying.

When HIGH, C

input data is ignored for data keying.

1-0

LAYMODE

Layer Assignment Select.

Mode

BACKGND
Source

MIDGND
Source

Key

FOREGND
Source

Key

OVERLAY

0L4-0

CVBS

KEY

CVBS

KEY

OVERLAY

OL4-0

CVBS

OVERLAY

OL4-0

KEY

CVBS

KEY

OVERLAY

OL4-0

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Key Value Register (0x0A)

DKEYMAX

Reg

Bit

Name

Description

7-0

DKEYMAX

Y Maximum Data Key Value.
DKEYMAX is compared against the 8 MSB's of Y channel. If DKEYMAX is
greater or equal to Y and DKEYMIN less than Y then a match is signaled.

Key Value Register (0x0B)

DKEYMIN

Reg

Bit

Name

Description

7-0

DKEYMIN

Y Minimum Data Key Value.
DKEYMIN is compared against the 8 MSB's of Y channel. If DKEYMAX is
greater or equal to Y and DKEYMIN less than Y then a match is signaled.

Key Value Register (0x0C)

EKEYMAX

Reg

Bit

Name

Description

7-0

EKEYMAX

Maximum Data Key Value.

EKEYMAX is compared against the 8 MSB's of C

channel. If EKEYMAX is

greater or equal to C

and EKEYMIN less than C

then a match is signaled.

Key Value Register (0x0D)

EKEYMIN

Reg

Bit

Name

Description

7-0

DKEYMIN

Minimum Data Key Value.

EKEYMIN is compared against the 8 MSB's of C

channel. If EKEYMAX is

greater or equal to C

and EKEYMIN less than C

then a match is signaled

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

DAC Control Register (0x11)

DRSSEL

RESERVED

COMP2DB

SINEN

REFSEL

LUMDIS

CHRMDIS

BURSTDIS

Reg

Bit

Name

Description

DRSSEL

DRS Selection.
When DRSSEL is HIGH, PD[7:0] is routed to the DRS detection block.
When DRSSEL is LOW, CVBS[9:2] is routed to the DRS detection block.

RESERVED

Program Low

COMP2DB.

Composite 2 Overflow Control.
When COMP2DB is HIGH, the digital range of the composite sumer is 0 to
2047 with half the digital resolution. When COMP2DB is LOW, the digital
output of the composite summer is 0 to 1023, all values exceeding 1023 or
below 0 are clipped.

SINEN

X/Sine(X) Filter Enable.
When SINEN is LOW, the X/Sin(X) filter is bypassed.
When SINEN is HIGH, the X/Sin(X) filter is used to compensate for the
DAC roll-off at high frequencies.

RESERVED

Program Low

LUMDIS

Luma Disable.
When LUMDIS is LOW, the luminance data on the composite data path is
enabled. When LUMDIS is HIGH, the luminance data on the composite
data path is disabled.

CHRMDIS

Chroma Disable.
When CHRMDIS is LOW, the chrominance data on the composite data
path is enabled. When CHRMDIS is HIGH, the chrominance data on the
composite data path is disabled.

BURSTDIS

Burst Disable.
When BURSTDIS is LOW, the burst is enabled.
When BURSTDIS is HIGH, the burst is disabled.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

VBI Ped Enable Register (0x14)

VBIPEDEM

Reg

Bit

Name

Description

7-0

VBIPEDEM

VBI Pedestal Enable, Even Fields.
VBIPEDEM is the bits 15-8 of VBIPEDE[15:0]. VBIPEDE controls the
addition of pedestal on a line by line basis from line 10 in NTSC
(VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field
of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263
inclusive.

VBI Ped Enable Register (0x15)

VBIPEDEL

Reg

Bit

Name

Description

7-0

VBIPEDEL

VBI Pedestal Enable, Even Fields.
VBIPEDEL is the bits 7-0 of VBIPEDE[15:0]. VBIPEDE controls the
addition of pedestal on a line by line basis from line 10 in NTSC
(VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field
of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263
inclusive.

VBI Ped Enable Register (0x16)

VBIPEDOM

Reg

Bit

Name

Description

7-0

VBIPEDOM

VBI Pedestal Enable, Odd Fields.
VBIPEDOM is the bits 14-7 of VBIPEDO[14:0]. VBIPEDO controls the
addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =
HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.
VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

VBI Ped Enable Register (0x17)

VBIPEDOL

HVA

Reg

Bit

Name

Description

7-1

VBIPEDOM

VBI Pedestal Enable, Odd Fields.
VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the
addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =
HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.
VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

HVA

Horizontal and Vertical Sync Alignment.
When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior
to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is
allowed to vary from HSIN by

±32 pixels.

Vertical Blanking Interval Enable Register (0x18)

Reserved

GLKCTL1

GLKCTL0

VBIENF1

Reg

Bit

Name

Description

Reserved

GLKCTL1

Genlock Control Register 1.
When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored.
When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the
PALODD flip of the subcarrier.

GLKCTL0

Genlock Control Register 0.
When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored.
When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls
the field sequence in the FVHGEN.

4-0

VBIENF

VBI Active Video Enable, Field 1.
The value of VBIENF1 determines which line blanking stops and active line
for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for
PAL starting from line 1 to line 32.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Vertical Blanking Interval Enable Register (0x19)

SHORT

T512

HALFEN

VBIENF2

Reg

Bit

Name

Description

SHORT

Test Register. Program LOW.

T512

EH/SL Offset Control Bit.
When LOW, the true value of EH and SL is offset by 256.
When HIGH, the true value of EH and SL is offset by 512.

HALFEN

Half Line Enable.
When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL).
When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of
active video.

4-0

VBIENF2

VBI Active Video Enable, Field 2.
The value of VBIENF2 determines which line blanking stops and active line
for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for
PAL starting from line 1 to line 32.

Pedestal Height Register (0x1A)

Reserved

PEDHGT1

Reg

Bit

Name

Description

Reserved

6-0

PEDHGT1

Composite Pedestal Height.
PEDHGT1 is a 2's comp value producing a pedestal height from -22.1 IRE
to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5
IRE pedestal for NTSC-M results from a hex code of 0010110b.

Closed Caption Register (0x1C)

CCD1

Reg

Bit

Name

Description

7-0

CCD1

First Byte of CC Data.
Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if
CCPAR is HIGH.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Closed Caption Register (0x1D)

CCD2

Reg

Bit

Name

Description

7-0

CCD2

Second Byte of CC Data.
Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if
CCPAR is HIGH

Closed Caption Register (0x1E)

CCON

CCRTS

CCPAR

CCFLD

CCLINE

Reg

Bit

Name

Description

CCON

Enable CC Data Packet.
Command the CC data generator to send either CC data or a NULL byte
whenever the specified line is transmitted.

CCRTS

Request To Send Data.
This bit is set HIGH by the user when bytes 0x1C and 0x1D have been
loaded with the next two bytes to be sent. When the encoder's line count
reaches preceding the line specified in bits 4-0 of this register the data will
be transferred from registers 0x1C and 0x1D, and RTS will be RESET
LOW. A new pair of bytes may then be loaded into registers 0x1C and
0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL
bytes will be sent.

CCPAR

Auto Parity Generation.
When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D
with a calculated ODD parity. When set LOW, the CC processor transmits
the 16 bits exactly as loaded into registers 0x1C and 0x1D.

CCFLD

CC Field Select.
When LOW, CC data is transmitted on the selected line of ODD fields.
When HIGH, it is sent on EVEN fields.

3-0

CCLINE

CC Line Select.
Defines (with an offset) the line on which CC data are transmitted.

Timing Register (0x1F)

PDCNT

Reg

Bit

Name

Description

7-0

PDCNT

Pixel Data Control Start.
PDCNT determines the number of pixels (PCK's) from the midpoint of the
falling edge of horizontal sync to the rising edge of PDC on active video
lines.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Timing Register (0x20)

Reg

Bit

Name

Description

7-0

Horizontal Sync Tip Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x21)

Reg

Bit

Name

Description

7-0

Breezeway Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x22)

Reg

Bit

Name

Description

7-0

Burst Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x23)

CBP

Reg

Bit

Name

Description

7-0

CBP

Color Back Porch Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x24)

XBP

Reg

Bit

Name

Description

7-0

CBP

Extended Color Back Porch Duration.
This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023
PCK cycles.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Timing Register (0x25)

Reg

Bit

Name

Description

7-0

Active Video Region Duration.
This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023
PCK cycles.

Timing Register (0x26)

Reg

Bit

Name

Description

7-0

Active Video Region 2

Half Line Duration.

This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023
PCK cycles.

Timing Register (0x27)

Reg

Bit

Name

Description

7-0

Active Video Region 1

Half Line Duration.

This 8 bit register holds the LSB's of a 10 bit value extending from 0 to 1023
PCK cycles.

Timing Register (0x28)

Reg

Bit

Name

Description

7-0

Equalization Pulse Low Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Timing Register (0x29)

Reg

Bit

Name

Description

7-0

Equalization Pulse High Duration.
This 8 bit register holds 8 LSB's of EH, The addition of 256 or 512 is
controlled by T512. The range is either 256 to 511 PCK cycles or 512 to
767 PCK cycles.

Timing Register (0x2A)

Reg

Bit

Name

Description

7-0

Vertical Sync Pulse Low Duration.
This 8 bit register holds 8 LSB's of SL, The addition of 256 or 512 is
controlled by T512. The range is either 256 to 511 PCK cycles or 512 to
767 PCK cycles.

Timing Register (0x2B)

Reg

Bit

Name

Description

7-0

Vertical Sync Pulse High Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Timing Register (0x2C)

Reg

Bit

Name

Description

7-0

Front Porch Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Timing Register (0x2D)

XBP

Reg

Bit

Name

Description

7-6

XBP

Extended Color Back Porch Duration.
2 MSB's of the 10 bit XBP, extending from 0 to 1023 PCK cycles.

5-4

Active Video Duration.
2 MSB's of the 10 bit VA, extending from 0 to 1023 PCK cycles.

3-2

Active Video Region 1

Half Line Duration.

2 MSB's of a 10 bit VB, extending from 0 to 1023 PCK cycles.

1-0

Active Video Region 2

Half Line Duration.

2 MSB's of a 10 bit VC, extending from 0 to 1023 PCK cycles.

Timing Register (0x2E)

FIELD

LTYPE

Reg

Bit

Name

Description

7-5

FIELD

Field Identification. (READ ONLY)
These three bits are updated 12 PXCK periods after each vertical sync.
They allow the user to determine field type on a continuous basis

4-0

LTYPE

LineType Identification (READ ONLY)
These three bits are updated 5 PXCK periods after each horizontal sync.
They allow the user to determine line type on a continuous basis.

Timing Register (0x2F)

CBL

Reg

Bit

Name

Description

7-0

CBL

Color Bar Duration.
This 8 bit register holds a value extending from 0 to 255 PCK cycles.

Color Space Matrix Register (0x30)

MCF1L

Reg

Bit

Name

Description

7-0

MCF1L

Matrix Coefficient #1.
Bits 7-0 of MCF1.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Color Space Matrix Register (0x3F)

SEL_CLK

RESERVED

GAUSS_BYP

SEL_PIX

C2DB_OFF

NMEH

CSMFMT

Reg

Bit

Name

Description

SEL_PIX

DCVBS Output Selection.
When SEL_PIX is HIGH, the interpolated pixel data is selected as the
output for the DCVBS port. When SEL_PIX is LOW, the non-interpolated
pixel data is selected as the output for the DCVBS port.

RESERVED

Program Low

GAUSS_BYP

Gaussian Bypass Select.
When GAUSS_BYP is LOW, the gaussian filter is enabled.
When GAUSS_BYP is HIGH, the gaussian filter is bypassed.

SEL_CLK

DCVBS Clock Select.
When SEL_CLK is LOW, the DCVBS output is clocked at the PXCK.
When SEL_CLK is HIGH, the DCVBS output is clocked at the PCK.

C2DB_OFF

COMP2DB Offset Selection.
When C2DB_OFF is HIGH an offset of 256 is added to the COMP2 output
allowing the chrominance data that extends below the sync level to be
passed through the outputs.

2-0

RESERVED

Program Low

Subcarrier Register (0x40)

FREQL

Reg

Bit

Name

Description

7-0

FREQL

Subcarrier Frequency.
Bits 7-0 of the subcarrier frequency FREQL[31:0].

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Subcarrier Register (0x41)

FREQ3

Reg

Bit

Name

Description

7-0

FREQ3

Subcarrier Frequency.
Bits 15-8 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x42)

FREQ2

Reg

Bit

Name

Description

7-0

FREQ2

Subcarrier Frequency.
Bits 23-16 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x43)

FREQM

Reg

Bit

Name

Description

7-0

FREQM

Subcarrier Frequency.
Bits 31-24 of the subcarrier frequency FREQL[31:0].

Subcarrier Register (0x44)

SYSPHL

Reg

Bit

Name

Description

7-0

SYSPHL

System Phase.
Bits 7-0 of the video phase offset SYSPH[15:0].

Subcarrier Register (0x45)

SYSPHM

Reg

Bit

Name

Description

7-0

SYSPHM

System Phase.
Bits 15-8 of the video phase offset SYSPH[15:0].

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Definitions

(continued)

Subcarrier Register (0x46)

BURPHL

Reg

Bit

Name

Description

7-0

BURPHL

Burst Phase.
Bits 7-0 of the burst phase offset BURPH[15:0].

Subcarrier Register (0x47)

BURPHM

Reg

Bit

Name

Description

7-0

BURPHM

Burst Phase.
Bits 15-8 of the burst phase offset BURPH[15:0].

Burst Height Register (0x48)

BRSTFULL

Reg

Bit

Name

Description

7-0

BRSTFULL

Burst Height Maximum Amplitude.
The 8 bit value assigned to U burst component in NTSC and to the U and V
components in PAL for the maximum burst amplitude. The burst envelopes
midpoint is derived from BRSTFULL. The value programmed into
BRSTFULL needs to be .707 of the magnitude of the burst vector.

Burst Height Register (0x49)

BRST1

Reg

Bit

Name

Description

7-0

BRST1

Burst Height 1st Intermediate Value.
The 8 bit value assigned to U burst component in NTSC and to the U and V
components in PAL for the first intermediate value of the burst envelope.
The value programmed into BRST1 needs to be .707 of the magnitude of
the burst vector.

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Absolute Maximum Ratings

(beyond which the device may be damaged)

Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating

conditions. Functional operation under any of these conditions is NOT implied.

2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current, flowing into the device.

Parameter

Min.

Max.

Unit

Power Supply Voltage

-0.5

7.0

Digital Inputs

Applied Voltage

-0.5

+ 0.5

Forced Current

3,4

-20.0

20.0

Digital Outputs

Applied Voltage

-0.5

+ 0.5

Forced Current

3,4

-20.0

20.0

Short Circuit Duration (Single Output in HIGH state to GND)

second

Analog Output Short Circuit Duration (Single output to GND)

Infinite

Temperature

Operating, Ambient

-20

+110

°C

Operating, Junction, Plastic package

+150

°C

Lead, Soldering (10 seconds)

+300

°C

Vapor Phase Soldering (1 minute)

+220

°C

Storage

-65

+150

°C

Operating Conditions

Parameter

Min.

Nom.

Max.

Units

Power Supply Voltage

4.75

5.0

5.25

Input Voltage, Logic HIGH

TTL Compatible Inputs

2.0

CMOS Compatible Inputs

0.7V

Input Voltage, Logic LOW

TTL Compatible Inputs

GND

0.8

CMOS Compatible Inputs

GND

0.3V

Output Current, Logic HIGH

-2.0

Output Current, Logic LOW

4.0

REF

External Reference Voltage

1.235

REF

D/A Converter Reference Current (I

REF

= V

REF

/ R

REF

flowing out of the R

REF

pin)

1.020

REF

Reference Resistor, V

REF

= Nom.

1210

OUT

Total Output Load Resistance

37.5

Ambient Temperature, Still Air

°C

Pixel Interface

PXL

Pixel Rate

Mpps

PXCK

Master Clock Rate, 2x pixel rate

MHz

PWHPX

PXCK Pulse Width, HIGH

PWLPX

PXCK Pulse Width, LOW

17.5

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Electrical Characteristics

Notes:
1. Typical I

with V

= +5.0 Volts and T

= 25

°C.

2. Timing reference points are at the 50% level.

Switching Characteristics

Notes:
1. Timing reference points are at the 50% level.
2. Analog C

LOAD

<10 pF, D

7-0

load <40 pF.

3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2)

and PXCK, as established by the hardware RESET.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Power Supply Current

= Max., f

PXCK

= 27MHz

335

375

DDQ

Power Supply Current
(D/A disabled)

= Max., f

PXCK

= 27MHz

Voltage Reference Output

1.235

Input Bias Current, V

REF

= Nom.

µA

Input Current, Logic HIGH

= Max., V

= V

µA

Input Current, Logic LOW

= Max., V

= GND

-10

µA

Output Voltage, Logic HIGH

= Max.

2.4

Output Voltage, Logic LOW

= Max.

0.4

OZH

Hi-Z Leakage current, HIGH

= Max., V

= V

µA

OZL

Hi-Z Leakage current, LOW

= Max., V

= GND

-10

µA

Digital Input Capacitance

= 25

°C, f = 1MHz

Digital Output Capacitance

= 25

°C, f = 1MHz

Video Output Compliance
Voltage

-0.3

2.0

OUT

Video Output Resistance

OUT

Video Output Capacitance

OUT

= 0 mA, f = 1 MHz

Parameter

Conditions

Min.

Typ.

Max.

Units

PIPES

Pipeline Delay

PD to Analog Out
PD to DCVBS

64
66

PXCK

Periods

DOZ

Output Delay, CS to low-Z

DOM

Output Delay, CS to Data Valid

HOM

Output Hold Time, CS to hi-Z

Output Delay

PXCK to HSOUT, VSOUT,
PDC, LINE, FLD

D/A Output Current Risetime

10% to 90% of full-scale

D/A Output Current Falltime

90% to 10% of full-scale

DOV

Analog Output Delay

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

System Performance Characteristics

Notes:
1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns.
2. Analog CLOAD <10 pF, D7-0 load <40 pF.

Parameter

Conditions

Min.

Typ.

Max.

Units

RES

D/A Converter Resolution

Bits

Integral Linearity Error

0.25

Differential Linearity Error
(monotonic)

0.10

Gain Error

±7.5 %FS

Differential Phase

PXCK = 27.00 MHz,40 IRE Ramp

0.5

degree

Differential Gain

PXCK = 27.00 MHz,40 IRE Ramp

0.9

SKEW

CHROMA to LUMA Output
Skew

PSRR

Power Supply Rejection
Ratio

f=1kHz

0.5

%/%V

Applications Discussion

The suggested output reconstruction filter is shown in Figure
29. The phase and frequency response for the encoder and
the reconstruction filter is shown in Figure 30.

Figure 28. Typical Analog Reconstruction Filter

Figure 29. Overall Response

The circuit in Figure 31 shows the connection of power sup-
ply voltages, output reconstruction filters and the external
voltage reference. All V

pins should be connected to the

same power source.

The full-scale output voltage level for each D/A:

OUTx

= I

OUTx

x R

= K x I

REFx

x R

= K x (V

REF

REFx

) x R

where:

· I

OUTx

is the full-scale output current sourced by the D/A

converter.

· R

is the resistive load on the D/A output pin.

· K is a constant for the TMC2192 D/A converters (approx-

imately equal to 34).

· I

REFx

is the reference current flowing out of the R

REFx

pin to ground.

· V

REF

is the voltage measured on the V

REF

pin.

· R

REFx

is the total resistance connected between the

REFx

pin and ground.

The reference voltage in Figure 31 is from an LM185 1.2
Volt band-gap reference. The suggested trim is designed to
give

±10% of trim around 5K Ohms. This R

REFx

sets the

"gain" for that D/A converter. Varying R

REFx

±10% will

cause the full-scale output voltage on the D/A to vary by
±10%.

An alternative output reconstruction filter is the Microelec-
tronic Modules Corp. ST-163E, which contains 4 indepen-
dent reconstruction filter. The phase and frequency response
of this filter is shown in the Output Low-Pass Filters Section
of this data sheet.

A_IN

A_OUT

330pF

27pF

100pF

R9
75

L6
1.0

µH

65-6294-31

D1
DIODE
SCHOTTKY

L5 1.8

µH

D2
DIODE
SCHOTTKY

65-6294-32

Attenuation (dB)

Frequency (MHz)

-10

-20

-30

-40

180

270

360

Phase (deg)

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Layout Considerations

Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Wire-wrap is
not an option. Overall system performance is strongly influ-
enced by the board layout. Capacitive coupling from digital
to analog circuits may result in poor picture quality. Con-
sider the following suggestions when doing the layout:

Keep analog traces (C

BYPx

, V

REF

, R

REF

, DACx) as

short and far from all digital signals as possible. The
TMC2192 should be located near the board edge, close
to the analog output connectors.

The power plane for the TMC2192 should be separate
from that which supplies other digital circuitry. A single
power plane should be used for all of the V

pins. If

the power supply for the TMC2192 is the same for the
system's digital circuitry, power to the TMC2192 should
be filtered with ferrite beads and 0.1

µF capacitors to

reduce noise.

The ground plane should be solid, not cross-hatched.
Connections to the ground plane should be very short.

Decoupling capacitors should be applied liberally to
pins. For best results, use 0.1

µF capacitors. Lead lengths

should be minimized. Ceramic chip capacitors are the
best choice.

If there is dedicated digital power plane, it should not
overlap the TMC2192 footprint, the voltage reference,
or the analog outputs. Capacitive coupling of digital
power supply noise from this layer to the TMC2192 and
its related analog circuitry can have an adverse effect on
performance.

The PXCK should be handled carefully. Jitter and noise
on this clock or its ground reference will translate to
noise on the video outputs. Terminate the clock line
carefully to eliminate overshoot and ringing.

Connect all unused inputs to the TMC2192 to either
ground or V

. Do not leave them unconnected.

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Figure 30. Typical Layout

LPF

{Schematic}

A_IN

A_OUT

ST-163E

{Schematic}

AOUT

DOUT

BOUT

COUT

CIN

BIN

DIN

AIN

VDD

VCC

VDD

CONNECT Cx TO VDDA PIN

AND CBYPy PIN DIRECTLY

STUFF EITHER C54 OR D4

PD[0..23]

OLENG[0..5]

DCVBS3

PD2

PD14

PD18

DCVBS1

DCVBS4

DCVBS6

HSOUT

ECVBS1

PD19

OLENG3

ECVBS9

PD22

PD23

DCVBS5

PD20

PD11

ECVBS[0..9]

PD13

ECVBS0

PD4

PD12

DCVBS2

PD7

PD8

PD3

PD5

PD16

OLENG2

VSOUT

ECVBS4

ECVBS3

ECVBS2

DCVBS9

PD21

ECVBS8

SDA

PD6

OLENG4

DCVBS0

DCVBS7

ECVBS6

ECVBS5

DCVBS[0..9]

PD0

PD9

DCVBS8

ECVBS7

PD17

PD1

PD15

OLENG0

OLENG1

OLENG5

PD10

EMCU[0..3]

ESA0

EMCU3

EDCVBSEN\

EMCU1

ESA1

EMCU2

EMCU0

ERESET\

SCL

R32

8.25K Ohm

R33

8.25K Ohm

R35

8.25K Ohm

R31

10K Ohm

R28

10K Ohm

R29

10K Ohm

R40

4K7

TP27

VSOUT

TP28

HSOUT

TP26

PXCK

TP29

HSIN

TP30

VSIN

JP13

C58

0.1uF

C57

0.1uF

C56

0.1uF

TP16

RDA

TP18

DA1

TP20

DA2

TP22

DA3

TP24

DA4

TP17

ORDA

TP19

ODA1

TP21

ODA2

TP23

ODA3

TP25

ODA4

RDAC

DAC1

DAC2

DAC3

DAC4

C55

0.1uF

C67

0.1uF

C63

0.1uF

C62

0.1uF

C66

0.1uF

C65

0.1uF

C61

0.1uF

C64

0.1uF

C68

0.1uF

R37

10K Pot

R36

10K Pot
1

R39

10K Pot

R34

8.25K Ohm

R30

10K Ohm

R38

10K Pot
1

C54

0.1uF

1.235V

R27

3.3K Ohm

TMC2192KJC

V_REF

VDDA

COMP

C_COMP

AGND

CHROMA

C_CHROMA

VDDA

R_CHROMA

AGND

LUMA

C_LUMA

VDDA

R_LUMA

AGND

VDDA

AGND

KEY

OL4

OL3

OL2

OL1

OL0

DGND

PD23

PD22

PD21

PD20

PD19

PD18

PD17

PD16

PD15

PD14

PD13

PD12

VDD

DGND

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD0

PD1

VDD

VSIN

HSIN

SER

CS/SCL

R/W/SDA

A1/SA1

A0/SA0

CVBS0

CVBS1

CVBS2

CVBS3

CVBS4

CVBS5

CVBS6

CVBS7

CVBS8

CVBS9

PXCK

PDC

HSOUT

VSOUT

DCVEN

RESET

DGND

VDD

LINE4

LINE3

FLD0

FLD1

FLD2

LINE0

LINE1

LINE2

R_COMP

AGND

100

VDD

DGND

PD[0..23]

ECVBS[0..9]

EPXCK

HSIN

VSIN

DCVBS[0..9]

HSOUT

VSOUT

SDA

OLENGI[0..5]

EMCU[0..3]

SCL

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Mechanical Dimensions

100-Lead MQFP

Lead Detail

A A2

-C-

Lead Coplanarity

Seating Plane

ccc

See Lead Detail

Pin 1 Indentifier

Base Plane

Datum Plane

° Min.

.20 (.008) Min.

.13 (.30)
.005 (.012)

.13 (.005) R Min.

0.076" (1.95mm) Ref

.134

3.40

Symbol

Inches

Min.

Max.

Min.

Max.

Millimeters

Notes

.010

.25

.015

.38

.100

.120

2.55

3.05

.008

3, 5

.22

.009

.23

.005

.13

.667

.687

16.95

17.45

.0256 BSC

.65 BSC

.028

.040

.73

1.03

100

.004

.12

ccc

.904

.923

22.95

23.45

.783

.791

19.90

20.10

.547

.555

13.90

14.10

Notes:

All dimensions and tolerances conform to ANSI Y14.5M-1982.

Controlling dimension is millimeters.

Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.

"L" is the length of terminal for soldering to a substrate.

"B" & "C" includes lead finish thickness.

TMC2192

PRODUCT SPECIFICATION

8/13/03 0.0m 002

Stock#DS30002192

2003 Fairchild Semiconductor Corporation

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OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

2. A critical component in any component of a life support

device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
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Ordering Information

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Product Number

Temperature Range

Screening

Package

Package Marking

TMC2192KHC

= 0

°C to 70°C

Commercial

100-pin MQFP

TMC2192KHC

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TMC2192

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TMC2192