X9448.fm
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Mixed Signal with 2-Wire Interface
X9448
Dual Digitally Controlled Potentiometer (XDCP
TM
) & Voltage Comparator
FEATURES
Two digitally controlled potentiometers and two
voltage comparators in one package
2-wire serial interface
Register oriented format
--Direct read/write wiper position
--Store as many as four positions per pot
Fast response comparator
Enable, latch, or shutdown comparator outputs
through ACR
Auto-recall of WCR and ACR data from R0
Hardware write protection, WP
Separate analog and digital/system supplies
Direct write cell
--Endurance100,000 data changes per bit per
register
--Register data retention100 years
16-bytes of EEPROM memory
Power saving feature and low noise
Two 10K
or two 2.5K
potentiometers
Resolution: 64 taps each pot
24-lead TSSOP and 24-lead SOIC packages
DESCRIPTION
The X9448 integrates two nonvolatile digitally con-
trolled potentiometers (XDCP) and two voltage com-
parators on a CMOS monolithic microcircuit.
The X9448 contains two resistor arrays, each com-
posed of 63 resistive elements. Between each element
and at either end are tap points accessible to the wiper
elements. The position of the wiper element on the
array is controlled by the user through the two wire
serial bus interface.
Each potentiometer has an associated voltage com-
parator. The comparator compares the external input
voltage V
NI
with the wiper voltage V
W
and sets the out-
put voltage level to a logic high or low.
Each resistor array and comparator has associated
with it a wiper counter register (WCR), analog control
register (ACR), and eight 6-bit data registers that can
be directly written and read by the user. The contents
of the wiper counter register controls the position of
the wiper on the resistor array. The contents of the
analog control register controls the comparator and its
output. The potentiometer is programmed with a
2-wire serial interface
BLOCK DIAGRAM
V
OUT (0,1)
(R
0
-R
3
)
0,1
Interface
and
Control
Circuitry
SCL
SDA
A0
A1
A2
A3
V
H (0,1)
V
L (0,1)
WP
V
W (0,1)
V
NI (0,1)
+
WCR
0,1
(R
0
-R
3
)
0,1
ACR
0,1
XDCP is a trademark of Xicor, Inc.
X9448
Characteristics subject to change without notice.
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PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9448.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Device Address (A
0
A
3
)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9448. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins
V
H
(V
H0
V
H1
), V
L
(V
L0
V
L1
)
The V
H
and V
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
(V
W0
V
W1
)
The wiper output is equivalent to the wiper output of a
mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input V
NI0
, V
NI1
V
NI0
and V
NI1
are the input voltages to the plus (non-
inverting) inputs of the two comparators.
Buffered Voltage Outputs V
OUT0
, V
OUT1
The V
OUT0
, and V
OUT1
are the buffered voltage
comparator outputs enabled by respective bits in the
volatile analog control register.
Hardware Write Protect Input WP
The
WP
pin when low prevents nonvolatile writes to the
wiper counter and analog control registers.
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.
System Supply V
CC
and Ground V
SS
The system supply V
CC
and its reference V
SS
is used
to bias the interface and control circuits.
PIN CONFIGURATION
V
CC
V
L0
V
H0
WP
SDA
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
V+
V
OUT0
V
NI0
NC
A0
NC
A
3
SCL
NC
V
NI1
SOIC
X9448
V
SS
V
W0
13
11
12
A
2
V
L1
V
H1
V
W1
V
OUT1
V
CC
V
L1
V
H1
WP
SDA
A
2
A
3
SCL
NC
V
NI1
TSSOP
V
SS
V
W1
A
1
V
L0
V
H0
V
W0
V-
V
OUT1
NC
V+
V
OUT0
V
NI0
A
0
NC
V-
15
14
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
X9448
13
11
12
15
14
X9448
Characteristics subject to change without notice.
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PIN NAMES
PRINCIPLES OF OPERATION
The X9448 is a highly integrated microcircuit incorpo-
rating two resistor arrays, two voltage comparators
and their associated registers and counters; and the
serial interface logic providing direct communication
between the host and the digitally-controlled potenti-
ometers and voltage comparators.
Serial Interface
The X9448 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9448 will be considered a slave device
in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9448 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9448 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9448 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9448 will respond with a final acknowledge.
Array Description
The X9448 is comprised of two resistor arrays and two
voltage comparators. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (V
H
and V
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Symbol
Description
SCL
Serial Clock
SDA
Serial Data
A0-A3
Device Address
V
H0
V
H1
,
V
L0
V
L1
Potentiometers (terminal equivalent)
V
W0
V
W1
Potentiometers (wiper equivalent)
V
NI0
, V
NI1
Comparator Input Voltages
V
OUT0,
V
OUT1
Buffered Comparator Outputs
WP
Hardware Write Protection
V+,V-
Analog and Voltage Comparator
Supplies
V
CC
System/Digital Supply Voltage
V
SS
System Ground
NC
No Connection
X9448
Characteristics subject to change without notice.
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Voltage Comparator
The comparator compares the wiper voltage V
W
with
the external input voltage V
NI
. The comparator and its
logic level output are controlled by the Shutdown,
Latch, and Enable bits of the analog control register
(ACR). Enable connects the comparator output to the
V
OUT
pin, Latch memorizes the output logic state, and
Shutdown removes the analog section supply voltages
to save power. The analog control register is pro-
grammed using the two wire serial interface.
The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9448 this
is fixed as 0101[B].
Figure 1. Address/Identification Byte Format
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9448 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9448 to respond with an acknowledge. The A
0
A
3
inputs can be actively driven by CMOS input sig-
nals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal nonvol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9448 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9448 is
still busy with the write operation no ACK will be
returned. If the X9448 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of two pots or one of two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
1
0
0
A3
A2
A1
A0
Device Type
Identifier
Device Address
1
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation
Issue
Instruction
PROCEED
Issue STOP
NO
YES
YES
PROCEED
Issue STOP
NO
I1
I2
I3
I0
R1
R0
P1
P0
WCR and ACR Select
Register
Select
Instructions
X9448
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Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1 P0
A
C
K
SCL
SDA
S
T
O
P
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
P1 P0 R1 R0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D5 D4 D3 D2
D1 D0
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last two bits (P1 and P0)
select which one of the two potentiometers or which
one of the two voltage comparators is to be affected by
the instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
STPWV
. A transfer from the Wiper
Counter Register current wiper position to a data regis-
ter is a write to nonvolatile memory and takes a mini-
mum of t
WR
to complete. The transfer can occur
between one of the two potentiometers or one of the
two voltage comparators and one of its associated reg-
isters; or it may occur globally, wherein the transfer
occurs between both of the potentiometers and voltage
comparators and one of their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure 4.
These instructions transfer data between the host and
the X9448; either between the host and one of the data
registers or directly between the host and the wiper
counter and analog control registers. These instruc-
tions are: read wiper counter register or analog control
register, read the current wiper position of the selected
pot or the comparator control bits, Write wiper counter
register or analog control register, i.e. change current
wiper position of the selected pot or control the voltage
comparator; read data register, read the contents of the
selected nonvolatile register; write data register, write a
new value to the selected data register. The bit struc-
tures of the instructions are shown in Figure 6.
The increment/decrement command is different from
the other commands. Once the command is issued
and the X9448 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V
L
terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
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