PRELIMINARY DATA SHEET
FP750SOT343
P
ACKAGED
L
OW
N
OISE
,
M
EDIUM
P
OWER
PHEMT
Phone: (408) 988-1845
http:// www.filss.com
Revised: 2/01/02
Fax: (408) 970-9950
Email: sales@filss.com
FEATURES
0.5 dB Noise Figure at 2 GHz
21 dBm P-1dB 2 GHz
17 dB Power Gain at 2 GHz
33 dBm IP3 at 2 GHz
45% Power-Added-Efficiency
DESCRIPTION AND APPLICATIONS
The FP750SOT343 is a packaged AlGaAs/InGaAs/AlGaAs pseudomorphic high electron mobility
transistor (pHEMT) intended for applications requiring low noise figure, medium output power
and/or high dynamic range. It utilizes a 0.25
m x 750
m Schottky barrier gate, defined by
electron-beam photolithography. The FP750's active areas are passivated with Si
3
N
4
, and the
SOT343 (also known as SC-70) package is ideal for low-cost, high-performance applications that
require a surface-mount package.
The FP750SOT343 is designed for commercial systems for use in low noise amplifiers and
oscillators operating over the RF and Microwave frequency ranges. The low noise figure makes it
appropriate for use in receivers in WLL/RLL, WLAN, and GPS. This device is also suitable for
PCS and GSM base station front-ends.
ELECTRICAL SPECIFICATIONS @ T
Ambient
= 25C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Saturated Drain-Source Current
I
DSS
V
DS
= 2 V; V
GS
= 0 V
180
220
265
mA
Power at 1-dB Compression
P-1dB
f=2GHz; V
DS
= 3.3 V; I
DS
= 110mA
20
21
dBm
Power Gain at 1-dB Compression
G-1dB
f=2GHz; V
DS
= 3.3 V; I
DS
= 110mA
16
17
dB
Power-Added Efficiency
PAE
f=2GHz; V
DS
= 3.3 V;
I
DS
= 110mA; P
OUT
= 21 dBm
45
%
f=2GHz; V
DS
= 3.3V; 40mA
0.4
dB
f=2GHz; V
DS
= 3.3V; I
DS
= 60mA
0.5
dB
Noise Figure
NF
f=2GHz; V
DS
= 3.3V; 110mA
0.7
dB
Output Third-Order Intercept Point
IP3
V
DS
= 3.3V; I
DS
= 110mA
33
dBm
Transconductance
G
M
V
DS
= 2 V; V
GS
= 0 V
170
220
mS
Gate-Source Leakage Current
I
GSO
V
GS
= -5 V
5
35
A
Pinch-Off Voltage
V
P
V
DS
= 2 V; I
DS
= 2 mA
-1.2
V
Gate-Source Breakdown
Voltage Magnitude
|V
BDGS
|
I
GS
= 2 mA
10
12
V
Gate-Drain Breakdown
Voltage Magnitude
|V
BDGD
|
I
GD
= 2 mA
10
13
V
PRELIMINARY DATA SHEET
FP750SOT343
P
ACKAGED
L
OW
N
OISE
,
M
EDIUM
P
OWER
PHEMT
Phone: (408) 988-1845
http:// www.filss.com
Revised: 2/01/02
Fax: (408) 970-9950
Email: sales@filss.com
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Test Conditions
Min
Max
Units
Drain-Source Voltage
V
DS
T
Ambient
= 22
3
C
5
V
Gate-Source Voltage
V
GS
T
Ambient
= 22
3
C
-3
V
Drain-Source Current
I
DS
T
Ambient
= 22
3
C
I
DSS
mA
Gate Current
I
G
T
Ambient
= 22
3
C
7.5
mA
RF Input Power
P
IN
T
Ambient
= 22
3
C
175
mW
Channel Operating Temperature
T
CH
T
Ambient
= 22
3
C
175
C
Storage Temperature
T
STG
--
-65
175
C
Total Power Dissipation
P
TOT
T
Ambient
= 22
3
C
1.0
W
Notes:
Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.
Power Dissipation defined as: P
TOT
(P
DC
+ P
IN
) P
OUT
, where
P
DC
: DC Bias Power
P
IN
: RF Input Power
P
OUT
: RF Output Power
Absolute Maximum Power Dissipation to be de-rated as follows above 25
C:
P
TOT
= 1.0W (0.007W/
C) x T
PACK
where T
PACK
= source tab lead temperature.
This PHEMT is susceptible to damage from Electrostatic Discharge. Proper precautions should be used when handling these
devices.
HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A (0-500 V). Further information on ESD control
measures can be found in MIL-STD-1686 and MIL-HDBK-263.
APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site.
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