FPD1050
0.75W
P
OWER P
HEMT
Phone: +1 408 850-5790
http:// www.filcs.com
Revised: 8/05/04
Fax: +1 408 850-5766
Email: sales@filcsi.com
FEATURES
28.5 dBm Linear Output Power at 12 GHz
11 dB Power Gain at 12 GHz
14 dB Maximum Stable Gain at 12 GHz
41 dBm Output IP3
45% Power-Added Efficiency
DESCRIPTION AND APPLICATIONS
The FPD1050 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT),
featuring a 0.25
m by 1050 m Schottky barrier gate, defined by high-resolution stepper-based
photolithography. The recessed and offset Gate structure minimizes parasitics to optimize
performance. The epitaxial structure and processing have been optimized for reliable high-power
applications. The FPD750 also features Si
3
N
4
passivation and is also available in a low cost plastic
SOT89 plastic package.
Typical applications include commercial and other narrowband and broadband high-performance
amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output
amplifiers, and medium-haul digital radio transmitters.
ELECTRICAL SPECIFICATIONS AT 22C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL
Power at 1dB Gain Compression
P
1dB
V
DS
= 8 V; I
DS
= 50% I
DSS
27.5
28.5 dBm
Maximum Stable Gain (S
21
/S
12
)
MSG
V
DS
= 8 V; I
DS
= 50% I
DSS
14.0
dB
Power Gain at P
1dB
G
1dB
V
DS
= 8 V; I
DS
= 50% I
DSS
10.0
11.0 dB
Power-Added Efficiency
PAE
V
DS
= 8 V; I
DS
= 50% I
DSS
;
P
OUT
= P
1dB
45 %
Output Third-Order Intercept Point
(from 15 to 5 dB below P
1dB
)
IP3 V
DS
= 10V; I
DS
= 50% I
DSS
Matched for optimal power
Tuned for best IP3
39
41
dBm
Saturated Drain-Source Current
I
DSS
V
DS
= 1.3 V; V
GS
= 0 V
250
315
375
mA
Maximum Drain-Source Current
I
MAX
V
DS
= 1.3 V; V
GS
+1 V
520 mA
Transconductance G
M
V
DS
= 1.3 V; V
GS
= 0 V
280
mS
Gate-Source Leakage Current
I
GSO
V
GS
= -5 V
15
A
Pinch-Off Voltage
|V
P
| V
DS
= 1.3 V; I
DS
= 1 mA
1.0
V
Gate-Source Breakdown Voltage
|V
BDGS
| I
GS
= 1 mA
16
18
V
Gate-Drain Breakdown Voltage
|V
BDGD
| I
GD
= 1 mA
16
18
V
Thermal Resistivity (see Notes)
JC
V
DS
>
6V
45
C/W
DRAIN
BOND
PAD (2X)
SOURCE
BOND
PAD (2x)
GATE
BOND
PAD (1X)
DIE SIZE: 470 x 440
m
DIE THICKNESS: 100
m
BONDING PADS: >85 x 60
m
FPD1050
0.75W
P
OWER P
HEMT
Phone: +1 408 850-5790
http:// www.filcs.com
Revised: 8/05/04
Fax: +1 408 850-5766
Email: sales@filcsi.com
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Test Conditions
Min
Max
Units
Drain-Source Voltage
V
DS
-3V < V
GS
< +0V
10
V
Gate-Source Voltage
V
GS
0V < V
DS
< +8V
-3
V
Drain-Source Current
I
DS
For V
DS
> 2V
I
DSS
mA
Gate Current
I
G
Forward or reverse current
10
mA
RF Input Power
P
IN
Under any acceptable bias state
175
mW
Channel Operating Temperature
T
CH
Under any acceptable bias state
175
C
Storage Temperature
T
STG
Non-Operating Storage
-40
150
C
Total Power Dissipation
P
TOT
See De-Rating Note below
3.4
W
Gain Compression
Comp.
Under any bias conditions
5
dB
Simultaneous Combination of Limits**
2 or more Max. Limits
80
%
*
T
Ambient
= 22
C unless otherwise noted
**Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.
Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.
Power Dissipation defined as: P
TOT
(P
DC
+ P
IN
) P
OUT
, where
P
DC
: DC Bias Power
P
IN
: RF Input Power
P
OUT
: RF Output Power
Absolute Maximum Power Dissipation to be de-rated as follows above 22C:
P
TOT
= 3.4W (0.022W/
C) x T
HS
where T
HS
= heatsink or ambient temperature above 22
C
Example: For a 85
C heatsink temperature: P
TOT
= 3.4W (0.022 x (85 22)) = 2.01W
HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
ASSEMBLY INSTRUCTIONS
The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage
temperature should be 280-290
C; maximum time at temperature is one minute. The recommended
wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm)
gold wire. Stage temperature should be 250-260
C.
APPLICATIONS NOTES & DESIGN DATA
Complete design data, including S-parameters, noise data, and large-signal models are available on
the Filtronic web site.
All information and specifications are subject to change without notice.
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