PRELIMINARY
FPD6836P70
H
I
-F
REQUENCY
P
ACKAGED P
HEMT
Phone: +1 408 850-5790
http://www.filtronic.co.uk/semis
Revised: 7/15/05
Fax: +1 408 850-5766
Email: sales@filcsi.com
PERFORMANCE
22 dBm Output Power (P
1dB
)
19 dB Power Gain (G
1dB
) at 1.85 GHz
0.5 dB Noise Figure at 1.85 GHz
32 dBm Output IP3
50% Power-Added Efficiency at 1.85 GHz
Useable Gain to 20 GHz
Evaluation Boards Available
GATE LEAD IS ANGLED
DESCRIPTION AND APPLICATIONS
The
FPD
6836P70 is a packaged
depletion mode
AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25
m x 360 m Schottky barrier
G
ate, defined by
high-resolution stepper-based
photolithography.
.
The
FPD
6836
is also available in die form .
Typical applications include gain blocks and medium power stages for applications to 22 GHz.
ELECTRICAL SPECIFICATIONS AT 22C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL (except as noted)
Power at 1dB Gain Compression
P
1dB
V
DS
= 5 V; I
DS
= 50% I
DSS
22 dBm
Gain at 1dB Gain Compression
SSG
V
DS
= 5 V; I
DS
= 50% I
DSS
19 dB
Power-Added Efficiency
PAE
V
DS
= 5 V; I
DS
= 50% I
DSS
;
P
OUT
= P
1dB
45 %
Maximum Stable Gain (S
21
/S
12
)
f = 12 GHz
f = 18 GHz
MSG V
DS
= 5 V; I
DS
= 50% I
DSS
13
11
Noise Figure
NF
V
DS
= 5 V; I
DS
= 25% I
DSS
0.5 dB
Output Third-Order Intercept Point
P
OUT
= 11 dBm SCL
IP3 V
DS
= 5V; I
DS
= 50% I
DSS
32 dBm
Saturated Drain-Source Current
I
DSS
V
DS
= 1.3 V; V
GS
= 0 V
85
105
125
mA
Maximum Drain-Source Current
I
MAX
V
DS
= 1.3 V; V
GS
+1 V
215 mA
Transconductance G
M
V
DS
= 1.3 V; V
GS
= 0 V
140
mS
Gate-Source Leakage Current
I
GSO
V
GS
= -5 V
1
10
A
Pinch-Off Voltage
|V
P
| V
DS
= 1.3 V; I
DS
= 0.2 mA
0.7
0.9
1.3
V
Gate-Source Breakdown Voltage
|V
BDGS
| I
GS
= 0.2 mA
12
14
V
Gate-Drain Breakdown Voltage
|V
BDGD
| I
GD
= 0.2 mA
14.5
16
V
Thermal Resistivity (see Notes)
JC
V
DS
> 3V
275
C/W
PRELIMINARY
FPD6836P70
H
I
-F
REQUENCY
P
ACKAGED P
HEMT
Phone: +1 408 850-5790
http://www.filtronic.co.uk/semis
Revised: 7/15/05
Fax: +1 408 850-5766
Email: sales@filcsi.com
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Symbol
Test Conditions
Min
Max
Units
Drain-Source Voltage
V
DS
-3V < V
GS
< +0V
8
V
Gate-Source Voltage
V
GS
0V < V
DS
< +8V
-3
V
Drain-Source Current
I
DS
For V
DS
> 2V
I
DSS
mA
Gate Current
I
G
Forward or reverse current
15
mA
RF Input Power
2
P
IN
Under any acceptable bias state
170
mW
Channel Operating Temperature
T
CH
Under any acceptable bias state
175
C
Storage Temperature
T
STG
Non-Operating Storage
-40
150
C
Total Power Dissipation
P
TOT
See De-Rating Note below
550
mW
Gain Compression
Comp.
Under any bias conditions
5
dB
Simultaneous Combination of Limits
3
2 or more Max. Limits
80
%
1
T
Ambient
= 22
C unless otherwise noted
2
Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3
Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
Total Power Dissipation defined as: P
TOT
(P
DC
+ P
IN
) P
OUT
, where:
P
DC
: DC Bias Power
P
IN
: RF Input Power
P
OUT
: RF Output Power
Total Power Dissipation to be de-rated as follows above 22C:
P
TOT
= 550mW (3.6mW/
C) x T
PACK
where T
PACK
= source tab lead temperature above 22
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65
C source lead temperature: P
TOT
= 550mW (3.6 x (65 22)) = 323mW
HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 0 (< 250V) per JESD22-A114-B, Human Body
Model, and Class A (< 200V) per JESD22-A115-A, Machine Model.
APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
PRELIMINARY
FPD6836P70
H
I
-F
REQUENCY
P
ACKAGED P
HEMT
Phone: +1 408 850-5790
http://www.filtronic.co.uk/semis
Revised: 7/15/05
Fax: +1 408 850-5766
Email: sales@filcsi.com
(DIMENSIONS IN mm)
BIASING GUIDELINES
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD6836P70.
For standard Class A operation, a 50% of I
DSS
bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at
50% of I
DSS
. To achieve a larger separation between P
1dB
and IP3, an operating point in the 25%
to 33% of I
DSS
range is suggested. Such Class AB operation will not degrade the IP3
performance.
PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT
All information and specifications subject to change without notice.
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