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Электронный компонент: 68HC05JB4

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Motorola, Inc., 1999
HC05JB4GRS/H
REV 2
68HC05JB4
68HC705JB4
SPECIFICATION
(General Release)
February 24, 1999
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
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.
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
MOTOROLA
REV 2
i
TABLE OF CONTENTS
Section
Page
SECTION 1
GENERAL DESCRIPTION
1.1
FEATURES ...................................................................................................... 1-1
1.2
MASK OPTIONS.............................................................................................. 1-2
1.3
MCU STRUCTURE.......................................................................................... 1-2
1.4
FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4
1.4.1
V
DD
AND V
SS
.............................................................................................. 1-4
1.4.2
OSC1, OSC2 ............................................................................................... 1-4
1.4.3
RESET......................................................................................................... 1-6
1.4.4
IRQ (MASKABLE INTERRUPT REQUEST)................................................ 1-6
1.4.5
V3.3 ............................................................................................................. 1-6
1.4.6
D+ and D ................................................................................................... 1-6
1.4.7
PA0-PA7 ...................................................................................................... 1-6
1.4.8
PB0-PB4 ...................................................................................................... 1-7
1.4.9
PC0-PC5...................................................................................................... 1-7
SECTION 2
MEMORY
2.1
I/O AND CONTROL REGISTERS ................................................................... 2-2
2.2
RAM ................................................................................................................. 2-2
2.3
ROM................................................................................................................. 2-2
2.4
I/O REGISTERS SUMMARY ........................................................................... 2-3
SECTION 3
CENTRAL PROCESSING UNIT
3.1
REGISTERS .................................................................................................... 3-1
3.2
ACCUMULATOR (A)........................................................................................ 3-2
3.3
INDEX REGISTER (X) ..................................................................................... 3-2
3.4
STACK POINTER (SP) .................................................................................... 3-2
3.5
PROGRAM COUNTER (PC) ........................................................................... 3-2
3.6
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
3.6.1
Half Carry Bit (H-Bit) .................................................................................... 3-3
3.6.2
Interrupt Mask (I-Bit) .................................................................................... 3-3
3.6.3
Negative Bit (N-Bit) ...................................................................................... 3-3
3.6.4
Zero Bit (Z-Bit) ............................................................................................. 3-3
3.6.5
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
SECTION 4
INTERRUPTS
4.1
INTERRUPT VECTORS .................................................................................. 4-1
4.2
INTERRUPT PROCESSING............................................................................ 4-2
4.3
RESET INTERRUPT SEQUENCE .................................................................. 4-4
4.4
SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
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.
GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
MC68HC05JB4
ii
REV
2
TABLE OF CONTENTS
Section
Page
4.5
HARDWARE INTERRUPTS ............................................................................ 4-4
4.5.1
External Interrupt IRQ.................................................................................. 4-4
4.5.2
External Interrupt IRQ2................................................................................ 4-5
4.5.3
IRQ Control/Status Register (ICSR) - $0A................................................... 4-6
4.5.4
Port A External Interrupts (PA0-PA3, by mask option) ................................ 4-7
4.5.5
Timer1 Interrupt (TIMER1)........................................................................... 4-8
4.5.6
USB Interrupt (USB) .................................................................................... 4-8
4.5.7
MFT Interrupt (MFT) .................................................................................... 4-8
SECTION 5
RESETS
5.1
POWER-ON RESET ........................................................................................ 5-2
5.2
EXTERNAL RESET ......................................................................................... 5-2
5.3
INTERNAL RESETS ........................................................................................ 5-2
5.3.1
Power-On Reset (POR) ............................................................................... 5-2
5.3.2
USB Reset ................................................................................................... 5-3
5.3.3
Computer Operating Properly (COP) Reset ................................................ 5-3
5.3.4
Low Voltage Reset (LVR) ............................................................................ 5-3
5.3.5
Illegal Address Reset................................................................................... 5-4
SECTION 6
LOW POWER MODES
6.1
STOP MODE.................................................................................................... 6-3
6.2
WAIT MODE .................................................................................................... 6-3
6.3
DATA-RETENTION MODE.............................................................................. 6-3
SECTION 7
INPUT/OUTPUT PORTS
7.1
SLOW FALLING-EDGE OUTPUT DRIVER..................................................... 7-1
7.2
PORT-A............................................................................................................ 7-2
7.2.1
Port-A Data Register.................................................................................... 7-2
7.2.2
Port-A Data Direction Register .................................................................... 7-3
7.2.3
Port-A Pull-up Control Register ................................................................... 7-3
7.3
PORT-B............................................................................................................ 7-3
7.3.1
Port-B Data Register.................................................................................... 7-4
7.3.2
Port-B Data Direction Register .................................................................... 7-4
7.3.3
Port-B Pull-up Control Register ................................................................... 7-4
7.4
PORT-C ........................................................................................................... 7-4
7.4.1
Port-C Data Register ................................................................................... 7-5
7.4.2
Port-C Data Direction Register .................................................................... 7-5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
.
.
February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
MOTOROLA
REV 2
iii
TABLE OF CONTENTS
Section
Page
SECTION 8
MULTI-FUNCTION TIMER
8.1
OVERVIEW...................................................................................................... 8-2
8.2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2
8.3
MFT REGISTERS ............................................................................................ 8-3
8.3.1
Timer Counter Register (TCNT) $09 ........................................................... 8-3
8.3.2
Timer Control/Status Register (TCSR) $08 ................................................. 8-3
8.4
OPERATION DURING STOP MODE .............................................................. 8-4
8.5
COP CONSIDERATION DURING STOP MODE............................................. 8-4
SECTION 9
16-BIT TIMER
9.1
TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4
9.3
INPUT CAPTURE REGISTERS ...................................................................... 9-5
9.4
OUTPUT COMPARE REGISTERS ................................................................. 9-6
9.5
TIMER CONTROL REGISTER (TCR) ............................................................. 9-8
9.6
TIMER STATUS REGISTER (TSR)................................................................. 9-9
9.7
TIMER OPERATION DURING WAIT MODE................................................. 9-10
9.8
TIMER OPERATION DURING STOP MODE ................................................ 9-10
SECTION 10
UNIVERSAL SERIAL BUS MODULE
10.1
FEATURES .................................................................................................... 10-1
10.2
OVERVIEW.................................................................................................... 10-2
10.2.1
USB Protocol ............................................................................................. 10-2
10.2.2
Reset Signaling.......................................................................................... 10-8
10.2.3
Suspend..................................................................................................... 10-9
10.2.4
Resume After Suspend.............................................................................. 10-9
10.2.5
Low Speed Device................................................................................... 10-10
10.3
CLOCK REQUIREMENTS........................................................................... 10-10
10.4
HARDWARE DESCRIPTION....................................................................... 10-10
10.4.1
Voltage Regulator .................................................................................... 10-11
10.4.2
USB Transceiver...................................................................................... 10-11
10.4.3
Receiver Characteristics.......................................................................... 10-12
10.4.4
USB Control Logic ................................................................................... 10-14
10.5
I/O REGISTER DESCRIPTION ................................................................... 10-17
10.5.1
USB Address Register (UADDR)............................................................. 10-18
10.5.2
USB Interrupt Register 0 (UIR0) .............................................................. 10-19
10.5.3
USB Interrupt Register 1 (UIR1) .............................................................. 10-20
10.5.4
USB Control Register 0 (UCR0) .............................................................. 10-21
10.5.5
USB Control Register 1 (UCR1) .............................................................. 10-22
10.5.6
USB Control Register 2 (UCR2) .............................................................. 10-23
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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