Freescale Semiconductor
Product Brief

9S12XDFAMPP

Rev. 2.14, 7-Nov-2005

MC9S12

D Family

16-bit Microprocessor Family (covers MC9S12

D64 through

MC9S12

DP512 and MC3S12

DT256/MC3S12

DG128)

Introduction

Targeted at automotive multiplexing applications, the MC9S12

D Family will deliver 32-bit performance

with all the advantages and efficiencies of a 16-bit MCU. The S12

is designed to retain the low cost, low

power consumption, excellent EMC performance and code-size efficiency advantages enjoyed by users
of Freescale's previous 16-bit MC9S12 MCU family.

Based around an enhanced S12 core, the MC9S12

D Family will deliver two to five times the

performance of a 25 MHz S12 whilst retaining a high degree of pin and code compatibility with the original
S12D - family.

The MC9S12

D Family features the performance boosting XGATE co-processor. The XGATE, which is

programmable in "C" language, has an instruction set which is optimized for data movement, logic and
bit manipulation instructions. It runs at twice the bus frequency of the S12

and off-loads the CPU by

providing high speed data transfer (and data processing) between any peripheral module, RAM and I/O
ports. This is particularly useful in applications such as automotive gateways where there are multiple
busses carrying heavy data traffic which would otherwise exert a heavy interrupt/processing load on the
CPU.

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Features

The MC9S12

D Family will feature an enhanced MSCAN module which, when used in conjunction with

XGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retains
backwards compatibility with the MSCAN module featured on previous S12 products.

Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotive
spec SG-Flash with additional integrated EEPROM.

In addition to the rich S12 peripheral set, the MC9S12

D Family will feature more RAM, extra A/D

channels, new timer features and additional LIN-compatible SCI ports compared with the original S12 D-
Family. The MC9S12

D Family also features a new flexible interrupt handler which allows multilevel

nested interrupts.

The MC9S12

D Family has full 16-bit data paths throughout. The non-multiplexed expanded bus

interface available on the 144-pin versions allows an easy interface to external memories. The inclusion
of a PLL circuit allows power consumption and performance to be adjusted to suit operational
requirements. System power consumption is further improved with the new

fast exit from STOP mode

feature and an ultra low power wakeup timer.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt
capability allowing wakeup from STOP or WAIT mode.

The MC9S12

D Family will be available in 144-pin LQFP (with optional external bus), 112-pin, and 80-pin

options.

Upward compatible with MC9S12 instruction set

Enhanced indexed addressing

Additional (superset) instructions to improve 32-bit calculations and
semaphore handling

Access large data segments independent of PPAGE

Eight levels of nested interrupt

Flexible assignment of interrupt sources to each interrupt level.

One non-maskable high priority interrupt (XIRQ)

Wakeup interrupt inputs

IRQ and non-maskable XIRQ

Features

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Programmable, high performance I/O co-processor module

up to

80 MIPS RISC performance

Transfers data to or from all peripherals and RAM without CPU
intervention or CPU wait states

Performs logical, shifts, arithmetic, and bit operations on data

Enables FullCAN capability when used in conjunction with MSCAN
module

Full LIN master or slave capability when used in conjunction with the
six integrated LIN SCI modules

Can interrupt the HCS12X CPU signalling transfer completion

Triggers from any hardware module as well as from the CPU possible

64K, 128K, 256K, 384K and 512K byte Flash

128K and 256K ROM

Flash General Features

Erase sector size 1024 bytes

Automated program and erase algorithm

Fast sector erase and word program operation

2-stage command pipeline for faster multi-word program times

Sector erase abort feature for critical interrupt response

Protection scheme to prevent accidental program or erase

Security option to prevent unauthorized access

Code integrity check using built-in data compression

Sense-amp margin level setting for reads

1K, 2K, 4K byte EEPROM

Small erase sector (4 bytes)

Automated program and erase algorithm

Fast sector erase and word program operation

2-stage command pipeline for faster multi-word program times

Sector erase abort feature for critical interrupt response

Protection scheme to prevent accidental program or erase

4K, 8K, 12K, 14K, 16K, 20K, 32K Byte RAM

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Features

Loop control Pierce oscillator using a 0.5 MHz to 16 MHz crystal

Option for full-swing Pierce without internal feedback resistor using a
0.5 MHz to 40 MHz crystal

Current gain control on amplitude output

Signal with low harmonic distortion

Low power

Good noise immunity

Eliminates need for external current limiting resistor

Transconductance sized for optimum start-up margin for typical
crystals

Clock monitor

Phase-locked-loop clock frequency multiplier

Reference divider

Automatic bandwidth control mode for low-jitter operation

Automatic frequency lock detector

Fast wakeup from STOP in self clock mode for power saving and
immediate program execution

Computer operating properly (COP) watchdog with optional safety
window to initialize timeout counter

Real time interrupt for task scheduling purposes or cyclic wakeup
from low power modes

System reset generation

16 bit data

Support for external WAIT input or internal wait cycles to adapt MCU
speed to peripheral speed requirements

Up to four chip select outputs to select 16K, 1M, 2M and 4M byte
address spaces

Supports glue-less interface to popular asynchronous RAMs and
Flash devices

External address space 4M byte for data and program space

Features

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Up to two independent ADC converters (see

Table 2

)

8-bit or 10-bit resolution

Multiplexer for 16 analog input channels

7 s, 10-bit single conversion time

Programmable sample time

Left/right, signed/unsigned result data

Continuous conversion mode

Multiple channel scans

External and internal conversion trigger capability

Pins can also be used as digital I/O

Eight 16-bit channels for input capture or output compare

One 16-bit free-running counter with 8-bit precision prescaler

One 16-bit modulus down counter with 8-bit precision prescaler

Four 8-bit or two 16-bit pulse accumulators

Four channels have enhanced input capture capabilities:

Delay counter for noise immunity

16-bit capture buffer

8-bit pulse accumulator buffer

Four channel x 24-bit modulus down-count timers

Timeout interrupt

Timeout peripheral trigger

Start of timers can be aligned

Eight channel x 8-bit or four channel x 16-bit pulse width modulator

Programmable period and duty cycle per channel

Center-aligned or left-aligned outputs

Programmable clock select logic with a wide range of frequencies

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Features

Up to five MSCAN modules (see

Table 2

)

CAN 2.0 A, B software compatible

Standard and extended data frames

8 bytes data length

Programmable bit rate up to 1 Mbps

Five receive buffers with FIFO storage scheme

Three transmit buffers with internal prioritization

Flexible identifier acceptance filter programmable as:

2 x 32-bit

4 x 16-bit

8 x 8-bit

Wakeup with integrated low-pass filter option

Loop back for self test

Listen-only mode to monitor CAN bus

Bus-off recovery by software intervention or automatically

16-bit time stamp of transmitted/received messages

FullCAN capability when used in conjunction with XGATE

Up to three SPI modules (see

Table 2

)

Full-duplex or single-wire bidirectional

Double-buffered transmit and receive

Master or slave mode

MSB-first or LSB-first shifting

Serial clock phase and polarity options

Up to six SCI modules (see

Table 2

)

Full-duplex or single wire operation

Standard mark/space non-return-to-zero (NRZ) format

Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with
programmable pulse widths

13-bit baud rate selection

Programmable character length

Programmable polarity for transmitter and receiver

Receive wakeup on active edge

Break detect and transmit collision detect supporting LIN

Features

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Up to two IIC modules (see

Table 2

)

Compatible with I2C Bus standard

Multi-master operation

Software programmable for one of 256 different serial clock
frequencies

Software selectable acknowledge bit

Interrupt driven byte-by-byte data transfer

Arbitration lost interrupt with automatic mode switching from master
to slave

Calling address identification interrupt

Start and stop signal generation/detection

Repeated start signal generation

Acknowledge bit generation/detection

Bus busy detection

supports 400 Kbps

Background debug controller (BDM) with single-wire interface

Non-intrusive memory access commands

Supports in-circuit programming of on-chip non-volatile memory

Supports security

Four comparators A, B, C and D

Each can monitor CPU or XGATE busses

A and C compares 23-bit address bus and 16-bit data bus with
mask register

B and D compares 23-bit address bus only

Three modes: simple address/data match, inside address range
or outside address range

64 x 64-bit circular trace buffer to capture change-of-flow addresses
or address and data of every access

Tag-type or force-type hardware breakpoint requests

Power-on reset (POR)

illegal address detection with reset

Low-voltage detection with interrupt or reset

up to 117 general-purpose input/output (I/O) pins depending on the
package option and 2 input-only pins

Hysteresis and configurable pullup/pulldown device on all input pins

Configurable drive strength on all output pins

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

MC9S12XD Family Block Diagram

512K/384K/256k/128K/64K Byte Flash

32K/20K/16K/14K/12K/8K/4K Byte RAM

Enhanced Capture

RESET

EXTAL

XTAL

SCI0

4K/2K/1K Byte EEPROM

BKGD

R/W/WE

MODB/TAGHI

XIRQ

ECLKX2/XCLKS

VDDR

CPU12X

Periodic Interrupt

COP Watchdog

Clock Monitor

Single-wire Background

Breakpoints

PLL

VSSPLL

XFC

VDDPLL

VDDA

VSSA

VRH

VRL

ATD0

IRQ

LSTRB/LDS/EROMCTL
ECLK
MODA/RE/TAGLO

PA4
PA3
PA2
PA1
PA0

PA7
PA6
PA5

TEST

ADDR12
ADDR11
ADDR10
ADDR9
ADDR8

ADDR15
ADDR14

ADDR13

PB4
PB3
PB2
PB1
PB0

PB7
PB6
PB5

ADDR4
ADDR3
ADDR2
ADDR1

ADDR7
ADDR6
ADDR5

PE3
PE4
PE5
PE6
PE7

PE0
PE1
PE2

AN2

AN6

AN0

AN7

AN1

AN3
AN4
AN5

PAD03
PAD04
PAD05
PAD06
PAD07

PAD00
PAD01
PAD02

IOC2

IOC6

IOC0

IOC7

IOC1

IOC3
IOC4
IOC5

PT3
PT4
PT5
PT6
PT7

PT0
PT1
PT2

RXD

TXD

MISO
MOSI

PS3
PS4
PS5

PS0
PS1
PS2

SCI1

RXD

TXD

PP3
PP4
PP5
PP6
PP7

PP0
PP1
PP2

SCK

PS6
PS7

SPI0

IIC0

SDA

SCL

PJ2 CS1
PJ4 CS0

CAN0

RXCAN

TXCAN

PM1

PM0

CAN1

RXCAN

TXCAN

PM2
PM3

CAN2

RXCAN

TXCAN

PM4
PM5
PM6
PM7

KWH2

KWH6

KWH0

KWH7

KWH1

KWH3

KWH4
KWH5

PH3
PH4
PH5
PH6
PH7

PH0
PH1
PH2

KWJ0
KWJ1

PJ0 CS3
PJ1

Clock and

Reset

Generation

Module

Voltage Regulator

VSSR

Debug Module

VDD1,2

VSS1,2

VREGEN

VDDR1,2

VSSR1,2

Voltage Regulator 3-5V

CAN4

RXCAN

TXCAN

MISO
MOSI

SCK

SPI2

MISO
MOSI

SCK

SPI1

KWP2

KWP6

KWP0

KWP7

KWP1

KWP3
KWP4
KWP5

KWJ2
KWJ4

Timer

o
d

u
l
e

t
o

P

o
r
t

R

o
u

t
i
n

PWM2

PWM6

PWM0

PWM7

PWM1

PWM3
PWM4
PWM5

PWM

8 Bit PPAGE

IQSTAT2

IQSTAT0
IQSTAT1

ACC2

PK3

PK6

PK0
PK1

ADDR19

EWAIT

ADDR16
ADDR17
ADDR18

PK2

ACC1

PK4
PK5

ADDR20
ADDR21

ROMCTL/EWAIT

PK7

ADDR22

VRH
VRL

VDDA

VSSA

VRH

VRL

ATD1

AN10

AN14

AN8

AN15

AN9

AN11
AN12
AN13

PAD11
PAD12
PAD13
PAD14
PAD15

PAD08
PAD09
PAD10

VDDA
VSSA

AN18

AN22

AN16

AN23

AN17

AN19
AN20
AN21

PAD19
PAD20
PAD21
PAD22
PAD23

PAD16
PAD17
PAD18

PC4
PC3
PC2
PC1
PC0

PC7
PC6
PC5

DATA12
DATA11
DATA10
DATA9
DATA8

DATA15
DATA14

DATA13

PD4
PD3
PD2
PD1
PD0

PD7
PD6
PD5

DATA4
DATA3
DATA2
DATA1
DATA0

DATA7
DATA6
DATA5

SCI2

RXD

TXD

PJ6
PJ7

PJ5 CS2

KWJ5
KWJ6
KWJ7

o
n
-
M

u
l
t
i
p
l
e

x
e

d

E

x
t
e

r
n
a

l

B

s

I
n
t
e
r
f
a

c
e

(
E

I
)

VDDX1,2

VSSX1,2

I/O Supply 3-5V

VDDA

VSSA

Analog Supply 3-5V

VDDPLL

VSSPLL

PLL Supply 2.5V

Enhanced Multilevel

Interrupt Module

XGATE

Peripheral Co-Processor

VDD1,2

VSS1,2

Digital Supply 2.5V

Allows 4MByte

Program space

SCI3

RXD

TXD

SCI4

RXD

TXD

SCI5

RXD

TXD

IIC1

SDA

SCL

Timer

4 channel

16 bit with Prescaler

for internal timebases

CAN3

RXCAN

TXCAN

ADDR0

UDS

IQSTAT3
ACC0

MC9S12XD Family Block Diagram

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Table 1. Package and Memory Options of MC9S12

D Family Members

Device

Package

Flash

RAM

EEPROM

ROM

9S12XDP512

144 LQFP

512K

32K

112 LQFP

9S12XDT512

144 LQFP

20K

112 LQFP

80 QFP

9S12XDT384

144 LQFP

384K

20K

112 LQFP

80 QFP

9S12XDQ256

144 LQFP

256K

16K

112 LQFP

80 QFP

9S12XDT256

144 LQFP

112 LQFP

80 QFP

9S12XD256

144 LQFP

14K

112 LQFP

80 QFP

3S12XDT256

144 LQFP

16K

(1)

NOTES:

1. No EEPROM is available on ROM versions.

256K

112 LQFP

80 QFP

9S12XDG128

112 LQFP

128K

12K

80 QFP

3S12XDG128

112 LQFP

(1)

128K

80 QFP

9S12XD128

112 LQFP

128K

80 QFP

9S12XD64

80 QFP

64K

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

MC9S12XD Family Block Diagram

Table 2. Peripheral Options of MC9S12

D Family Members

Device

Package

XGATE

CAN

SCI

SPI

IIC

ECT

PIT

A/D

I/O

9S12XDP512

144LQFP

yes

2/24

119

112LQFP

2/16

9S12XDT512

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

9S12XDT384

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

9S12XDQ256

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

9S12XDT256

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

9S12XD256

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

3S12XDT256

144LQFP

2/24

119

112LQFP

2/16

80QFP

1/8

9S12XDG128

112LQFP

yes

(1)

1/16

(2)

80QFP

1/8

3S12XDG128

112LQFP

1/16

(2)

80QFP

1/8

9S12XD128

112LQFP

1/16

(2)

80QFP

1/8

9S12XD64

80QFP

1/8

NOTES:

1. Can execute code only from RAM

2. ATD1 routed to PAD00-15 instead of PAD08-23.

MC9S12XD Family Block Diagram

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Pinout explanations:

A/D is the number of modules/total number of A/D channels.

I/O is the sum of ports capable to act as digital input or output.

144 Pin Packages:
Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only,
H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 24
25 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ)

112 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16
22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ)

80 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8
11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)

CAN0 can be routed under software control from PM[1:0] to pins PM[3:2] or PM[5:4] or PJ[7:6].

CAN4 pins are shared between IIC0 pins.

CAN4 can be routed under software control from PJ[7:6] to pins PM[5:4] or PM[7:6].

Versions with 5 CAN modules will have CAN0, CAN1, CAN2, CAN3 and CAN4

Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4

Versions with 3 CAN modules will have CAN0, CAN1 and CAN4.

Versions with 2 CAN modules will have CAN0 and CAN4.

Versions with 1 CAN modules will have CAN0

Versions with 2 SPI modules will have SPI0 and SPI1.

Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4.

Versions with 2 SCI modules will have SCI0 and SCI1.

Versions with 1 IIC module will have IIC0.

SPI0 can be routed to either Ports PS[7:4] or PM[5:2].

SPI1 pins are shared with PWM[3:0]; In 144 and 112-pin versions, SPI1 can be routed under
software control to PH[3:0].

SPI2 pins are shared with PWM[7:4]; In 144 and 112-pin versions, SPI2 can be routed under
software control to PH[7:4]. In 80-pin packages, SS-signal of SPI2 is not bonded out!

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Pin Assignments

Table 3. Port and Peripheral Availability by Package Option

Port

144 LQFP

112 LQFP

80 QFP

Port AD/ADC Channels

24/24

16/16

8/8

Port A pins

Port B pins

Port C pins

Port D pins

Port E pins incl. IRQ/XIRQ input only

Port H pins

Port J pins

Port K pins

Port M pins

Port P pins

Port S pins

Port T pins

Sum of Ports

119

VDDX/VSSX

4/4

3/3

2/2

Table 4. Peripheral

Port Cross Reference

(1)

I
0

I
1

I
2

I
3

I
4

I
5

I
0

I
1

I
2

I
I
C

PJ1:0

PJ3:2

PJ5:4

PJ7:6

PM1:0

PM3:2

PM5:4

PM7:6

PS1:0

PS3:2

PS7:4

PH3:0

Pin Assignments

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

PH5:4

PH7:6

PP3:0

PP7:4

NOTES:

1. X denotes the reset condition and O denotes a possible rerouting under software control

Table 5. Pin-Out Summary

(1)

LQFP

144

LQFP

112

QFP

Pin

2nd

Function

3rd

Function

4th

Function

5th

Function

PP3

KWP3

PWM3

SS1

PP2

KWP2

PWM2

SCK1

PP1

KWP1

PWM1

MOSI1

PP0

KWP0

PWM0

MISO1

PJ2

KWJ2

CS1

PK6

ADDR22

NOACC

PK3

ADDR19

PK2

ADDR18

IQSTAT2

PK1

ADDR17

IQSTAT1

PK0

ADDR16

IQSTAT0

PT0

IOC0

PT1

IOC1

PT2

IOC2

PT3

IOC3

VDD1

VSS1

PT4

IOC4

PT5

IOC5

PT6

IOC6

PT7

IOC7

PK5

ADDR21

PK4

ADDR20

PJ1

KWJ1

TXD2

PJ0

KWJ0

RXD2

Table 4. Peripheral

Port Cross Reference

(1)

I
0

I
1

I
2

I
3

I
4

I
5

I
0

I
1

I
2

I
I
C

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Pin Assignments

BKGD

MODC

VDDX2

VSSX2

PC0

DATA8

PC1

DATA9

PC2

DATA10

PC3

DATA11

PB0

ADDR0

UDS

PB1

ADDR1

PB2

ADDR2

PB3

ADDR3

PB4

ADDR4

PB5

ADDR5

PB6

ADDR6

PB7

ADDR7

PC4

DATA12

PC5

DATA13

PC6

DATA14

PC7

DATA15

PH7

KWH7

SS2

TXD5

PH6

KWH6

SCK2

RXD5

PH5

KWH5

MOSI2

TXD4

PH4

KWH4

MISO2

RXD4

PE7

XCLKS

ECLKX2

PE6

MODB

TAGHI

PE5

MODA

TAGLO

PE4

ECLK

VSSR

VDDR

RESET

VDDPLL

XFC

VSSPLL

EXTAL

XTAL

TEST

PH3

KWH3

SS1

TXD7

Table 5. Pin-Out Summary

(1)

LQFP

144

LQFP

112

QFP

Pin

2nd

Function

3rd

Function

4th

Function

5th

Function

Pin Assignments

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

PH2

KWH2

SCK1

RXD7

PH1

KWH1

MOSI1

TXD6

PH0

KWH0

MISO1

RXD6

PD0

DATA0

PD1

DATA1

PD2

DATA2

PD3

DATA3

PE3

LSTRB

LDS

EROMCTL

PE2

PE1

IRQ

PE0

XIRQ

PA0

ADDR8

PA1

ADDR9

PA2

ADDR10

PA3

ADDR11

PA4

ADDR12

PA5

ADDR13

PA6

ADDR14

PA7

ADDR15

VDDX3

PD4

DATA4

PD5

DATA5

PD6

DATA6

PD7

DATA7

VDD2

VSS2

PAD00

AN0

PAD08

AN8

PAD01

AN1

PAD09

AN9

PAD02

AN2

PAD10

AN8

PAD03

AN3

PAD11

AN11

PAD04

AN4

PAD12

AN12

Table 5. Pin-Out Summary

(1)

LQFP

144

LQFP

112

QFP

Pin

2nd

Function

3rd

Function

4th

Function

5th

Function

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Pin Assignments

PAD05

AN5

100

PAD13

AN13

101

PAD06

AN6

102

PAD14

AN14

103

PAD07

AN7

104

PAD15

AN15

105

PAD16

AN16

106

PAD17

AN17

107

VDDA

108

VRH

109

VRL

110

VSSA

111

PAD18

AN18

112

PAD19

AN19

113

PAD20

AN20

114

PAD21

AN21

115

PAD22

AN22

116

PAD23

AN23

117

PM7

TXCAN3

TXCAN4

TXD3

118

PM6

RXCAN3

RXCAN4

RXD3

119

PS0

RXD0

120

PS1

TXD0

121

PS2

RXD1

122

PS3

TXD1

123

PS4

MISO0

124

PS5

MOSI0

125

PS6

SCK0

126

PS7

SS0

127

VREGEN

128

PJ7

KWJ7

TXCAN4

SCL0

129

PJ6

KWJ6

RXCAN4

SDA0

130

PJ5

KWJ5

SCL1

CS2

131

PJ4

KWJ4

SDA1

CS0

132

100

PM5

TXCAN2

TXCAN0

TXCAN4

SCK0

133

101

PM4

RXCAN2

RXCAN0

RXCAN4

MOSI0

134

102

PM3

TXCAN1

TXCAN0

SS0

135

103

PM2

RXCAN1

RXCAN0

MISO0

Table 5. Pin-Out Summary

(1)

LQFP

144

LQFP

112

QFP

Pin

2nd

Function

3rd

Function

4th

Function

5th

Function

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Pin Assignments

Figure 1. MC9S12

D Family Pin Assignments for 144-pin LQFP Package

MC9S12

D Family

144 LQFP

Pins shown in BOLD are not available on the 80 QFP package

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3
7

3
8

3
9

4
0

4
1

4
2

4
3

4
4

4
5

4
6

4
7

4
8

4
9

5
0

5
1

5
2

5
3

5
4

5
5

5
6

5
7

5
8

5
9

6
0

6
1

6
2

6
3

6
4

6
5

6
6

6
7

6
8

6
9

7
0

7
1

7
2

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

1
4
4

1
4
3

1
4
2

1
4
1

1
4
0

1
3
9

1
3
8

1
3
7

1
3
6

1
3
5

1
3
4

1
3
3

1
3
2

1
3
1

1
3
0

1
2
9

1
2
8

1
2
7

1
2
6

1
2
5

1
2
4

1
2
3

1
2
2

1
2
1

1
2
0

1
1
9

1
1
8

1
1
7

1
1
6

1
1
5

1
1
4

1
1
3

1
1
2

1
1
1

1
1
0

1
0
9

Pins shown in BOLD-ITALICS are bit available on the 112 LQFP

nor on the 80 QFP Package Option

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Memory Maps

Figure 5. MC9S12XD-Family Flash Configuration

1, 2, 3, 4, 5

1. XGATE read access to Flash not possible on DG128/D128 and D64
2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF
3. Program Pages available on DQ256/D256 are $E0 - $E7 and $F8 - $FF
4. Shared XGATE/CPU area on DP512/DT512/DT384 at global address $78_0800 to $78_FFFF (30Kbyte)
5. Shared XGATE/CPU area on DQ256/D256 at global address $78_0800 to $79_3FFF (46Kbyte)

Shared XGATE/CPU area

Not implemented

$78_0000 (PPAGE $E0)

Global Address

$7A_0000 (PPAGE $E8)

$7C_0000 (PPAGE $F0)

$7E_0000 (PPAGE $F8)

128K

64K

128K

DP512/

DT512

DT384

DQ256/

D256

DG128/

D128

D64

Mechanical Package Dimensions

MC9S12XD Family, Rev. 2.14

Freescale Semiconductor

Mechanical Package Dimensions

Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03)

0.20 T L-M

144

GAGE PLANE

109

SEATING

108

PLANE

4X 36 TIPS

PIN 1

IDENT

VIEW Y

B1 V1

A
S

0.1

VIEW AB

140X

VIEW Y

PLATING

BASE

METAL

SECTION J1-J1

(ROTATED 90 )

144 PL

0.08

T L-M

DIM

MIN

MAX

20.00 BSC

MILLIMETERS

10.00 BSC

20.00 BSC

10.00 BSC

1.40

1.60

0.05

0.15

1.35

1.45

0.17

0.27

0.45

0.75

0.17

0.23

0.50 BSC

0.09

0.20

0.50 REF

0.25 BSC

0.13

0.20

0.13

0.20

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

0.09

0.16

1
2

NOTES:

DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

DIMENSIONS IN MILLIMETERS.

DATUMS L, M, N TO BE DETERMINED AT THE

SEATING PLANE, DATUM T.

DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE, DATUM T.

DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B DO INCLUDE MOLD MISMATCH

AND ARE DETERMINED AT DATUM PLANE H.

DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE D

DIMENSION TO EXCEED 0.35.

0.05

(Z)

(Y)

(K)

0.25

VIEW AB

0.20 T L-M

144X

9S12XDFAMPP
Rev. 2.14, 7-Nov-2005

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