Document Outline

• Revision History
• Chapter 1 General Description
  • 1.1 Introduction
  • 1.2 Features
  • 1.3 MCU Block Diagram
  • 1.4 Pin Assignments
  • 1.5 Pin Functions
• Chapter 2 Memory
  • 2.1 Introduction
  • 2.2 I/O Section
  • 2.3 Monitor ROM
  • 2.4 Random-Access Memory (RAM)
  • 2.5 FLASH Memory
    • 2.5.1 Functional Description
    • 2.5.2 FLASH Control Register
    • 2.5.3 FLASH Page Erase Operation
    • 2.5.4 FLASH Mass Erase Operation
    • 2.5.5 FLASH Program Operation
    • 2.5.6 FLASH Block Protection
    • 2.5.7 FLASH Block Protect Register
• Chapter 3 Configuration and Mask Option Registers (CONFIG and MOR)
  • 3.1 Introduction
  • 3.2 Functional Description
  • 3.3 Configuration Register 1 (CONFIG1)
  • 3.4 Configuration Register 2 (CONFIG2)
  • 3.5 Mask Option Register (MOR)
• Chapter 4 System Integration Module (SIM)
  • 4.1 Introduction
  • 4.2 SIM Bus Clock Control and Generation
    • 4.2.1 Bus Timing
    • 4.2.2 Clock Start-Up from POR or LVI Reset
    • 4.2.3 Clocks in Stop Mode and Wait Mode
  • 4.3 Reset and System Initialization
    • 4.3.1 External Pin Reset
    • 4.3.2 Active Resets from Internal Sources
      • 4.3.2.1 Power-On Reset
      • 4.3.2.2 Computer Operating Properly (COP) Reset
      • 4.3.2.3 Illegal Opcode Reset
      • 4.3.2.4 Illegal Address Reset
      • 4.3.2.5 Low-Voltage Inhibit (LVI) Reset
  • 4.4 SIM Counter
    • 4.4.1 SIM Counter During Power-On Reset
    • 4.4.2 SIM Counter During Stop Mode Recovery
    • 4.4.3 SIM Counter and Reset States
  • 4.5 Exception Control
    • 4.5.1 Interrupts
      • 4.5.1.1 Hardware Interrupts
      • 4.5.1.2 SWI Instruction
    • 4.5.2 Interrupt Status Registers
      • 4.5.2.1 Interrupt Status Register 1
      • 4.5.2.2 Interrupt Status Register 2
      • 4.5.2.3 Interrupt Status Register 3
    • 4.5.3 Reset
    • 4.5.4 Break Interrupts
    • 4.5.5 Status Flag Protection in Break Mode
  • 4.6 Low-Power Modes
    • 4.6.1 Wait Mode
    • 4.6.2 Stop Mode
  • 4.7 SIM Registers
    • 4.7.1 Break Status Register (BSR)
    • 4.7.2 Reset Status Register (RSR)
    • 4.7.3 Break Flag Control Register (BFCR)
• Chapter 5 Oscillator (OSC)
  • 5.1 Introduction
  • 5.2 Oscillator Selection
    • 5.2.1 XTAL Oscillator
    • 5.2.2 RC Oscillator
  • 5.3 Internal Oscillator
  • 5.4 I/O Signals
    • 5.4.1 Crystal Amplifier Input Pin (OSC1)
    • 5.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6)
    • 5.4.3 Oscillator Enable Signal (SIMOSCEN)
    • 5.4.4 XTAL Oscillator Clock (XTALCLK)
    • 5.4.5 RC Oscillator Clock (RCCLK)
    • 5.4.6 Oscillator Out 2 (2OSCOUT)
    • 5.4.7 Oscillator Out (OSCOUT)
    • 5.4.8 Internal Oscillator Clock (ICLK)
  • 5.5 Low Power Modes
    • 5.5.1 Wait Mode
    • 5.5.2 Stop Mode
  • 5.6 Oscillator During Break Mode
• Chapter 6 Timer Interface Module (TIM)
  • 6.1 Introduction
  • 6.2 Features
  • 6.3 Pin Name Conventions
  • 6.4 Functional Description
    • 6.4.1 TIM Counter Prescaler
    • 6.4.2 Input Capture
    • 6.4.3 Output Compare
      • 6.4.3.1 Unbuffered Output Compare
      • 6.4.3.2 Buffered Output Compare
    • 6.4.4 Pulse Width Modulation (PWM)
      • 6.4.4.1 Unbuffered PWM Signal Generation
      • 6.4.4.2 Buffered PWM Signal Generation
      • 6.4.4.3 PWM Initialization
  • 6.5 Interrupts
  • 6.6 Low-Power Modes
    • 6.6.1 Wait Mode
    • 6.6.2 Stop Mode
  • 6.7 TIM During Break Interrupts
  • 6.8 I/O Signals
    • 6.8.1 TIM Clock Pin (ADC12/T2CLK)
    • 6.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1)
  • 6.9 I/O Registers
    • 6.9.1 TIM Status and Control Register
    • 6.9.2 TIM Counter Registers
    • 6.9.3 TIM Counter Modulo Registers
    • 6.9.4 TIM Channel Status and Control Registers
    • 6.9.5 TIM Channel Registers
• Chapter 7 Serial Communications Interface (SCI)
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 Pin Name Conventions
  • 7.4 Functional Description
    • 7.4.1 Data Format
    • 7.4.2 Transmitter
      • 7.4.2.1 Character Length
      • 7.4.2.2 Character Transmission
      • 7.4.2.3 Break Characters
      • 7.4.2.4 Idle Characters
      • 7.4.2.5 Inversion of Transmitted Output
      • 7.4.2.6 Transmitter Interrupts
    • 7.4.3 Receiver
      • 7.4.3.1 Character Length
      • 7.4.3.2 Character Reception
      • 7.4.3.3 Data Sampling
      • 7.4.3.4 Framing Errors
      • 7.4.3.5 Baud Rate Tolerance
      • 7.4.3.6 Receiver Wakeup
      • 7.4.3.7 Receiver Interrupts
      • 7.4.3.8 Error Interrupts
  • 7.5 Low-Power Modes
    • 7.5.1 Wait Mode
    • 7.5.2 Stop Mode
  • 7.6 SCI During Break Module Interrupts
  • 7.7 I/O Signals
    • 7.7.1 TxD (Transmit Data)
    • 7.7.2 RxD (Receive Data)
  • 7.8 I/O Registers
    • 7.8.1 SCI Control Register 1
    • 7.8.2 SCI Control Register 2
    • 7.8.3 SCI Control Register 3
    • 7.8.4 SCI Status Register 1
    • 7.8.5 SCI Status Register 2
    • 7.8.6 SCI Data Register
    • 7.8.7 SCI Baud Rate Register
• Chapter 8 Multi-Master IIC Interface (MMIIC)
  • 8.1 Introduction
  • 8.2 Features
  • 8.3 I/O Pins
  • 8.4 Functional Description
    • 8.4.1 IIC Protocol
    • 8.4.2 START Signal
    • 8.4.3 Slave Address Transmission
    • 8.4.4 Data Transfer
    • 8.4.5 STOP Signal
    • 8.4.6 Repeated START Signal
    • 8.4.7 Arbitration Procedure
    • 8.4.8 Clock Synchronization
    • 8.4.9 Handshaking
    • 8.4.10 Clock Stretching
    • 8.4.11 Modes of Operation
  • 8.5 Interrupts
  • 8.6 Low-Power Modes
    • 8.6.1 Wait Mode
    • 8.6.2 Stop Mode
  • 8.7 MMIIC During Break Interrupts
  • 8.8 Multi-Master IIC Registers
    • 8.8.1 Multi-Master IIC Address Register (MMADR)
    • 8.8.2 Multi-Master IIC Control Register (MMCR)
    • 8.8.3 Multi-Master IIC Master Control Register (MIMCR)
    • 8.8.4 Multi-Master IIC Status Register (MMSR)
    • 8.8.5 Multi-Master IIC Data Transmit Register (MMDTR)
    • 8.8.6 Multi-Master IIC Data Receive Register (MMDRR)
  • 8.9 Programming Considerations
• Chapter 9 Analog-to-Digital Converter (ADC)
  • 9.1 Introduction
  • 9.2 Features
  • 9.3 Functional Description
    • 9.3.1 Clock Select and Divide Circuit
    • 9.3.2 Input Select and Pin Control
    • 9.3.3 Conversion Control
      • 9.3.3.1 Initiating Conversions
      • 9.3.3.2 Completing Conversions
      • 9.3.3.3 Aborting Conversions
      • 9.3.3.4 Total Conversion Time
    • 9.3.4 Sources of Error
      • 9.3.4.1 Sampling Error
      • 9.3.4.2 Pin Leakage Error
      • 9.3.4.3 Noise-Induced Errors
      • 9.3.4.4 Code Width and Quantization Error
      • 9.3.4.5 Linearity Errors
      • 9.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes
  • 9.4 Interrupts
  • 9.5 Low-Power Modes
    • 9.5.1 Wait Mode
    • 9.5.2 Stop Mode
  • 9.6 ADC10 During Break Interrupts
  • 9.7 Input/Output Signals
    • 9.7.1 ADC10 Analog Power Pin (VDDA)
    • 9.7.2 ADC10 Analog Ground Pin (VSSA)
    • 9.7.3 ADC10 Voltage Reference High Pin (VREFH)
    • 9.7.4 ADC10 Voltage Reference Low Pin (VREFL)
    • 9.7.5 ADC10 Channel Pins (ADn)
  • 9.8 Registers
    • 9.8.1 ADC10 Status and Control Register
    • 9.8.2 ADC10 Result High Register (ADRH)
    • 9.8.3 ADC10 Result Low Register (ADRL)
    • 9.8.4 ADC10 Clock Register (ADCLK)
• Chapter 10 Input/Output (I/O) Ports
  • 10.1 Introduction
  • 10.2 Port A
    • 10.2.1 Port A Data Register (PTA)
    • 10.2.2 Data Direction Register A (DDRA)
    • 10.2.3 Port A Input Pull-Up Enable Registers
  • 10.3 Port B
    • 10.3.1 Port B Data Register (PTB)
    • 10.3.2 Data Direction Register B (DDRB)
  • 10.4 Port D
    • 10.4.1 Port D Data Register (PTD)
    • 10.4.2 Data Direction Register D (DDRD)
    • 10.4.3 Port D Control Register (PDCR)
  • 10.5 Port E
    • 10.5.1 Port E Data Register (PTE)
    • 10.5.2 Data Direction Register E (DDRE)
• Chapter 11 External Interrupt (IRQ)
  • 11.1 Introduction
  • 11.2 Features
  • 11.3 Functional Description
    • 11.3.1 IRQ Pin
  • 11.4 IRQ Module During Break Interrupts
  • 11.5 IRQ Status and Control Register (INTSCR)
• Chapter 12 Keyboard Interrupt Module (KBI)
  • 12.1 Introduction
  • 12.2 Features
  • 12.3 I/O Pins
  • 12.4 Functional Description
    • 12.4.1 Keyboard Initialization
  • 12.5 Keyboard Interrupt Registers
    • 12.5.1 Keyboard Status and Control Register
    • 12.5.2 Keyboard Interrupt Enable Register
  • 12.6 Low-Power Modes
    • 12.6.1 Wait Mode
    • 12.6.2 Stop Mode
  • 12.7 Keyboard Module During Break Interrupts
• Chapter 13 Computer Operating Properly (COP)
  • 13.1 Introduction
  • 13.2 Functional Description
  • 13.3 I/O Signals
    • 13.3.1 ICLK
    • 13.3.2 COPCTL Write
    • 13.3.3 Power-On Reset
    • 13.3.4 Internal Reset
    • 13.3.5 Reset Vector Fetch
    • 13.3.6 COPD (COP Disable)
    • 13.3.7 COPRS (COP Rate Select)
  • 13.4 COP Control Register
  • 13.5 Interrupts
  • 13.6 Monitor Mode
  • 13.7 Low-Power Modes
    • 13.7.1 Wait Mode
    • 13.7.2 Stop Mode
  • 13.8 COP Module During Break Mode
• Chapter 14 Low-Voltage Inhibit (LVI)
  • 14.1 Introduction
  • 14.2 Features
  • 14.3 Functional Description
  • 14.4 LVI Control Register (CONFIG2/CONFIG1)
  • 14.5 Low-Power Modes
    • 14.5.1 Wait Mode
    • 14.5.2 Stop Mode
• Chapter 15 Central Processor Unit (CPU)
  • 15.1 Introduction
  • 15.2 Features
  • 15.3 CPU Registers
    • 15.3.1 Accumulator
    • 15.3.2 Index Register
    • 15.3.3 Stack Pointer
    • 15.3.4 Program Counter
    • 15.3.5 Condition Code Register
  • 15.4 Arithmetic/Logic Unit (ALU)
  • 15.5 Low-Power Modes
    • 15.5.1 Wait Mode
    • 15.5.2 Stop Mode
  • 15.6 CPU During Break Interrupts
  • 15.7 Instruction Set Summary
  • 15.8 Opcode Map
• Chapter 16 Development Support
  • 16.1 Introduction
  • 16.2 Break Module (BRK)
    • 16.2.1 Functional Description
    • 16.2.2 Flag Protection During Break Interrupts
    • 16.2.3 CPU During Break Interrupts
    • 16.2.4 TIM During Break Interrupts
    • 16.2.5 COP During Break Interrupts
    • 16.2.6 Break Module Registers
      • 16.2.6.1 Break Status and Control Register (BRKSCR)
      • 16.2.6.2 Break Address Registers
      • 16.2.6.3 Break Status Register
      • 16.2.6.4 Break Flag Control Register (BFCR)
    • 16.2.7 Low-Power Modes
      • 16.2.7.1 Wait Mode
      • 16.2.7.2 Stop Mode
  • 16.3 Monitor Module (MON)
    • 16.3.1 Functional Description
    • 16.3.2 Entering Monitor Mode
    • 16.3.3 Baud Rate
    • 16.3.4 Data Format
    • 16.3.5 Echoing
    • 16.3.6 Break Signal
    • 16.3.7 Commands
    • 16.3.8 Security
    • 16.3.9 ROM-Resident Routines
      • 16.3.9.1 PRGRNGE
      • 16.3.9.2 ERARNGE
      • 16.3.9.3 LDRNGE
      • 16.3.9.4 MON_PRGRNGE
      • 16.3.9.5 MON_ERARNGE
      • 16.3.9.6 MON_LDRNGE
      • 16.3.9.7 EE_WRITE
      • 16.3.9.8 EE_READ
• Chapter 17 Electrical Specifications
  • 17.1 Introduction
  • 17.2 Absolute Maximum Ratings
  • 17.3 Functional Operating Range
  • 17.4 Thermal Characteristics
  • 17.5 5-V DC Electrical Characteristics
  • 17.6 5-V Control Timing
  • 17.7 5-V Oscillator Characteristics
  • 17.8 3-V DC Electrical Characteristics
  • 17.9 3-V Control Timing
  • 17.10 3-V Oscillator Characteristics
  • 17.11 Typical Supply Currents
  • 17.12 Timer Interface Module Characteristics
  • 17.13 ADC10 Characteristics
  • 17.14 MMIIC Electrical Characteristics
  • 17.15 Memory Characteristics
• Chapter 18 Ordering Information and Mechanical Specifications
  • 18.1 Introduction
  • 18.2 MC Order Numbers
  • 18.3 Package Dimensions