· Preliminary

Freescale Semiconductor
Hardware Specification

MCF5235EC

Rev. 1.3, 10/2004

Technical Data

Table of Contents

The MCF523x is a family of highly-integrated 32-bit
microcontrollers based on the V2 ColdFire
microarchitecture. Featuring a 16 or 32 channel eTPU,
64 Kbytes of internal SRAM, a 2-bank SDRAM
controller, four 32-bit timers with dedicated DMA, a 4
channel DMA controller, up to 2 CAN modules, 3
UARTs and a queued SPI, the MCF523x family has been
designed for general purpose industrial control
applications. It is also a high-performance upgrade for
users of the MC68332. This document provides an
overview of the MCF523x microcontroller family, as
well as detailed descriptions of the mechanical and
electrical characteristics of the devices.

The MCF523x family is based on the Version 2 ColdFire
reduced instruction set computing (RISC)
microarchitecture operating at a core frequency of up to
150 MHz and bus frequency up to 75 MHz.

Overview

This 32-bit device's on-chip modules include:

Overview ......................................................... 1

Signal Descriptions.......................................... 9

Modes of Operation ....................................... 14

Design Recommendations ............................ 17

Mechanicals/Pinouts and Part Numbers ....... 25

Preliminary Electrical Characteristics ............ 34

Documentation .............................................. 58

MCF523x Integrated
Microprocessor
Hardware Specification

32-bit Embedded Controller Division

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Overview

Freescale Semiconductor

V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 Dhrystone 2.1
MIPS @ 150 MHz

eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with
Nexus Class 1 debug support

64 Kbytes of internal SRAM

External bus speed of one half the CPU operating frequencey (75 MHz bus @ 150 MHz core)

10/100 Mbps bus-mastering Ethernet controller

8 Kbytes of configurable instruction/data cache

Three universal asynchronous receiver/transmitters (UARTs)

Controller area network 2.0B (FlexCAN) module
-- Optional second FlexCAN module multiplexed with the third UART

Inter-integrated circuit (I

CTM) bus controller

Queued serial peripheral interface (QSPI) module

Hardware cryptography accelerator (optional)
-- Random number generator
-- DES/3DES/AES block cipher engine
-- MD5/SHA-1/HMAC accelerator

Four channel 32-bit direct memory access (DMA) controller

Four channel 32-bit input capture/output compare timers with optional DMA support

Four channel 16-bit periodic interrupt timers (PITs)

Programmable software watchdog timer

Interrupt controller capable of handling up to 126 interrupt sources

Clock module with integrated phase locked loop (PLL)

External bus interface module including a 2-bank synchronous DRAM controller

32-bit non-multiplexed bus with up to 8 chip select signals that support paged mode Flash
memories

1.1

MCF523x Family Configurations

Table 1. MCF523x Family Configurations

Module

5232

5233

5234

5235

ColdFire V2 Core with EMAC
(Enhanced Multiply-Accumulate
Unit)

Enhanced Time Processor Unit
with memory (eTPU)

16-ch

32-ch

16-ch

32-ch

System Clock

up to 150 MHz

Performance (Dhrystone/2.1 MIPS)

up to 144

Overview

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

1.2

Block Diagram

The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA)
package.

Figure 1

shows a top-level block diagram of the MCF5235, the superset device.

Instruction/Data Cache

8 Kbytes

Static RAM (SRAM)

64 Kbytes

Interrupt Controllers (INTC)

Edge Port Module (EPORT)

External Interface Module (EIM)

4-channel Direct-Memory Access
(DMA)

SDRAM Controller

Fast Ethernet Controller (FEC)

Cryptography - Security module for
data packets processing

Watchdog Timer (WDT)

Four Periodic Interrupt Timers (PIT)

32-bit DMA Timers

QSPI

UART(s)

FlexCAN 2.0B - Controller-Area
Network communication module

General Purpose I/O Module
(GPIO)

JTAG - IEEE 1149.1 Test Access
Port

Package

160 QFP

196

MAPBGA

256

MAPBGA

256

MAPBGA

256

MAPBGA

Table 1. MCF523x Family Configurations (continued)

Module

5232

5233

5234

5235

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Overview

Freescale Semiconductor

Figure 1. MCF5235 Block Diagram

64 Kbytes

SRAM

(8Kx16)x4

FlexCAN

eTPU

EIM

ETHERNET

V2 ColdFire CPU

INTC0

Watchdog

PIT0

JTAG

TAP

CACHE

(1Kx32)x2

PIT1

PIT2

PIT3

4 CH DMA

UART

QSPI

DTIM

Timer

i
n Muxin

PLL

CLKGEN

UART

8 Kbytes

Edge

Port

SDRAMC

CHIP

EBI

SELECTS

(To/From PADI)

(To/From

eTPU

CANTX

CANRX

FAST

CONTROLLER

(FEC)

FEC

DTnIN

DTnOUT

UnRXD

UnTXD

I2C_SDA

I2C_SCL

SDRAMC

QSPI

UnRTS

UnCTS

PORTS

CIM

(To/From PADI)

NEXUS

(GPIO)

D[31:0]

A[23:0]

R/W

CS[3:0]

TSIZ[1:0]

TEA

BS[3:0]

DIV

EMAC

DREQ[2:0]

INTC1

Arbiter

(To/From SRAM backdoor)

(To/From Arbiter backdoor)

SKHA

RNGA

MDHA

(To/From PADI)

Cryptography

Modules

(x2)

DACK[2:0]

BDM

(To/From INTC)

PADI)

JTAG_EN

Overview

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

1.3

Features

The following section gives a brief overview of this family's feature set. For more detailed information see
the MCF5235 Reference Manual (MCF5235RM).

1.3.1

Feature Overview

Version 2 ColdFire variable-length RISC processor core
-- Static operation
-- 32-bit address and data path on-chip
-- Processor core runs at twice the bus frequency
-- Sixteen general-purpose 32-bit data and address registers
-- Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the

user stack pointer register, and 4 new instructions for improved bit processing

-- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit

signal processing algorithms

-- Illegal instruction decode that allows for 68K emulation support

Enhanced Time Processor Unit (eTPU)
-- Event triggered VLIW processor timer subsystem
-- 32 channels
-- 24-bit timer resolution
-- 6 Kbyte of code memory and 1.5 Kbyte of data memory
-- Variable number of parameters allocatable per channel
-- Double match/capture channels
-- Angle mode support
-- DMA and interrupt request support
-- Nexus Class 1 Debug support

System debug support
-- Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port

with cross triggering operations for ease of use

-- Unified programming model including both ColdFire and Nexus debug registers
-- Real time trace for determining dynamic execution path
-- Background debug mode (BDM) for in-circuit debugging
-- Real time debug support, with two user-visible hardware breakpoint registers (PC and address

with optional data) that can be configured into a 1- or 2-level trigger

On-chip memories
-- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
-- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Overview

Freescale Semiconductor

masters (e.g., DMA, FEC)

Fast Ethernet Controller (FEC)
-- 10 BaseT capability, half duplex or full duplex
-- 100 BaseT capability, half duplex or full duplex
-- On-chip transmit and receive FIFOs
-- Built-in dedicated DMA controller
-- Memory-based flexible descriptor rings
-- Media independent interface (MII) to external transceiver (PHY)

FlexCAN Modules (up to 2)
-- Full implementation of the CAN protocol specification version 2.0B

Standard Data and Remote Frames (up to 109 bits long)
Extended Data and Remote Frames (up to 127 bits long)
08 bytes data length
Programmable bit rate up to 1 Mbit/sec

-- Flexible Message Buffers (MBs), totalling up to 16 message buffers of 08 bytes data length

each, configurable as Rx or Tx, all supporting standard and extended messages

-- Unused MB space can be used as general purpose RAM space
-- Listen only mode capability
-- Content-related addressing
-- Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for

MB15

-- Programmable transmit-first scheme: lowest ID or lowest buffer number
-- "Time stamp" based on 16-bit free-running timer
-- Global network time, synchronized by a specific message

Three Universal Asynchronous Receiver Transmitters (UARTs)
-- 16-bit divider for clock generation
-- Interrupt control logic
-- Maskable interrupts
-- DMA support
-- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
-- Up to 2 stop bits in 1/16 increments
-- Error-detection capabilities
-- Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines
-- Transmit and receive FIFO buffers

C Module

-- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

Overview

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

-- Fully compatible with industry-standard I

C bus

-- Master or slave modes support multiple masters
-- Automatic interrupt generation with programmable level

Queued Serial Peripheral Interface (QSPI)
-- Full-duplex, three-wire synchronous transfers
-- Up to four chip selects available
-- Master mode operation only
-- Programmable master bit rates
-- Up to 16 pre-programmed transfers

Four 32-bit DMA Timers
-- 13-ns resolution at 75 MHz
-- Programmable sources for clock input, including an external clock option
-- Programmable prescaler
-- Input-capture capability with programmable trigger edge on input pin
-- Output-compare with programmable mode for the output pin
-- Free run and restart modes
-- Maskable interrupts on input capture or reference-compare
-- DMA trigger capability on input capture or reference-compare

Four Periodic Interrupt Timers (PITs)
-- 16-bit counter
-- Selectable as free running or count down

Software Watchdog Timer
-- 16-bit counter
-- Low power mode support

Phase Locked Loop (PLL)
-- Crystal or external oscillator reference
-- 8 to 25 MHz reference frequency for normal PLL mode
-- 24 to 75 MHz oscillator reference frequency for 2:1 mode
-- Separate clock output pin

Interrupt Controllers (x2)
-- Support for up to 110 interrupt sources organized as follows:

103 fully-programmable interrupt sources
7 fixed-level external interrupt sources

-- Unique vector number for each interrupt source
-- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Overview

Freescale Semiconductor

-- Support for hardware and software interrupt acknowledge (IACK) cycles
-- Combinatorial path to provide wake-up from low power modes

DMA Controller
-- Four fully programmable channels
-- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along

with support for 16-byte (4

× 32-bit) burst transfers

-- Source/destination address pointers that can increment or remain constant
-- 24-bit byte transfer counter per channel
-- Auto-alignment transfers supported for efficient block movement
-- Bursting and cycle steal support
-- Software-programmable connections between the 12 DMA requesters in the UARTs (3),

32-bit timers (4) plus external logic (4) the four DMA channels and the eTPU (1)

External Bus Interface
-- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
-- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
-- Support for n-1-1-1 burst fetches from page mode Flash
-- Glueless interface to SRAM devices with or without byte strobe inputs
-- Programmable wait state generator
-- 32-bit bidirectional data bus
-- 24-bit address bus
-- Up to eight chip selects available
-- Byte/write enables (byte strobes)
-- Ability to boot from external memories that are 8, 16, or 32 bits wide

Chip Integration Module (CIM)
-- System configuration during reset
-- Selects one of four clock modes
-- Sets boot device and its data port width
-- Configures output pad drive strength
-- Unique part identification number and part revision number
-- Reset

Separate reset in and reset out signals
Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of

clock, PLL loss of lock

Status flag indication of source of last reset

General Purpose I/O interface
-- Up to 142 bits of general purpose I/O

Signal Descriptions

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

-- Bit manipulation supported via set/clear functions
-- Unused peripheral pins may be used as extra GPIO

JTAG support for system level board testing

Signal Descriptions

This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF523x signals, consult the MCF5235 Reference Manual (MCF5235RM).

2.1

Signal Properties

Table 2

lists all of the signals grouped by function. The "Dir" column is the direction for the primary

function of the pin. Refer to

Section 5, "Mechanicals/Pinouts and Part Numbers

," for package diagrams.

NOTE

In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. MCF523x Signal Information and Muxing

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

Reset

RESET

N13

T15

RSTOUT

P13

T14

Clock

EXTAL

M14

P16

XTAL

N14

R16

CLKOUT

K14

M16

Mode Selection

CLKMOD[1:0]

19,20

G5, H5

J3, J2

RCON

K10

P13

External Memory Interface and Ports

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Signal Descriptions

Freescale Semiconductor

A[23:21]

PADDR[7:5]

CS[6:4]

126, 125,

124

B11, C11,

D11

B14, C14,

A15

B14, C14,

A15

B14, C14,

A15

A[20:0]

123:115,
112:106,

102:98

A12, B12,
C12, A13,
B13, B14,

C13, C14,
D12, D13,
D14, E11,

E12, E13,
E14, F12,

F13, F14,

G11, G12,

G13

B15, B16,

C15, C16,
D16, D15,

D14, E16,
E15, E14,

E13, F15,
F14, F13,

G15, G14,
G13, H16,

H15, H14,

H13

B15, B16,

C15, C16,
D16, D15,
D14, E16,

E15, E14,

E13, F15,
F14, F13,

G15, G14,
G13, H16,

H15, H14,

H13

B15, B16,

C15, C16,
D16, D15,
D14, E16,

E15, E14,
E13, F15,

F14, F13,

G15, G14,

G13, H16,
H15, H14,

H13

D[31:16]

21:24, 26:30,

33:39

G1, G2, H1,

H2, H3, H4,

J1, J2, J3,

J4, K1, K2,

K3, K4, L1,

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

D[15:8]

PDATAH[7:0]

42:49,

M1, N1, M2,

N2, P2, L3,

M3, N3,

R2, T2, N3,
P3, R3, T3,

N4, P4,

R2, T2, N3,

P3, R3, T3,

N4, P4,

R2, T2, N3,
P3, R3, T3,

N4, P4,

D[7:0]

PDATAL[7:0]

50:52, 56:60 P3, M4, N4,

P4, L5, M5,

N5, P5

R4, T4, P5,

R5, N6, P6,

R6, N7

R4, T4, P5,

R5, N6, P6,

R6, N7

R4, T4, P5,

R5, N6, P6,

R6, N7

BS[3:0]

PBS[7:4]

CAS[3:0]

143:140

B6, C6, D7,

C9, B9, A9,

A10

C9, B9, A9,

A10

C9, B9, A9,

A10

PBUSCTL7

PBUSCTL6

H11

K14

TEA

PBUSCTL5

DREQ1

J14

K13

R/W

PBUSCTL4

J13

L16

TSIZ1

PBUSCTL3

DACK1

TSIZ0

PBUSCTL2

DACK0

PBUSCTL1

DACK2

H13

K16

TIP

PBUSCTL0

DREQ0

H12

K15

Chip Selects

CS[7:4]

PCS[7:4]

B9, A10,

C10, A11

C12, A13,

C13, A14

C12, A13,

C13, A14

C12, A13,

C13, A14

CS[3:2]

PCS[3:2]

SD_CS[1:0]

134,133

A9, C9

B12, D12

CS1

PCS1

130

B10

B13

CS0

129

D10

D13

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

Signal Descriptions

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

SDRAM Controller

SD_WE

PSDRAM5

K13

L13

SD_SCAS

PSDRAM4

K12

M15

SD_SRAS

PSDRAM3

K11

M14

SD_CKE

PSDRAM2

139

C10

SD_CS[1:0]

PSDRAM[1:0]

L12, L13

N15, M13

External Interrupts Port

IRQ[7:3]

PIRQ[7:3]

IRQ7=64
IRQ4=65

N7, M7, L7,

P8, N8

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

IRQ2

PIRQ2

DREQ2

IRQ1

PIRQ1

N10

eTPU

TPUCH31

ECOL

TPUCH30

ECRS

TPUCH29

ERXCLK

TPUCH28

ERXDV

TPUCH[27:24]

ERXD[3:0]

D3, D4, C3,

TPUCH23

ERXER

TPUCH22

ETXCLK

TPUCH21

ETXEN

TPUCH20

ETXER

TPUCH[19:16]

ETXD[3:0]

B6,B5, A5,

TPUCH[15:0]

11, 10, 7:2,

159:154,
152, 151

E2, E1, D1

D2, D3, C1,

C2, B1, B2,
A2, C3, B3,
A3, A4, C4,

F2, E1, E2,

D1, D2, C1,
C2, B1, B2,

A2, B3, A3,
B4, A4, A6,

F2, E1, E2,

D1, D2, C1,
C2, B1, B2,

A2, B3, A3,
B4, A4, A6,

F2, E1, E2,

D1, D2, C1,
C2, B1, B2,

A2, B3, A3,
B4, A4, A6,

TCRCLK

PETPU2

UTPUODIS

PETPU1

H10

J13

LTPUODIS

PETPU0

G10

J14

FEC

EMDIO

PFECI2C2

I2C_SDA

U2RXD

I/O

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Signal Descriptions

Freescale Semiconductor

EMDC

PFECI2C3

I2C_SCL

U2TXD

ECOL

ECRS

ERXCLK

ERXDV

ERXD[3:0]

D3, D4, C3,

ERXER

ETXCLK

ETXEN

ETXER

ETXD[3:0]

B6, B5, A5,

Feature Control

eTPU/EthENB

I2C_SDA

PFECI2C1

CAN0RX

I/O

J12

L15

I2C_SCL

PFECI2C0

CAN0TX

I/O

J11

L14

DMA

DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads.

Please refer to the following pins for muxing:

TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1,

TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2,

TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0.

QSPI

QSPI_CS1

PQSPI4

SD_CKE

B10

QSPI_CS0

PQSPI3

147

QSPI_CLK

PQSPI2

I2C_SCL

148

QSPI_DIN

PQSPI1

I2C_SDA

149

QSPI_DOUT

PQSPI0

150

UARTs

U2TXD

PUARTH1

CAN1TX

D11

U2RXD

PUARTH0

CAN1RX

D10

U1CTS

PUARTL7

U2CTS

C11

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

Signal Descriptions

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

U1RTS

PUARTL6

U2RTS

B11

U1TXD

PUARTL5

CAN0TX

135

A12

U1RXD

PUARTL4

CAN0RX

136

A11

U0CTS

PUARTL3

U0RTS

PUARTL2

U0TXD

PUARTL1

U0RXD

PUARTL0

DMA Timers

DT3IN

PTIMER7

U2CTS

QSPI_CS2

H14

J15

DT3OUT

PTIMER6

U2RTS

QSPI_CS3

G14

J16

DT2IN

PTIMER5

DREQ2

DT2OUT

P10

DT2OUT

PTIMER4

DACK2

R10

DT1IN

PTIMER3

DREQ1

DT1OUT

PTIMER2

DACK1

DT0IN

PTIMER1

DREQ0

DT0OUT

PTIMER0

DACK0

BDM/JTAG

DSCLK

TRST

N11

PSTCLK

TCLK

T10

BKPT

TMS

P10

P11

DSI

TDI

M10

T11

DSO

TDO

N10

R11

JTAG_EN

N13

DDATA[3:0]

M12, N12,

P12, L11

N14, P14,

T13, R13

N14, P14,

T13, R13

N14, P14,

T13, R13

PST[3:0]

77:74

M11, N11,

P11, L10

T12, R12,

P12, N12

T12, R12,

P12, N12

T12, R12,

P12, N12

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Modes of Operation

Freescale Semiconductor

Modes of Operation

3.1

Chip Configuration Mode--Device
Operating Options

Chip operating mode:
-- Master mode

Boot device/size:
-- External device boot

32-bit
16-bit (Default)

Test

TEST

PLL_TEST

R14

Power Supplies

VDDPLL

M13

P15

VSSPLL

L14

R15

OVDD

1, 9, 17, 32,

41, 55, 62,
69, 81, 90,

95, 105, 114,

128, 132,

138, 146

E5, E7,

E10, F7, F9,

G6, G8, H7,

H8, H9, J6,

J8, J10, K5,

K6, K8

E6:11, F5, F7:10, F12, G5, G6, G11,

G12, H5, H6, H11, H12, J5, J6, J11,

J12, K5, K6, K11, K12, L5, L7:10,

L12, M6:M11

VSS

8, 16, 25, 31,

40, 54, 61,
67, 80, 88,

94, 104, 113,

127, 131,
137, 145,

153, 160

A1, A14,

E6, E9, F6,

F8, F10,

G7, G9, H6,

J5, J7, J9,

K7, P1, P14

A1, A16, E5, E12, F6, F11, F16,

G7:10, H7: 10, J1, J7:10, K7:10, L6,

L11, M5, M12, N16, T1, T6, T16

VDD

15, 53, 103,

144

D6, F11,

G4, L4

A8, G16, H1, T5

NOTES:

Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the
exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1 Alternate 2

Dir.

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

Modes of Operation

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

8-bit

Output pad strength:
-- Partial drive strength (Default)
-- Full drive strength

Clock mode:
-- Normal PLL with external crystal
-- Normal PLL with external clock
-- 1:1 PLL Mode
-- External oscillator mode (no PLL)

Chip Select Configuration:
-- PADDR[7:5] configured as chip select(s) and/or address line(s)

PADDR[7:5] configured as A23-A21 (default)
PADDR configured as CS6, PADDR[6:5] as A22-A21
PADDR[7:6] configured as CS[6:5], PADDR5 as A21
PADDR[7:5] configured as CS[6:4]

3.1.1

Chip Configuration Pins

Table 3. Configuration Pin Descriptions

Pin

Chip Configuration

Function

Pin State/Meaning

Comments

RCON

Chip configuration
enable

1 Disabled
0 Enabled

Active low: if asserted, then all
configuration pins must be driven
appropriately for desired operation

D16

Select chip
operating mode

1 Master
0 Reserved

D20, D19

Select external boot
device data port size

00,11 External (32-bit)
10 External (8-bit)
01 External (16-bit)

Value read defaults to 32-bit

D21

Select output pad
drive strength

1 Full
0 Partial

CLKMOD1,
CLKMOD0

Select clock mode

00 External clock mode (no

PLL)

01 1:1 PLL mode
10 Normal PLL with

external clock reference

11 Normal PLL with crystal

clock reference

VDDPLL must be supplied if a PLL
mode is selected

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Modes of Operation

Freescale Semiconductor

3.2

Low Power Modes

The following features are available to support applications which require low power.

Four modes of operation:
-- RUN
-- WAIT
-- DOZE
-- STOP

Ability to shut down most peripherals independently.

Ability to shut down the external CLKOUT pin.

There are four modes of operation: RUN, WAIT, DOZE, and STOP. The system enters a low power mode
when the user programs the low power bits (LPMD) in the LPCR (Low Power Control Register) in the
CIM before the CPU core executes a STOP instruction. This idles the CPU with no cycles active. The
LPMD bits indicate to the system and clock controller to power down and stop the clocks appropriately.
During STOP mode, the system clock is stopped low.

A wakeup event is required to exit a low power mode and return back to RUN mode. Wakeup events
consist of any of the following conditions. See the following sections for more details.

1. Any type of reset.
2. Assertion of the BKPT pin to request entry into Debug mode.
3. Debug request bit in the BDM control register to request entry into debug mode.
4. Any valid interrupt request.

3.2.1

RUN Mode

RUN mode is the normal system operating mode. Current consumption in this mode is related directly to
the frequency chosen for the system clock.

D25, D24

Select chip select /
address line

00 PADDR[7:5] configured

as A23-A21 (default)

10 PADDR7 configured as

CS6,
PADDR[6:5] as A22-A21

01 PADDR[7:6] configured

as CS[6:5],
PADDR5 as A21

11 PADDR[7:5] configured

as CS[6:4]

JTAG_EN

Selects BDM or
JTAG mode

0 BDM mode
1 JTAG mode

Table 3. Configuration Pin Descriptions (continued)

Pin

Chip Configuration

Function

Pin State/Meaning

Comments

Design Recommendations

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

3.2.2

WAIT Mode

WAIT mode is intended to be used to stop only the CPU core and memory clocks until a wakeup event is
detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts,
which cause the CPU core to exit from WAIT mode.

3.2.3

DOZE Mode

DOZE mode affects the CPU core in the same manner as WAIT mode, but with a different code on the
CIM LPMD bits, which are monitored by the peripherals. Each peripheral defines individual operational
characteristics in DOZE mode. Peripherals which continue to run and have the capability of producing
interrupts may cause the CPU to exit the DOZE mode and return to the RUN mode. Peripherals which are
stopped will restart operation on exit from DOZE mode as defined for each peripheral.

3.2.4

STOP Mode

STOP mode affects the CPU core in the same manner as the WAIT and DOZE modes, but with a different
code on the CCM LPMD bits. In this mode, all clocks to the system are stopped and the peripherals cease
operation.

STOP mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting STOP mode, most peripherals retain their pre-stop status and resume operation.

3.2.5

Peripheral Shut Down

Most peripherals may be disabled by software in order to cease internal clock generation and remain in a
static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description
for further details). A peripheral may be disabled at anytime and will remain disabled during any low
power mode of operation.

Design Recommendations

4.1

Layout

Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF523x.

See application note AN1259 System Design and Layout Techniques for Noise Reduction in
processor-Based Systems.

Match the PC layout trace width and routing to match trace length to operating frequency and
board impedance. Add termination (series or therein) to the traces to dampen reflections.
Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do
cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6
mils trace and separation. Clocks get extra separation and more precise balancing.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Design Recommendations

Freescale Semiconductor

4.2

Power Supply

µF, .1 µF and .01 µF across each power supply

4.3

Decoupling

Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of
the package.

µF and .01 µF at each supply input

4.4

Buffering

Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See

Section 6, "Preliminary Electrical Characteristics

4.5

Pull-up Recommendations

Use external pull-up resistors on unused inputs. See pin table.

4.6

Clocking Recommendations

Use a multi-layer board with a separate ground plane.

Place the crystal and all other associated components as close to the EXTAL and XTAL
(oscillator pins) as possible.

Do not run a high frequency trace around crystal circuit.

Ensure that the ground for the bypass capacitors is connected to a solid ground trace.

Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop
currents in the vicinity of the crystal.

Tie the ground pin to the most solid ground in the system.

Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.

Tie XTAL to ground when an external oscillator is clocking the device.

4.7

Interface Recommendations

4.7.1

SDRAM Controller

4.7.1.1

SDRAM Controller Signals in Synchronous Mode

Table 4

shows the behavior of SDRAM signals in synchronous mode.

Design Recommendations

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

4.7.1.2

Address Multiplexing

Table 5

shows the generic address multiplexing scheme for SDRAM configurations. All possible address

connection configurations can be derived from this table.

Table 4. Synchronous DRAM Signal Connections

Signal

Description

SD_SRAS

Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SD_CS[1:0], which should not
be interfaced to the SDRAM SD_SRAS signals.

SD_SCAS

Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.

DRAMW

DRAM read/write. Asserted for write operations and negated for read operations.

SD_CS[1:0]

Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One
SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.

SD_CKE

Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.

BS[3:0]

Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.

CLKOUT

Bus clock output. Connects to the CLK input of SDRAMs.

Table 5. Generic Address Multiplexing Scheme

Address Pin Row Address Column Address

Notes Related to Port Sizes

8-bit port only

8- and 16-bit ports only

32-bit port only

16-bit port only or 32-bit port with only 8
column address lines

16-bit port only when at least 9 column
address lines are used

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Design Recommendations

Freescale Semiconductor

The following tables provide a more comprehensive, step-by-step way to determine the correct address
line connections for interfacing the MCF523x to SDRAM. To use the tables, find the one that corresponds
to the number of column address lines on the SDRAM and to the port size as seen by the MCF523x, which
is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a
2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are
shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.

Table 6. MCF523x to SDRAM Interface (8-Bit Port, 9-Column Address Lines)

MCF523x
Pins

A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

Table 7. MCF523x to SDRAM Interface (8-Bit Port,10-Column Address Lines)

MCF523x
Pins

A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

Table 8. MCF523x to SDRAM Interface (8-Bit Port,11-Column Address Lines)

MCF523x
Pins

A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20

Table 5. Generic Address Multiplexing Scheme (continued)

Address Pin Row Address Column Address

Notes Related to Port Sizes

Design Recommendations

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Table 9. MCF523x to SDRAM Interface (8-Bit Port,12-Column Address Lines)

MCF523x
Pins

A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Table 10. MCF523x to SDRAM Interface (8-Bit Port,13-Column Address Lines)

MCF523x
Pins

A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18

Table 11. MCF523x to SDRAM Interface (16-Bit Port, 8-Column Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

Table 12. MCF523x to SDRAM Interface (16-Bit Port, 9-Column Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

Table 13. MCF523x to SDRAM Interface (16-Bit Port, 10-Column Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Design Recommendations

Freescale Semiconductor

Table 14. MCF523x to SDRAM Interface (16-Bit Port, 11-Column Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Table 15. MCF523x to SDRAM Interface (16-Bit Port, 12-Column Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10

A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A10 A11 A12 A13 A14 A15 A16 A17 A18

Table 16. MCF523x to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)

MCF523x
Pins

A16 A15 A14 A13 A12 A11 A10

A18 A20 A22 A24 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A10 A11 A12 A13 A14 A15 A16 A17

Table 17. MCF523x to SDRAM Interface (32-Bit Port, 8-Column Address Lines)

MCF523x
Pins

A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

Table 18. MCF523x to SDRAM Interface (32-Bit Port, 9-Column Address Lines)

MCF523x
Pins

A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20

Design Recommendations

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

4.7.1.3

SDRAM Interfacing Example

The tables in the previous section can be used to configure the interface in the following example. To
interface one 2M

× 32-bit × 4 bank SDRAM component (8 columns) to the MCF523x, the connections

would be as shown in

Table 22

4.7.2

Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in

Table 23

Table 19. MCF523x to SDRAM Interface (32-Bit Port, 10-Column Address Lines)

MCF523x
Pins

A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

Table 20. MCF523x to SDRAM Interface (32-Bit Port, 11-Column Address Lines)

MCF523x
Pins

A15 A14 A13 A12 A11 A10

A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A10 A11 A12 A13 A14 A15 A16 A17 A18

Table 21. MCF523x to SDRAM Interface (32-Bit Port, 12-Column Address Lines)

MCF523x
Pins

A15 A14 A13 A12 A11 A10

A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31

Row

Column

SDRAM
Pins

A10 A11 A12 A13 A14 A15 A16 A17

Table 22. SDRAM Hardware Connections

SDRAM
Pins

A10 = CMD

BA0

BA1

MCF523x
Pins

A15

A14

A13

A12

A11

A10

A17

A18

A19

A20

A21

A22

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Design Recommendations

Freescale Semiconductor

The serial mode interface operates in what is generally referred to as AMD mode. The MCF523x
configuration for seven-wire serial mode connections to the external transceiver are shown in

Table 24

Refer to the M523xEVB evaluation board user's manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5235 site by navigating to:

http://www.freescale.com

Table 23. MII Mode

Signal Description

MCF523x Pin

Transmit clock

ETXCLK

Transmit enable

ETXEN

Transmit data

ETXD[3:0]

Transmit error

ETXER

Collision

ECOL

Carrier sense

ECRS

Receive clock

ERXCLK

Receive enable

ERXDV

Receive data

ERXD[3:0]

Receive error

ERXER

Management channel clock

EMDC

Management channel serial data

EMDIO

Table 24. Seven-Wire Mode Configuration

Signal Description

MCF523x Pin

Transmit clock

ETXCLK

Transmit enable

ETXEN

Transmit data

ETXD[0]

Collision

ECOL

Receive clock

ERXCLK

Receive enable

ERXDV

Receive data

ERXD[0]

Unused, configure as PB14

ERXER

Unused input, tie to ground

ECRS

Unused, configure as PB[13:11]

ERXD[3:1]

Unused output, ignore

ETXER

Unused, configure as PB[10:8]

ETXD[3:1]

Unused, configure as PB15

EMDC

Input after reset, connect to ground

EMDIO

Mechanicals/Pinouts and Part Numbers

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

4.7.2.1

FlexCAN

The FlexCAN module interface to the CAN bus is composed of 2 pins: CANTX and CANRX, which are
the serial transmitted data and the serial received data. The use of an external CAN transceiver to interface
to the CAN bus is generally required. The transceiver is capable of driving the large current needed for the
CAN bus and has current protection, against a defective CAN bus or defective stations.

4.7.3

BDM

Use the BDM interface as shown in the M523xEVB evaluation board user's manual. The schematics for
this board are accessible at the MCF523x site by navigating from:

http://www.freescale.com

following the

32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF523x and M523xEVB links.

Mechanicals/Pinouts and Part Numbers

This section contains drawings showing the pinout and the packaging and mechanical characteristics of
the MCF523x devices. See

Table 2

for a list the signal names and pin locations for each device.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Mechanicals/Pinouts and Part Numbers

Freescale Semiconductor

5.1

Pinout--196 MAPBGA

Figure 2

shows a pinout of the MCF5232CVMxxx package.

Figure 2. MCF5232CVMxxx Pinout (196 MAPBGA)

VSS

TPUCH6

TPUCH3

TPUCH2

QSPI_

DOUT

QSPI_CS0

U2RXD

U2TXD

CS3

CS6

CS4

A20

A17

VSS

TPUCH8

TPUCH7

TPUCH4

TPUCH0

QSPI_

DIN

BS3

QSPI_CS1

U1CTS

CS7

CS1

A23

A19

A16

A15

TPUCH10 TPUCH9

TPUCH5

TPUCH1 QSPI_CLK

BS2

BS0

U1RTS

CS2

CS5

A22

A18

A14

A13

TPUCH13 TPUCH12 TPUCH11

VDD

BS1

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS0

A21

A12

A11

A10

TPUCH14 TPUCH15 TCRCLK

DT0IN

OVDD

VSS

OVDD

SD_CKE

VSS

OVDD

U0TXD

U0RXD

U0CTS

DT0OUT

TEST

VSS

OVDD

VSS

OVDD

VSS

VDD

D31

D30

U0RTS

VDD

CLKMOD1

OVDD

VSS

OVDD

VSS

LTPU
ODIS

DT3OUT G

D29

D28

D27

D26

CLKMOD0

VSS

OVDD

UTPU

ODIS

TIP

DT3IN

D25

D24

D23

D22

VSS

OVDD

VSS

OVDD

VSS

OVDD

I2C_SCL

I2C_SDA

R/W

TEA

D21

D20

D19

D18

OVDD

VSS

OVDD

JTAG_EN

RCON

SD_SRAS SD_SCAS

SD_WE

CLKOUT K

D17

D16

D10

VDD

DT1IN

IRQ5

IRQ1

DT2OUT

PST0

DDATA0

SD_CS1

SD_CS0

VSSPLL

D15

D13

DT1OUT

IRQ6

IRQ2

DT2IN

TDI/DSI

PST3

DDATA3

VDDPLL

EXTAL

D14

D12

IRQ7

IRQ3

TRST/

DSCLK

TDO/DSO

PST2

DDATA2

RESET

XTAL

VSS

D11

TSIZ1

TSIZ0

IRQ4

TCLK/

PSTCLK

TMS/

BKPT

PST1

DDATA1

RSTOUT

VSS

Mechanicals/Pinouts and Part Numbers

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

5.2

Package Dimensions--196 MAPBGA

Figure 3

shows MCF5232CVMxxx package dimensions.

Figure 3. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

0.20

Laser mark for pin 1

identification in

this area

13X

0.15 Z

0.30 Z

Rotated 90 Clockwise

Detail K

View M-m

13X

0.30

0.10 Z

196X

Metalized mark for

pin 1 identification

in this area

14 13 12 11

NOTES:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances

per ASME Y14.5M, 1994.

3. Dimension B is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is defined

by the spherical crowns of the solder

balls.

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

DIM

Min Max

Millimeters

A 1.32 1.75

A1 0.27 0.47
A2 1.18 REF

b 0.35 0.65

D 15.00 BSC
E 15.00 BSC

1.00 BSC

0.50 BSC

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Mechanicals/Pinouts and Part Numbers

Freescale Semiconductor

5.2.1

Pinout--256 MAPBGA

Figure 4

through

Figure 6

show pinouts of the MCF5233CVMxxx, MCF5234CVMxxx, and

MCF5235CVMxxx packages.

Figure 4. MCF5233CVMxxx Pinout (256 MAPBGA)

VSS

TPUCH6

TPUCH4

TPUCH2 TPUCH17 TPUCH1

TPUCH0

VDD

BS1

BS0

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS6

CS4

A21

VSS

TPUCH8 TPUCH7

TPUCH5

TPUCH3 TPUCH18 TPUCH19 TPUCH16

QSPI_

CLK

BS2

QSPI_

CS1

U1RTS

CS3

CS1

A23

A20

A19

TPUCH10 TPUCH9 TPUCH25 TPUCH24 TPUCH22 TPUCH20

I2C_SDA/

U2RXD

QSPI_

DIN

BS3

SD_CKE U1CTS

CS7

CS5

A22

A18

A17

TPUCH12 TPUCH11 TPUCH27 TPUCH26 TPUCH23 TPUCH21

I2C_SCL/

U2TXD

QSPI_

DOUT

QSPI_

CS0

U2RXD/

CAN1RX

U2TXD/

CAN1TX

CS2

CS0

A14

A15

A16

TPUCH14 TPUCH13 TPUCH29 TPUCH28

VSS

OVDD

VSS

A10

A11

A12

A13

TCRCLK TPUCH15 TPUCH31 TPUCH30

OVDD

VSS

OVDD

VSS

OVDD

VSS

U0CTS

U0RXD

DT0OUT

DT0IN

OVDD

VSS

OVDD

VDD

U0TXD

U0RTS

OVDD

VSS

OVDD

VSS

CLK

MOD0

CLK

MOD1

TEST

OVDD

VSS

OVDD

UTPU

ODIS

LTPU
ODIS

DT3IN

DT3OUT J

D28

D29

D30

D31

OVDD

VSS

OVDD

TEA

TIP

D24

D25

D26

D27

OVDD

VSS

OVDD

VSS

OVDD

SD_WE

I2C_SCL/

CAN0TX

I2C_SDA/

CAN0RX

R/W

D21

D22

D23

VSS

OVDD

VSS

SD_
CS0

SD_

SRAS

SD_

SCAS

CLKOUT M

D19

D20

D13

TSIZ1

IRQ5

IRQ1

TRST/

DSCLK

PST0

JTAG_

DDATA3 SD_CS1

VSS

D17

D18

D12

DT1IN

TSIZ0

IRQ4

DT2IN

TMS/

BKPT

PST1

RCON

DDATA2 VDDPLL

EXTAL P

D16

D15

D11

DT1OUT

IRQ7

IRQ3

DT2OUT

TDO/

DSO

PST2

DDATA0

PLL_

TEST

VSSPLL

XTAL

VSS

D14

D10

VDD

VSS

IRQ6

IRQ2

TCLK/

PSTCLK

TDI/DSI

PST3

DDATA1 RSTOUT RESET

VSS

Mechanicals/Pinouts and Part Numbers

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Figure 5. MCF5234CVMxxx Pinout (256 MAPBGA)

VSS

TPUCH6

TPUCH4

TPUCH2

ETXD1

TPUCH1

TPUCH0

VDD

BS1

BS0

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS6

CS4

A21

VSS

TPUCH8 TPUCH7

TPUCH5

TPUCH3

ETXD2

ETXD3

ETXD0

QSPI_

CLK

BS2

QSPI_

CS1

U1RTS

CS3

CS1

A23

A20

A19

TPUCH10 TPUCH9

ERXD1

ERXD0

ETXCLK

ETXER

EMDIO

QSPI_

DIN

BS3

SD_CKE U1CTS

CS7

CS5

A22

A18

A17

TPUCH12 TPUCH11

ERXD3

ERXD2

ERXER

ETXEN

EMDC

QSPI_

DOUT

QSPI_

CS0

U2RXD U2TXD

CS2

CS0

A14

A15

A16

TPUCH14 TPUCH13 ERXCLK

ERXDV

VSS

OVDD

VSS

A10

A11

A12

A13

TCRCLK TPUCH15

ECOL

ECRS

OVDD

VSS

OVDD

VSS

OVDD

VSS

U0CTS

U0RXD

DT0OUT

DT0IN

OVDD

VSS

OVDD

VDD

U0TXD

U0RTS

OVDD

VSS

OVDD

VSS

CLK

MOD0

CLK

MOD1

TEST

OVDD

VSS

OVDD

UTPU

ODIS

LTPU
ODIS

DT3IN

DT3OUT J

D28

D29

D30

D31

OVDD

VSS

OVDD

TEA

TIP

D24

D25

D26

D27

OVDD

VSS

OVDD

VSS

OVDD

SD_WE

I2C_SCL/

CAN0TX

I2C_SDA/

CAN0RX

R/W

D21

D22

D23

VSS

OVDD

VSS

SD_CS0

SD_

SRAS

SD_

SCAS

CLKOUT M

D19

D20

D13

TSIZ1

IRQ5

IRQ1

TRST/

DSCLK

PST0

JTAG_

DDATA3 SD_CS1

VSS

D17

D18

D12

DT1IN

TSIZ0

IRQ4

DT2IN

TMS/

BKPT

PST1

RCON

DDATA2 VDDPLL

EXTAL P

D16

D15

D11

DT1OUT

IRQ7

IRQ3

DT2OUT

TDO/

DSO

PST2

DDATA0

PLL_

TEST

VSSPLL

XTAL

VSS

D14

D10

VDD

VSS

IRQ6

IRQ2

TCLK/

PSTCLK

TDI/DSI

PST3

DDATA1

RST

OUT

RESET

VSS

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Mechanicals/Pinouts and Part Numbers

Freescale Semiconductor

Figure 6. MCF5235CVMxxx Pinout (256 MAPBGA)

VSS

TPUCH6 TPUCH4

TPUCH2

TPUCH17/

ETXD1

TPUCH1

TPUCH0

VDD

BS1

BS0

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS6

CS4

A21

VSS

TPUCH8 TPUCH7 TPUCH5

TPUCH3

TPUCH18/

ETXD2

TPUCH19/

ETXD3

TPUCH16/

ETXD0

QSPI_

CLK

BS2

QSPI_

CS1

U1RTS

CS3

CS1

A23

A20

A19

TPUCH10 TPUCH9

TPUCH25/

ERXD1

TPUCH24/

ERXD0

TPUCH22/

ETXCLK

TPUCH20/

ETXER

I2C_SDA/

U2RXD/

EMDIO

QSPI_

DIN

BS3

SD_CKE U1CTS

CS7

CS5

A22

A18

A17

TPUCH12 TPUCH11

TPUCH27/

ERXD3

TPUCH26/

ERXD2

TPUCH23/

ERXER

TPUCH21/

ETXEN

I2C_SCL/

U2TXD/

EMDC

QSPI_

DOUT

QSPI_

CS0

U2RXD/

CAN1RX

U2TXD/

CAN1TX

CS2

CS0

A14

A15

A16

TPUCH14 TPUCH13

TPUCH29/

ERXCLK

TPUCH2/

ERXDV

VSS

OVDD

VSS

A10

A11

A12

A13

TCRCLK TPUCH15

TPUCH31/

ECOL

TPUCH30/

ECRS

OVDD

VSS

OVDD

VSS

OVDD

VSS

U0CTS

U0RXD

DT0OUT

DT0IN

OVDD

VSS

OVDD

VDD

U0TXD

U0RTS

OVDD

VSS

OVDD

VSS

CLK

MOD0

CLK

MOD1

TEST

OVDD

VSS

OVDD

UTPU

ODIS

LTPU
ODIS

DT3IN

DT3OUT J

D28

D29

D30

D31

OVDD

VSS

OVDD

TEA

TIP

D24

D25

D26

D27

OVDD

VSS

OVDD

VSS

OVDD

SD_WE

I2C_SCL/

CAN0TX

I2C_SDA/

CAN0RX

R/W

D21

D22

D23

eTPU/

EthENB

VSS

OVDD

VSS

SD_CS0

SD_

SRAS

SD_

SCAS

CLKOUT M

D19

D20

D13

TSIZ1

IRQ5

IRQ1

TRST/

DSCLK

PST0

JTAG_

DDATA3 SD_CS1

VSS

D17

D18

D12

DT1IN

TSIZ0

IRQ4

DT2IN

TMS/

BKPT

PST1

RCON

DDATA2 VDDPLL

EXTAL P

D16

D15

D11

DT1OUT

IRQ7

IRQ3

DT2OUT

TDO/

DSO

PST2

DDATA0

PLL_

TEST

VSSPLL

XTAL

VSS

D14

D10

VDD

VSS

IRQ6

IRQ2

TCLK/

PSTCLK

TDI/DSI

PST3

DDATA1 RSTOUT RESET

VSS

Mechanicals/Pinouts and Part Numbers

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

5.2.2

Package Dimensions--256 MAPBGA

Figure 7

shows MCF5235CVMxxx, MCF5234CVMxxx, and MCF5233CVMxx package dimensions.

Figure 7. 256 MAPBGA Package Outline

LASER MARK FOR PIN A1

IDENTIFICATION IN

THIS AREA

0.20

METALIZED MARK FOR

PIN A1 IDENTIFICATION

IN THIS AREA

15X

256X

0.25

0.10

DETAIL K

VIEW M-M

ROTATED 90 CLOCKWISE

0.15

0.30

256X

NOTES:
1.

DIMENSIONS ARE IN MILLIMETERS.

INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.

DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.

DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.

DIM

MIN

MAX

MILLIMETERS

1.25

1.60

0.27

0.47

1.16 REF

0.40

0.60

17.00 BSC

1.00 BSC

0.50 BSC

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Mechanicals/Pinouts and Part Numbers

Freescale Semiconductor

5.3

Pinout--160 QFP

Figure 8

shows a pinout of the MCF5232CABxxx package.

Figure 8. MCF5232CABxxx Pinout (160 QFP)

1
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

VSS

UCH

VSS

UCH

QSP

I
_DOUT

QSP

I
_DIN

QSP

I
_C

QSP

I
_CS0

OVDD

VSS

\OVS

BS3

BS2

BS1

BS0

\QS

PI_

OVDD

VSS

D\CA

N0R

1
T

OVDD

VSS

OVDD

VSS

A22

A21

A20

A19

A18

A17
A16
A15
A14
A13
A12
OVDD
VSS
A11
A10
A9
A8
A7
A6
A5
OVDD
VSS/OVSS
VDD
A4
A3
A2
A1
A0
TA
R/W
OVDD
VSS
SD_WE
SD_SCAS
SD_SRAS
OVDD
CLKOUT
VSS
VDDPLL
EXTAL
XTAL
VSSPLL
RESET
RSTOUT/PLL_TEST
OVDD

A23

OVDD

TPUCH8
TPUCH9

TPUCH10
TPUCH11
TPUCH12
TPUCH13

VSS

OVDD

TPUCH14
TPUCH15

TCRCLK

U0RXD

U0TXD

VDD

VSS

OVDD

TEST

CLKMOD1
CLKMOD0

D31
D30
D29
D28

VSS

D27
D26
D25
D24
D23

VSS

OVDD

D22
D21
D20
D19
D18
D17
D16

VSS

OVDD

D15

D14

D13

D12

D10

S\O

VSS

OVDD

IRQ7

IRQ4

IRQ1

\PSTC

L
K

OVDD

TRST

\DSCL

\
BK

TDO/DSO

I
/
DSI

PST0

PST1

PST2

PST3

RCON

MCF5232

Mechanicals/Pinouts and Part Numbers

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

5.4

Package Dimensions--160 QFP

Figure 9

shows MCF5232CAB80 package dimensions.

Figure 9. 160 QFP Package Dimensions

TOP &

BOTTOM

Case 864A-03

BASE

METAL

SECTION BB

DETAIL C

C

H

A, B, D

DETAIL A

A

B

H

DETAIL C

MILLIMETERS

INCHES

DIM MIN

MAX

MIN

MAX

A
B
C

D
E
F
G

H
J
K
L
M
N
P
Q
R

T
U
V
W
X

Y
Z

27.90

28.10 1.098 1.106

27.90

28.10 1.098 1.106

3.35

3.85 0.132 1.106

3.35

3.85

0.009 0.015

0.22

0.38

0.009 0.013

0.22

0.33

0.126 0.138

3.20

3.50

0.65 BSC

0.026 REF

0.010 0.014

0.25

0.35

0.004 0.009

0.11

0.23

0.028 0.035

0.70

0.90

25.35 BSC

0.998 REF

0.004 0.007

0.11

0.19

0.325 BSC

0.013 REF

0.005 0.012

0.13

0.30

0.005

0.13

31.00

31.40 1.220 1.236

31.00

31.40 1.220 1.236

0.016

0.4

1.60 REF

0.063 REF

1.33 REF

0.052 REF

1.33 REF

0.052 REF

NOTES

1. DIMENSIONING AND TOLERINCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER

3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT

DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.

0.110 (0.004)

A-B

0.13 (0.005) M

0.20 (0.008)

A-B

0.20 (0.008)

A-B

0.20 (0.008)

A-B

A-

0
.
20 (0.008)

0.20 (

.008)

0.20 (0.0

08)

A-

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

5.5

Ordering Information

Preliminary Electrical Characteristics

This chapter contains electrical specification tables and reference timing diagrams for the MCF5235
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5235.

The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this processor document supersede any values
found in the module specifications.

6.1

Maximum Ratings

Table 25. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5232CAB80

MCF5232 RISC Microprocessor, 160 QFP

80MHz

to +85

MCF5232CVM100

MCF5232 RISC Microprocessor, 196 MAPBGA

100MHz

to +85

MCF5232CVM150

MCF5232 RISC Microprocessor, 196 MAPBGA

150MHz

to +85

MCF5233CVM100

MCF5233 RISC Microprocessor, 256 MAPBGA

100MHz

to +85

MCF5233CVM150

MCF5233 RISC Microprocessor, 256 MAPBGA

150MHz

to +85

MCF5234CVM100

MCF5234 RISC Microprocessor, 256 MAPBGA

100MHz

to +85

MCF5234CVM150

MCF5234 RISC Microprocessor, 256 MAPBGA

150MHz

to +85

MCF5235CVM100

MCF5235 RISC Microprocessor, 256 MAPBGA

100MHz

to +85

MCF5235CVM150

MCF5235 RISC Microprocessor, 256 MAPBGA

150MHz

to +85

Table 26. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

Core Supply Voltage

0.5 to +2.0

Pad Supply Voltage

0.3 to +4.0

Clock Synthesizer Supply Voltage

DDPLL

0.3 to +4.0

Digital Input Voltage

0.3 to + 4.0

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

6.2

Thermal Characteristics

Table 27

lists thermal resistance values

Instantaneous Maximum Current
Single pin limit (applies to all pins)

3,4,5

Operating Temperature Range (Packaged)

- T

)

40 to 85

°C

Storage Temperature Range

stg

65 to 150

°C

NOTES:

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum
Ratings are stress ratings only, and functional operation at the maxima is not guaranteed.
Continued operation at these levels may affect device reliability or cause permanent damage
to the device.

This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either V

or OV

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.

All functional non-supply pins are internally clamped to V

and OV

Power supply must maintain regulation within operating OV

range during instantaneous

and operating maximum current conditions. If positive injection current (V

> OV

) is greater

than I

, the injection current may flow out of OV

and could result in external power supply

going out of regulation. Insure external OV

load will shunt current greater than maximum

injection current. This will be the greatest risk when the processor is not consuming power
(ex; no clock).Power supply must maintain regulation within operating OV

range during

instantaneous and operating maximum current conditions.

Table 27. Thermal Characteristics

Characteristic

Symbol

256

MAPBGA

196

MAPBGA

160QFP

Unit

Junction to ambient, natural convection

Four layer board (2s2p)

JMA

1,2

3,4

5,6

°C / W

Junction to ambient (@200 ft/min)

Four layer board (2s2p)

JMA

°C / W

Junction to board

°C / W

Junction to case

°C / W

Junction to top of package

,13

,14

,15

°C / W

Maximum operating junction temperature

TBD

Table 26. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

NOTES:

JMA

and

parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of

JmA

and power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer's system using the

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

JMA

and

parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of

JmA

and power dissipation specifications in the system design to prevent device junction

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

JMA

and

parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of

JmA

and power dissipation specifications in the system design to prevent device junction

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.

The average chip-junction temperature (T

) in

°C can be obtained from:

(1)

Where:

= Ambient Temperature,

°C

JMA

= Package Thermal Resistance, Junction-to-Ambient,

°C/W

= P

INT

+ P

I/O

INT

= I

× V

, Watts - Chip Internal Power

JMA

(

)

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

6.3

DC Electrical Specifications

I/O

= Power Dissipation on Input and Output Pins -- User Determined

For most applications P

I/O

< P

INT

and can be ignored. An approximate relationship between P

and T

(if P

I/O

is neglected) is:

(2)

Solving equations 1 and 2 for K gives:

K = P

× (T

+ 273

°C) +

JMA

× P

(3)

where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring P

(at equilibrium) for a known T

. Using this value of K, the values of P

and

can be obtained by solving equations (1) and (2) iteratively for any value of T

Table 28. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

1.35

1.65

Pad Supply Voltage

3.6

Input High Voltage

0.7

3.65

Input Low Voltage

0.3

0.35

Input Hysteresis

HYS

0.06

Input Leakage Current

= V

or V

, Input-only pins

1.0

µA

High Impedance (Off-State) Leakage Current

= V

or V

, All input/output and output pins

1.0

µA

Output High Voltage (All input/output and all output pins)
I

= 5.0 mA

- 0.5

Output Low Voltage (All input/output and all output pins)
I

= 5.0mA

0.5

Weak Internal Pull Up Device Current, tested at V

Max.

APU

130

µA

Input Capacitance

All input-only pins
All input/output (three-state) pins

--
--

7
7

273

°C

(

)

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

6.4

Oscillator and PLLMRFM Electrical Characteristics

Load Capacitance

Low drive strength
High drive strength

25
50

Core Operating Supply Current

Master Mode

TBD

Pad Operating Supply Current

Master Mode
Low Power Modes

--
--

TBD
TBD

µA

DC Injection Current

6, 7, 8

NEGCLAMP

0.3 V, V

POSCLAMP

= V

+ 0.3

Single Pin Limit
Total processor Limit, Includes sum of all stressed pins

1.0

NOTES:

Refer to Table 29 for additional PLL specifications.

Refer to the MCF5235 signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination. See High Speed Signal
Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines.

Current measured at maximum system clock frequency, all modules active, and default drive strength with matching
load.

All functional non-supply pins are internally clamped to V

and their respective V

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

Power supply must maintain regulation within operating V

range during instantaneous and operating maximum

current conditions. If positive injection current (V

> V

) is greater than I

, the injection current may flow out of V

and could result in external power supply going out of regulation. Insure external V

load will shunt current greater

than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples
are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at
power-up, system clock is not present during the power-up sequence until the PLL has attained lock.

Table 29. HiP7 PLLMRFM Electrical Specifications

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

PLL Reference Frequency Range

Crystal reference
External reference
1:1 mode (NOTE: f

sys/2

= 2

× f

ref_1:1

)

ref_crystal

ref_ext

ref_1:1

8
8

25
25
75

MHz

Core frequency
CLKOUT Frequency

External reference
On-Chip PLL Frequency

sys

sys/2

ref

÷ 32

150

75
75

MHz
MHz
MHz

Loss of Reference Frequency

3, 5

LOR

100

1000

kHz

Self Clocked Mode Frequency

4, 5

SCM

TBD

MHz

Table 28. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Crystal Start-up Time

5, 6

cst

EXTAL Input High Voltage

Crystal Mode

All other modes (Dual Controller (1:1),

Bypass, External)

IHEXT

TBD
TBD

V
V

EXTAL Input Low Voltage

Crystal Mode

All other modes (Dual Controller (1:1),

Bypass, External)

ILEXT

TBD
TBD

V
V

XTAL Output High Voltage

= 1.0 mA

TBD

XTAL Output Low Voltage

= 1.0 mA

TBD

XTAL Load Capacitance

PLL Lock Time

5, 8,14

lpll

750

µs

Power-up To Lock Time

5, 6,9

With Crystal Reference (includes 5 time)
Without Crystal Reference

lplk

--
--

750

µs

1:1 Mode Clock Skew (between CLKOUT
and EXTAL)

skew

Duty Cycle of reference

Frequency un-LOCK Range

3.8

4.1

% f

sys/2

Frequency LOCK Range

LCK

1.7

2.0

sys/2

CLKOUT Period Jitter,

5, 6, 9,12, 13

Measured at f

sys/2

Max

Peak-to-peak Jitter (Clock edge to clock

edge)

Long Term Jitter (Averaged over 2 ms

interval)

jitter

--
--

5.0
.01

% f

sys/2

Frequency Modulation Range Limit

sys/2

Max must not be exceeded)

mod

0.8

2.2

sys/2

ICO Frequency. f

ico

= f

ref

(MFD+2)

ico

MHz

NOTES:

All values given are initial design targets and subject to change.

All internal registers retain data at 0 Hz.

"Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL
into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls
below f

LOR

with default MFD/RFD settings.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This parameter is guaranteed by design rather than 100% tested.

Table 29. HiP7 PLLMRFM Electrical Specifications

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

6.5

External Interface Timing Characteristics

Table 30

lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.

All other timing relationships can be derived from these values.

This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).

Assuming a reference is available at power up, lock time is measured from the time V

and V

DDSYN

are

valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.

lpll

= (64

5 + 5

)

ref

, where T

ref

= 1/F

ref_crystal

= 1/F

ref_ext

= 1/F

ref_1:1

, and

= 1.57x10

-6

2(MFD + 2).

PLL is operating in 1:1 PLL mode.

Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum f

sys/2

. Measurements are made with the device powered by filtered supplies and clocked by a

stable external clock signal. Noise injected into the PLL circuitry via V

DDSYN

and V

SSSYN

and variation in

crystal oscillator frequency increase the Cjitter percentage for a given interval.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.

Modulation percentage applies over an interval of 10

µs, or equivalently the modulation rate is 100KHz.

Modulation rate selected must not result in f

sys/2

value greater than the f

sys/2

maximum specified value.

Modulation range determined by hardware design.

sys/2

= f

ico

/ (2

RFD

)

Table 30. Processor Bus Input Timing Specifications

Name

Characteristic

NOTES:

Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
environment..

Symbol

Min

Max

Unit

freq

System bus frequency

sys/2

MHz

CLKOUT period

cyc

1/50

Control Inputs

B1a

Control input valid to CLKOUT high

TEA and TA pins are being referred to as control inputs.

CVCH

B1b BKPT valid to CLKOUT high

Refer to figure A-19.

BKVCH

B2a

CLKOUT high to control inputs invalid

CHCII

B2b

CLKOUT high to asynchronous control input BKPT invalid

BKNCH

Data Inputs

Data input (D[31:0]) valid to CLKOUT high

DIVCH

CLKOUT high to data input (D[31:0]) invalid

CHDII

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Timings listed in

Table 30

are shown in

Figure 10

& Figure A-3.

Figure 10. General Input Timing Requirements

6.6

Processor Bus Output Timing Specifications

Table 31

lists processor bus output timings.

Table 31. External Bus Output Timing Specifications

Name

Characteristic

Symbol

Min

Max

Unit

Control Outputs

B6a

CLKOUT high to chip selects valid

CHCV

0.5t

CYC

B6b

CLKOUT high to byte enables (BS[3:0]) valid

CHBV

0.5t

CYC

B6c

CLKOUT high to output enable (OE) valid

CHOV

0.5t

CYC

CLKOUT high to control output (BS[3:0], OE) invalid

CHCOI

0.5t

CYC

+1.5

B7a

CLKOUT high to chip selects invalid

CHCI

0.5t

CYC

+1.5

Invalid

CLKOUT(75MHz)

SETUP

HOLD

Input Setup And Hold

1.5V

trise

= V

1.5V

1.5V Valid

tfall

= V

Input Rise Time

Input Fall Time

* The timings are also valid for inputs sampled on the negative clock edge.

Inputs

CLKOUT

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Read/write bus timings listed in

Table 31

are shown in

Figure 11

Figure 12

, and

Figure 13

Address and Attribute Outputs

CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) valid

CHAV

CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) invalid

CHAI

1.5

Data Outputs

B11

CLKOUT high to data output (D[31:0]) valid

CHDOV

B12

CLKOUT high to data output (D[31:0]) invalid

CHDOI

1.5

B13

CLKOUT high to data output (D[31:0]) high impedance

CHDOZ

NOTES:

CS transitions after the falling edge of CLKOUT.

BS transitions after the falling edge of CLKOUT.

OE transitions after the falling edge of CLKOUT.

Table 31. External Bus Output Timing Specifications (continued)

Name

Characteristic

Symbol

Min

Max

Unit

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 14. SDRAM Read Cycle

Figure 15

shows an SDRAM write cycle.

Table 32. SDRAM Timing

NUM

Characteristic

Symbol

Min

Max

Unit

CLKOUT high to SDRAM address valid

CHDAV

CLKOUT high to SDRAM control valid

CHDCV

CLKOUT high to SDRAM address invalid

CHDAI

1.5

CLKOUT high to SDRAM control invalid

CHDCI

1.5

SDRAM data valid to CLKOUT high

DDVCH

CLKOUT high to SDRAM data invalid

CHDDI

1.5

NOTES:

D7 and D8 are for write cycles only.

CLKOUT high to SDRAM data valid

CHDDVW

CLKOUT high to SDRAM data invalid

CHDDIW

1.5

A[23:0]

RAS

D[31:0]

ACTV

NOP

PALL

NOP

RAS[1:0]

READ

Column

SD_CKE

SDWE

CAS[3:0]

DACR[CASL] = 2

CAS

NOP

Row

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 16. GPIO Timing

6.8

Reset and Configuration Override Timing

Table 34. Reset and Configuration Override Timing

= 2.7 to 3.6 V, V

= 0 V, T

= T

to T

)

NOTES:

All AC timing is shown with respect to 50% V

levels unless otherwise noted.

NUM

Characteristic

Symbol

Min

Max

Unit

RESET Input valid to CLKOUT High

RVCH

CLKOUT High to RESET Input invalid

CHRI

1.5

RESET Input valid Time

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the
system. Thus, RESET must be held a minimum of 100 ns.

RIVT

CYC

CLKOUT High to RSTOUT Valid

CHROV

RSTOUT valid to Config. Overrides valid

ROVCV

Configuration Override Setup Time to RSTOUT invalid

COS

CYC

Configuration Override Hold Time after RSTOUT invalid

COH

RSTOUT invalid to Configuration Override High Impedance

ROICZ

CYC

CLKOUT

GPIO Outputs

GPIO Inputs

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Figure 17. RESET and Configuration Override Timing

* Refer to the Coldfire Integration Module (CIM) section for more information.

6.9

C Input/Output Timing Specifications

Table 35

lists specifications for the I

C input timing parameters shown in

Figure 18

Table 36

lists specifications for the I

C output timing parameters shown in

Figure 18

Table 35. I

C Input Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

cyc

Clock low period

cyc

I2C_SCL/I2C_SDA rise time (V

= 0.5 V to V

= 2.4 V)

Data hold time

I2C_SCL/I2C_SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

cyc

Data setup time

Start condition setup time (for repeated start condition only)

cyc

Stop condition setup time

cyc

Table 36. I

C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

cyc

Clock low period

cyc

I2C_SCL/I2C_SDA rise time (V

= 0.5 V to

= 2.4 V)

µs

Data hold time

cyc

I2C_SCL/I2C_SDA fall time (V

= 2.4 V to

= 0.5 V)

Clock high time

cyc

CLKOUT

RESET

RSTOUT

Configuration Overrides*:

(RCON, Override pins])

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 18

shows timing for the values in

Table 35

and

Table 36

Figure 18. I

C Input/Output Timings

6.10 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

6.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and

ERXCLK)

The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.

Table 37

lists MII receive channel timings.

Data setup time

cyc

Start condition setup time (for repeated start
condition only)

cyc

Stop condition setup time

cyc

NOTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR
programmed with the maximum frequency (IFDR = 0x20) results in minimum output
timings as shown in

Table 36

. The I

C interface is designed to scale the actual data

transition time to move it to the middle of the I2C_SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the
numbers given in

Table 36

are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can
only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on
external signal capacitance and pull-up resistor values.

Specified at a nominal 50-pF load.

Table 36. I

C Output Timing Specifications between I2C_SCL and I2C_SDA

Num

Characteristic

Min

Max

Units

I2C_SCL

I2C_SDA

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Figure 19

shows MII receive signal timings listed in

Table 37

Figure 19. MII Receive Signal Timing Diagram

6.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN,

ETXER, ETXCLK)

Table 38

lists MII transmit channel timings.

The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ETXCLK frequency.

The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the
rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use
of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 37. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

ERXD[3:0], ERXDV, ERXER to ERXCLK setup

ERXCLK to ERXD[3:0], ERXDV, ERXER hold

ERXCLK pulse width high

35%

65%

ERXCLK period

ERXCLK pulse width low

35%

65%

ERXCLK period

Table 38. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

ETXCLK to ETXD[3:0], ETXEN, ETXER invalid

ETXCLK to ETXD[3:0], ETXEN, ETXER valid

ETXCLK pulse width high

35%

65%

ETXCLK period

ETXCLK pulse width low

35%

65%

ETXCLK period

ERXCLK (input)

ERXD[3:0] (inputs)

ERXDV
ERXER

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 20

shows MII transmit signal timings listed in

Table 38

Figure 20. MII Transmit Signal Timing Diagram

6.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)

Table 39

lists MII asynchronous inputs signal timing.

Figure 21

shows MII asynchronous input timings listed in

Table 39

Figure 21. MII Async Inputs Timing Diagram

6.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)

Table 40

lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 39. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

ECRS, ECOL minimum pulse width

1.5

ETXCLK period

Table 40. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

EMDC falling edge to EMDIO output invalid (minimum propagation
delay)

M11

EMDC falling edge to EMDIO output valid (max prop delay)

M12

EMDIO (input) to EMDC rising edge setup

M13

EMDIO (input) to EMDC rising edge hold

M14

EMDC pulse width high

40%

60%

MDC period

M15

EMDC pulse width low

40%

60%

MDC period

ETXCLK (input)

ETXD[3:0] (outputs)

ETXEN

ETXER

ECRS, ECOL

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Figure 22

shows MII serial management channel timings listed in

Table 40

Figure 22. MII Serial Management Channel Timing Diagram

6.11 32-Bit Timer Module AC Timing Specifications

Table 41

lists timer module AC timings.

6.12 QSPI Electrical Specifications

Table 42

lists QSPI timings.

Table 41. Timer Module AC Timing Specifications

Name

Characteristic

066 MHz

Unit

Min

Max

DT0IN / DT1IN / DT2IN / DT3IN cycle time

CYC

DT0IN / DT1IN / DT2IN / DT3IN pulse width

CYC

Table 42. QSPI Modules AC Timing Specifications

Name

Characteristic Min

Max

Unit

QS1

QSPI_CS[1:0] to QSPI_CLK

510

tcyc

QS2

QSPI_CLK high to QSPI_DOUT valid.

QS3

QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QS4

QSPI_DIN to QSPI_CLK (Input setup)

QS5

QSPI_DIN to QSPI_CLK (Input hold)

M11

EMDC (output)

EMDIO (output)

M12

M13

EMDIO (input)

M10

M14

M15

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

The values in

Table 42

correspond to

Figure 23

Figure 23. QSPI Timing

6.13 JTAG and Boundary Scan Timing

Table 43. JTAG and Boundary Scan Timing

Num

Characteristics

NOTES:

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Symbol

Min

Max

Unit

TCLK Frequency of Operation

JCYC

1/4

sys/2

TCLK Cycle Period

JCYC

CYC

TCLK Clock Pulse Width

JCW

TCLK Rise and Fall Times

JCRF

Boundary Scan Input Data Setup Time to TCLK Rise

BSDST

Boundary Scan Input Data Hold Time after TCLK Rise

BSDHT

TCLK Low to Boundary Scan Output Data Valid

BSDV

TCLK Low to Boundary Scan Output High Z

BSDZ

TMS, TDI Input Data Setup Time to TCLK Rise

TAPBST

J10

TMS, TDI Input Data Hold Time after TCLK Rise

TAPBHT

J11

TCLK Low to TDO Data Valid

TDODV

J12

TCLK Low to TDO High Z

TDODZ

J13

TRST Assert Time

TRSTAT

100

J14

TRST Setup Time (Negation) to TCLK High

TRSTST

QSPI_CS[1:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3

QS4

QS2

Preliminary Electrical Characteristics

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Freescale Semiconductor

Figure 28

shows real-time trace timing for the values in

Table 44

Figure 28. Real-Time Trace AC Timing

Figure 29

shows BDM serial port AC timing for the values in

Table 44

Figure 29. BDM Serial Port AC Timing

DE5

DSCLK high to DSO invalid

cyc

DE6

BKPT input data setup time to
CLKOUT Rise

DE7

CLKOUT high to BKPT high Z

NOTES:

DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.

Table 44. Debug AC Timing Specification

Num

Characteristic

150 MHz

Units

Min

Max

PSTCLK

PST[3:0]

DE2

DE1

DDATA[3:0]

DE0

DSI

DSO

Current

CLKOUT

Past

Current

DSCLK

DE3

DE4

DE5

BKPT

DE6

DE7

MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3

Preliminary

Documentation

Freescale Semiconductor

Documentation

Table 46

lists the documents that provide a complete description of the MCF523x and their development

support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor
sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address
at

http://www.freescale.com

7.1

Document Revision History

Table 46

provides a revision history for this document.

Table 45. MCF523x Documentation

Freescale

Document

Number

Title

Revision

Status

MCF5235EC

MCF5235 RISC Microprocessor Hardware

Specifications

Rev. 1.3

This document

MCF5235RM

MCF523x Reference Manual

Available

MCF5235PB

MCF523x Product Brief

Available

MCF523xFS

MCF523x Fact Sheet

In Process

eTPURM/D

eTPU User Manual

Available

CFPRODFACT/D

The ColdFire Family of 32-Bit Microprocessors

Family Overview and Technology Roadmap

Available under

NDA

MCF5xxxWP

MCF5xxxWP WHITE PAPER: Motorola ColdFire

VL RISC Processors

Available under

NDA

MAPBGAPP

MAPBGA 4-Layer Example

Available

CFPRM/D

ColdFire Family Programmer's Reference Manual

Available

Table 46. Document Revision History

Rev. No.

Substantive Change(s)

Preliminary release.

-Updated Signal List table

1.1

-Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.

1.2

-Corrected

Figure 8

pin 81. VDD instead of VSS

-Changed instances of Motorola to Freescale

1.3

-Removed detailed signal description section. This information can be found in the MCF5235RM
Chapter 2.
-Removed detailed feature list. This information can be found in the MCF5235RM Chapter 1.
-Corrected

Figure 2

pin F10. VSS instead of VDD. Change made in

Table 2

as well.

-Corrected

Figure 8

pin 81. OVDD instead of VDD. Change made in

Table 2

as well.

-Cleaned up many inconsistencies within the pinout figure signal names
-Corrected document IDs in

Table 45

MCF5235EC
Rev. 1.3, 10/2004

HOW TO REACH US:

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Freescale Semiconductor Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
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Technical Information Center
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81-3-3440-3569

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© Freescale Semiconductor, Inc. 2004.

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