· Preliminary

Freescale Semiconductor
Data Sheet: Advance Information

MCF5373DS

Rev. 0.3, 04/2006

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

Table of Contents

The MCF537x devices are a family of highly-integrated
32-bit microprocessors based on the Version 3 ColdFire
microarchitecture. All MCF537x devices contain a
32-Kbyte internal SRAM, a Fast Ethernet controller, a
2-bank SDR/DDR SDRAM controller, a 16-channel
DMA controller, up to three UARTs, a queued SPI, as
well as other peripherals that enable the MCF537x
family for use in general purpose industrial control
applications. Optional peripherals include USB host and
On-the-Go controllers and cryptography hardware
accelerators.

This document provides an overview of the MCF537x
microprocessor family, focusing on its highly diverse
feature set. It was written from the perspective of the
MCF5373L device. However, it also pertains to the
MCF5372L, MCF5372, and MCF5373. See the
following section for a summary of differences between
the various devices of the MCF537x family.

MCF5373 ColdFire

Microprocessor Data Sheet

Supports MCF5372L, MCF5372, MCF5373L, & MCF5373

by: Microcontroller Division

MCF537x Family Configurations ......................... 2

Ordering Information ........................................... 3

Signal Descriptions.............................................. 3

Mechanicals and Pinouts .................................... 8

Preliminary Electrical Characteristics ................ 14

Revision History ................................................ 40

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

MCF537x Family Configurations

Freescale Semiconductor

MCF537x Family Configurations

The following table compares the various device derivatives available within the MCF537x family.

Table 1. MCF537x Family Configurations

Module

MCF5372 MCF5372L MCF5373 MCF5373L

ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)

Core (System) Clock

up to

180 MHz

up to

240 MHz

up to

180 MHz

up to

240 MHz

Peripheral and External Bus Clock
(Core clock

÷ 3)

up to

60 MHz

up to

80 MHz

up to

60 MHz

up to

80 MHz

Performance (Dhrystone/2.1 MIPS)

up to 158

up to 211

up to 158

up to 211

Instruction/Data Cache

16 Kbytes

Static RAM (SRAM)

32 Kbytes

SDR/DDR SDRAM Controller

USB 2.0 Host

USB 2.0 On-the-Go

Synchronous Serial Interface (SSI)

Fast Ethernet Controller (FEC)

Cryptography Hardware Accelerators

UARTs

QSPI

PWM Module

Real Time Clock

32-bit DMA Timers

Watchdog Timer (WDT)

Periodic Interrupt Timers (PIT)

Edge Port Module (EPORT)

Interrupt Controllers (INTC)

16-channel Direct Memory Access (DMA)

FlexBus External Interface

General Purpose I/O (GPIO)

up to 46

up to 62

up to 46

up to 62

JTAG - IEEE

1149.1 Test Access Port

Package

160 QFP

196

MAPBGA

160 QFP

196

MAPBGA

Ordering Information

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Ordering Information

Signal Descriptions

The following table lists all the MCF537x pins grouped by function. The "Dir" column is the direction for
the primary function of the pin only. Refer to

Section 4, "Mechanicals and Pinouts,"

for package diagrams.

For a more detailed discussion of the MCF537x signals, consult the MCF5373 Reference Manual
(MCF5373RM).

NOTE

In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A23), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. Orderable Part Numbers

Freescale Part

Number

Description

Speed

Temperature

MCF5372CAB180

MCF5372 RISC Microprocessor, 160 QFP

180 MHz

to +85

MCF5372LCVM240

MCF5372 RISC Microprocessor, 196 MAPBGA

240 MHz

to +85

MCF5373CAB180

MCF5373 RISC Microprocessor, 160 QFP

180 MHz

to +85

MCF5373LCVM240

MCF5373 RISC Microprocessor, 256 MAPBGA

240 MHz

to +85

Table 3. MCF5372/3 Signal Information and Muxing

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

Reset

RESET

K13

RSTOUT

L12

Clock

EXTAL

L14

XTAL

K14

EXTAL32K

P13

XTAL32K

N13

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Signal Descriptions

Freescale Semiconductor

FB_CLK

Mode Selection

RCON

DRAMSEL

J11

FlexBus

A[23:22]

FB_CS[5:4]

134, 133

A9, B9

A[21:16]

132127

C9, D9, A10,

B10, C10, D10

A[15:14]

SD_BA[1:0]

126, 123

A11, B11

A[13:11]

SD_A[13:11]

120118

C11, A12, B12

A10

11 A13

A[9:0]

SD_A[9:0]

116107

A14, B14, B13,

C12, D11, C14,

C13, D14D12

D[31:16]

SD_D[31:16]

2734, 4653

J2, J1, K4K1,

L4, L3, N2, P1,

P2, N3, L5, P3,

N4, P4

D[15:1]

FB_D[31:17]

1623, 5763

F2, F1, G4G1,
H4, H3, L6, M6,
N6, P6, L7, M7,

FB_D[16]

BE/BWE[3:0]

PBE[3:0]

SD_DQM[3:0]

26, 54, 24, 56

J3, M5, H2, P5

PBUSCTL3

PBUSCTL2

106

E14

R/W

PBUSCTL1

PBUSCTL0

DACK0

Chip Selects

FB_CS[5:4]

PCS[5:4]

D8, C8

FB_CS[3:2]

PCS[3:2]

B8, A8

FB_CS1

PCS1

135

FB_CS0

136

SDRAM Controller

SD_A10

SD_CKE

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

Signal Descriptions

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

SD_CLK

SD_CS0

SD_DQS3

SD_DQS2

SD_SCAS

SD_SRAS

SD_SDR_DQS

SD_WE

External Interrupts Port

IRQ7

PIRQ7

102

F13

IRQ6

PIRQ6

USBHOST_

VBUS_EN

F12

IRQ5

PIRQ5

USBHOST_

VBUS_OC

F11

IRQ4

PIRQ4

SSI_MCLK

101

G14

IRQ3

PIRQ3

G13

IRQ2

PIRQ2

USB_CLKIN

G12

IRQ1

PIRQ1

DREQ1

SSI_CLKIN

100

G11

FEC

FEC_MDC

PFECI2C3

I2C_SCL

FEC_MDIO

PFECI2C2

I2C_SDA

I/O

FEC_COL

PFECH7

144

FEC_CRS

PFECH6

145

FEC_RXCLK

PFECH5

146

FEC_RXDV

PFECH4

147

FEC_RXD[3:0]

PFECH[3:0]

148151

C5, D5, A4, B4

FEC_RXER

PFECL7

152

FEC_TXCLK

PFECL6

153

FEC_TXEN

PFECL5

154

FEC_TXER

PFECL4

155

FEC_TXD[3:0]

PFECL[3:0]

157, 158, 1, 2

D4, C3, B2, C2

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Signal Descriptions

Freescale Semiconductor

USB Host & USB On-the-Go

USBOTG_M

I/O

H14

USBOTG_P

I/O

H13

USBHOST_M

I/O

J13

USBHOST_P

I/O

J12

PWM

PWM7

PPWM7

I/O

E13

PWM5

PPWM5

I/O

E12

PWM3

PPWM3

DT3OUT

DT3IN

I/O

E11

PWM1

PPWM1

DT2OUT

DT2IN

I/O

F14

SSI

The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK,

IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD

I2C_SCL

PFECI2C1

U2TXD

I/O

I2C_SDA

PFECI2C0

U2RXD

I/O

DMA

DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:

TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.

QSPI

QSPI_CS2

PQSPI5

U2RTS

N12

QSPI_CS1

PQSPI4

PWM7

USBOTG_

PU_EN

M12

QSPI_CS0

PQSPI3

PWM5

M11

QSPI_CLK

PQSPI2

I2C_SCL

P12

QSPI_DIN

PQSPI1

U2CTS

P11

QSPI_DOUT

PQSPI0

I2C_SDA

N11

UARTs

U1CTS

PUARTL7

SSI_BCLK

143

U1RTS

PUARTL6

SSI_FS

142

U1TXD

PUARTL5

SSI_TXD

141

U1RXD

PUARTL4

SSI_RXD

140

U0CTS

PUARTL3

M14

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

Signal Descriptions

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

U0RTS

PUARTL2

M13

U0TXD

PUARTL1

N14

U0RXD

PUARTL0

P14

Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins.

DMA Timers

DT3IN

PTIMER3

DT3OUT

U2RXD

DT2IN

PTIMER2

DT2OUT

U2TXD

DT1IN

PTIMER1

DT1OUT

DACK1

DT0IN

PTIMER0

DT0OUT

DREQ0

BDM/JTAG

JTAG_EN

G10

DSCLK

TRST

K11

PSTCLK

TCLK

BKPT

TMS

L13

DSI

TDI

K12

DSO

TDO

L11

DDATA[3:0]

L9, M9, N9, P9

PST[3:0]

L10, M10, N10,

P10

ALLPST

Test

TEST

124

E10

Power Supplies

EVDD

9, 69, 71, 81, 94,

103, 139, 160

E6, E7, F5F7,

G5, H10, J8,

K8K9

IVDD

36, 79, 97, 125,

156

E5, J9, K5, K10

PLL_VDD

J10

SD_VDD

11, 39, 41, 67,

105, 121, 137

E8E9, F8F10,

J4J7, H5, K6,

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Mechanicals and Pinouts

Freescale Semiconductor

Mechanicals and Pinouts

This section contains drawings showing the pinout and the packaging and mechanical characteristics of
the MCF537x devices.

NOTE

The mechanical drawings are the latest revisions at the time of publication
of this document. The most up-to-date mechanical drawings can be found at
the product summary page located at

http://www.freescale.com/coldfire

USBOTG_VDD

H12

VSS

10, 42, 68, 82,

89, 104, 122,

138, 159

G6G9, H6H9

PLL_VSS

H11

USBHOST_VSS

J14

NOTES:

Refers to pin's primary function.

Pull-up enabled internally on this signal for this mode.

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by
negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the
alternate functions.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.

Pull-down enabled internally on this signal for this mode.

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

Dir.

MCF5372
MCF5373

160 QFP

MCF5372L
MCF5373L

196 MAPBGA

Mechanicals and Pinouts

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

4.1

Pinout--196 MAPBGA

The pinout for the MCF5373LCVM240 and MCF5372LCVM240 packages are shown below.

FEC_
MDIO

FEC_

TXER

FEC_

TXCLK

FEC_

RXD1

FEC_

RXCLK

FEC_

CRS

U1TXD

FB_CS2

A23

A19

A15

A12

A10

FEC_

MDC

FEC_
TXD1

FEC_

TXEN

FEC_

RXD0

FEC_

RXDV

FEC_

COL

U1RXD

FB_CS3

A22/

A18

A14

A11

DT2IN

FEC_
TXD0

FEC_
TXD2

FEC_

RXER

FEC_

RXD3

U1CTS

FB_CS0 FB_CS4

A21

A17

A13

DT3IN

DT1IN

DT0IN

FEC_
TXD3

FEC_

RXD2

U1RTS

FB_CS1 FB_CS5

A20

A16

SD_WE

I2C_SCL

I2C_SDA

IVDD

EVDD

SD_VDD SD_VDD

TEST

PWM3

PWM5

PWM7

D14

D15

SD_CS0

SD_CKE

EVDD

SD_VDD SD_VDD SD_VDD

IRQ5

IRQ6

IRQ7

PWM1

D10

D11

D12

D13

EVDD

VSS

JTAG_

IRQ1

IRQ2

IRQ3

IRQ4

SD_

DQS3

BE/

BWE1

SD_VDD

VSS

EVDD

PLL_

VSS

USBOTG

_VDD

USB

OTG_P

USB

OTG_M

D30

D31

BE/

BWE3

SD_VDD SD_VDD SD_VDD SD_VDD

EVDD

IVDD

PLL_

VDD

DRAM

SEL

USB

HOST_P

USB

HOST_M

USBHOST

_VSS

D26

D27

D28

D29

IVDD

SD_VDD SD_VDD

EVDD

IVDD

TRST/

DSCLK

TDI/DSI

RESET

XTAL

SD_CLK

SD_DR_

DQS

D24

D25

D19

R/W

DDATA3

PST3

TDO/

DSO

RSTOUT

TMS/

BKPT

EXTAL

M SD_CLK SD_A10

SD_CAS

SD_RAS

BE/

BWE2

DDATA2

PST2

QSPI_

CS0

QSPI_

CS1

U0RTS

U0CTS

FB_CLK

D23

D20

D17

SD_

DQS2

TCLK/

PSTCLK

DDATA1

PST1

QSPI_

DOUT

QSPI_

CS2

XTAL

32K

U0TXD

D22

D21

D18

D16

BE/

BWE0

RCON

DDATA0

PST0

QSPI_

DIN

QSPI_

CLK

EXTAL

32K

U0RXD

Figure 1. MCF5373LCVM240 Pinout Top View (196 MAPBGA)

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Mechanicals and Pinouts

Freescale Semiconductor

4.2

Package Dimensions--196 MAPBGA

Figure 2

shows the MCF5373LCVM240 and MCF5372LCVM240 package dimensions.

Figure 2. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

0.20

Laser mark for pin 1

identification in

this area

13X

0.15 Z

0.30 Z

Rotated 90 Clockwise

Detail K

View M-M

13X

0.30

0.10 Z

196X

Metalized mark for

pin 1 identification

in this area

14 13 12 11

NOTES:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances

per ASME Y14.5M, 1994.

3. Dimension B is measured at the

maximum solder ball diameter,

parallel to datum plane Z.

4. Datum Z (seating plane) is defined

by the spherical crowns of the solder

balls.

5. Parallelism measurement shall

exclude any effect of mark on top

surface of package.

DIM

Min Max

Millimeters

A 1.32 1.75

A1 0.27 0.47
A2 1.18 REF

b 0.35 0.65

D 15.00 BSC
E 15.00 BSC

1.00 BSC

0.50 BSC

Top View

Bottom View

Mechanicals and Pinouts

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

4.3

Pinout--160 QFP

The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.

Figure 3. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)

EVDD

VSS

C_TXD2

C_TXD3

IVDD

C_TXER

C_TXEN

C_TXCLK

C_RXER

C_RXD0

C_RXD1

C_RXD2

C_RXD3

C_RXDV

C_RXCLK

C_CRS

C_COL

EVDD

VSS

SD_VDD

A23/

FB_CS5

A22/

FB_CS4

A21

A20

A19

A18

A17

A16

A15

IVDD

A14

VSS

SD_VDD

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

FEC_TXD1

120

A13

FEC_TXD0

119

A12

FEC_MDIO

118

A11

FEC_MDC

117

A10

DT0IN

116

DT1IN

115

DT2IN

114

DT3IN

113

EVDD

112

VSS

111

SD_VDD

110

109

SD_WE

108

SD_CKE

107

SD_CS0

106

D15

105

SD_VDD

D14

104

VSS

D13

103

EVDD

D12

102

IRQ7

D11

101

IRQ4

D10

100

IRQ1

PLL_VDD

PLL_VSS

BE/BWE1

IVDD

SD_DQS1/3

JTAG_EN

BE/BWE3

RESET

D31

EVDD

D30

XTAL

D29

DRAMSEL

D28

EXTAL

D27

TDI/DSI

D26

VSS

D25

TRST/DSCLK

D24

TMS/BKPT

SD_DR_DQS

RSTOUT

IVDD

U0CTS

SD_CLK

U0RTS

SD_CLK

U0TXD

SD_VDD

VSS

FB_CLK

EVDD

SD_V

VSS

SD_CAS

SD_RAS

D23

D22

D21

D20

D19

D18

D17

D16

R/W

SD_V

VSS

/
PSTCLK

RCON

L_PS

TDO

/
DSO

SPI

_DI

QSP

I
_DO

SPI

_CLK

SPI

_CS2

U0RX

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Preliminary Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF5373
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5373.

The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this MCU document supersede any values
found in the module specifications.

5.1

Maximum Ratings

Table 4. Absolute Maximum Ratings

NOTES:

Functional operating conditions are given in

Section 5.4, "DC Electrical Specifications."

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.

This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either V

or EV

Rating

Symbol

Value

Unit

Core Supply Voltage

0.5 to +2.0

CMOS Pad Supply Voltage

0.3 to +4.0

DDR/Memory Pad Supply Voltage

SDV

0.3 to +4.0

PLL Supply Voltage

PLLV

0.3 to +2.0

Digital Input Voltage

Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.

0.3 to +3.6

Instantaneous Maximum Current
Single pin limit (applies to all pins)

3, 4, 5

All functional non-supply pins are internally clamped to V

and EV

Operating Temperature Range (Packaged)

- T

)

40 to +85

°C

Storage Temperature Range

stg

55 to +150

°C

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.2

Thermal Characteristics

The average chip-junction temperature (T

) in

°C can be obtained from:

Eqn. 1

Where:

= Ambient Temperature, °C

JMA

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P

INT

+ P

I/O

INT

= I

× IV

, Watts - Chip Internal Power

I/O

= Power Dissipation on Input and Output Pins -- User Determined

Power supply must maintain regulation within operating EV

range during instantaneous

and operating maximum current conditions. If positive injection current (V

> EV

) is greater

than I

, the injection current may flow out of EV

and could result in external power supply

going out of regulation. Insure external EV

load will shunt current greater than maximum

injection current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EV

range during

instantaneous and operating maximum current conditions.

Table 5. Thermal Characteristics

Characteristic

Symbol

256MBGA

196MBGA

160QFP

Unit

Junction to ambient, natural convection

Four layer board
(2s2p)

JMA

1,2

NOTES:

JMA

and

parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

recommends the use of

JmA

and power dissipation specifications in the system design to prevent device junction

temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer's system using the

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

1,2

°C / W

Junction to ambient (@200 ft/min)

Four layer board
(2s2p)

JMA

1,2

°C / W

Junction to board

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.

°C / W

Junction to case

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

°C / W

Junction to top of package

1,5

Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.

1,5

°C / W

Maximum operating junction temperature

105

JMA

(

)

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

For most applications P

I/O

< P

INT

and can be ignored. An approximate relationship between P

and T

(if

I/O

is neglected) is:

Eqn. 2

Solving equations 1 and 2 for K gives:

Eqn. 3

where K is a constant pertaining to the particular part. K can be determined from

Equation 3

by measuring

(at equilibrium) for a known T

. Using this value of K, the values of P

and T

can be obtained by

solving

Equation 1

and

Equation 2

iteratively for any value of T

5.3

ESD Protection

5.4

DC Electrical Specifications

Table 6. ESD Protection Characteristics

NOTES:

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.

Characteristics

Symbol

Value

Units

ESD Target for Human Body Model

HBM

2000

Table 7. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage

1.4

1.6

PLL Supply Voltage

PLLV

1.4

1.6

CMOS Pad Supply Voltage

3.0

3.6

Mobile DDR/Bus Pad Supply Voltage

SDV

1.65

1.95

DDR/Bus Pad Supply Voltage

SDV

2.25

2.75

SDR/Bus Pad Supply Voltage

SDV

3.0

3.6

USB Supply Voltage

USBV

3.0

3.6

CMOS Input High Voltage

+ 0.05

CMOS Input Low Voltage

-0.05

0.8

Mobile DDR/Bus Input High Voltage

SDV

TBD

SDV

+ 0.05

Mobile DDR/Bus Input Low Voltage

SDV

-0.05

TBD

DDR/Bus Input High Voltage

SDV

+ 0.05

DDR/Bus Input Low Voltage

SDV

-0.05

0.8

273

°C

(

)

---------------------------------

273

°C

(

) Q

JMA

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.4.1

PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V

pins.

The filter shown in

Figure 6

should be connected between the board V

and the PLLV

pins. The

resistor and capacitors should be placed as close to the dedicated PLLV

pin as possible.

Figure 6. System PLL V

Power Filter

5.4.2

USB Power Filtering

To minimize noise, external filters are required for each of the USB power pins. The filter shown in

Figure 7

should be connected between the board EV

or IV

and each of the USBV

pins. The

resistor and capacitors should be placed as close to the dedicated USBV

pin as possible.

Input Leakage Current

= V

or V

, Input-only pins

-1.0

1.0

µA

CMOS Output High Voltage

= 5.0 mA

- 0.4

CMOS Output Low Voltage

= 5.0 mA

0.4

DDR/Bus Output High Voltage

= 5.0 mA

SDV

- 0.4

DDR/Bus Output Low Voltage

= 5.0 mA

SDV

0.4

Weak Internal Pull-Up Device Current, tested at V

Max.

APU

-10

-130

µA

Input Capacitance

All input-only pins
All input/output (three-state) pins

--
--

7
7

NOTES:

Refer to the signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

Table 7. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Board V

0.1 µF

PLL V

10 µF

GND

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 7. USB V

Power Filter

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also
recommended in parallel with those shown.

5.4.3

Supply Voltage Sequencing and Separation Cautions

Figure 8

shows situations in sequencing the I/O V

(EV

), SDRAM V

(SDV

), PLL V

(PLLV

), and Core V

(IV

Figure 8. Supply Voltage Sequencing and Separation Cautions

The relationship between SDV

and EV

is non-critical during power-up and power-down sequences.

Both SDV

(2.5V or 3.3V) and EV

are specified relative to IV

Board EV

/IV

0.1 µF

USB V

10 µF

GND

SDV

(2.5V/1.8V)

Supplies Stable

3.3V

2.5V

1.5V

Time

Notes:

IVDD should not exceed EVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EVDD, SDVDD,
IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.

r Sup

ly V

ltage

, PLLV

, SDV

, USBV

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.4.3.1

Power Up Sequence

If EV

/SDV

are powered up with IV

at 0 V, then the sense circuits in the I/O pads will cause all

pad output drivers connected to the EV

/SDV

to be in a high impedance state. There is no limit on

how long after EV

/SDV

powers up before IV

must powered up. IV

should not lead the EV

SDV

or PLLV

by more than 0.4 V during power ramp-up, or there will be high current in the internal

ESD protection diodes. The rise times on the power supplies should be slower than 1

µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1

µs or slower rise time for all supplies.

2. IV

/PLLV

and EV

/SDV

should track up to 0.9 V, then separate for the completion of

ramps with EV

/SD V

going to the higher external voltages. One way to accomplish this is to

use a low drop-out voltage regulator.

5.4.3.2

Power Down Sequence

If IV

/PLLV

are powered down first, then sense circuits in the I/O pads will cause all output drivers

to be in a high impedance state. There is no limit on how long after IV

and PLLV

power down before

or SDV

must power down. IV

should not lag EV

, SDV

, or PLLV

going low by more

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There
are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV

/PLLV

to 0 V.

2. Drop EV

/SDV

supplies.

5.5

Power Consumption Specifications

Estimated maximum RUN mode power consumption measurements are shown in the below figure.

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 9. Estimated Maximum RUN Mode Power Consumption

Table 8

lists estimated maximum power and current consumption for the device in various operating

modes.

Table 8. Estimated Maximum Power Consumption Specifications

Characteristic

Symbol

Typical

Max

Unit

Run Mode - Total Power Dissipation

Static
Dynamic

--
--
--

250

5.74

244

mW
mW
mW

Core Operating Supply Current

Run Mode

NOTES:

Current measured at maximum system clock frequency, all modules active, and default drive
strength with matching load.

TBD

Pad Operating Supply Current

Run Mode (application dependent)
Wait Mode
Stop Mode

--
--
--

144

mA
mA
mA

Estimated Power Consumption vs. Core Frequency

100

150

200

250

300

120

160

200

240

Core Frequency (MHz)

r
Co

s
u

t
io

(

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.6

Oscillator and PLL Electrical Characteristics

5.7

External Interface Timing Characteristics

Table 10

lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings
listed in

Table 10

are shown in

Figure 11

and

Figure 12

Table 9. PLL Electrical Characteristics

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

PLL Reference Frequency Range

Crystal reference
External reference

ref_crystal

ref_ext

TBD
TBD

16
16

MHz
MHz

Core frequency
CLKOUT Frequency

NOTES:

All internal registers retain data at 0 Hz.

sys

sys/3

TBD
TBD

240

MHz
MHz

Crystal Start-up Time

2, 3

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

cst

EXTAL Input High Voltage

Crystal Mode

All other modes (External, Limp)

This parameter is guaranteed by design rather than 100% tested.

IHEXT

TBD
TBD

V
V

EXTAL Input Low Voltage

Crystal Mode

All other modes (External, Limp)

ILEXT

TBD
TBD

V
V

XTAL Load Capacitance

PLL Lock Time

2, 5

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).

lpll

Duty Cycle of reference

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 10. General Input Timing Requirements

5.7.1

FlexBus

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to
slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to
asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple
chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects
(FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory
interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte
(8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common
ROM/flash memories.

5.7.1.1

FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.

Invalid

FB_CLK (80MHz)

TSETUP

THOLD

Input Setup And Hold

1.5V

rise

= V

1.5V

Valid

fall

= V

Input Rise Time

Input Fall Time

* The timings are also valid for inputs sampled on the negative clock edge.

Inputs

FB_CLK

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 11. FlexBus Read Timing.

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

Notes

Frequency of Operation

Mhz

sys/3

FB1

Clock Period (FB_CLK)

FBCK

12.5

cyc

FB2

Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)

FBCHDCV

7.0

NOTES:

Timing for chip selects only applies to the FB_CS[5:0] signals. Please see

Section 5.8.2, "DDR SDRAM AC Timing

Characteristics

" for SD_CS[3:0] timing.

FB3

Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)

FBCHDCI

, 2

The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference
Manual for more information.

FB4

Data Input Setup

DVFBCH

3.5

FB5

Data Input Hold

DIFBCH

FB6

Transfer Acknowledge (TA) Input Setup

CVFBCH

FB7

Transfer Acknowledge (TA) Input Hold

CIFBCH

FB8

Address Output Valid (A[23:0])

FBCHAV

6.0

These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.

FB9

Address Output Hold (A[23:0])

FBCHAI

FB_CLK

A[23:0]

D[31:0]

R/W

FB_CSn

FB1

A[23:0]

FB2

FB3

FB4

FB5

FB6

FB7

DATA

BE/BWEn

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 12. Flexbus Write Timing

5.8

SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

5.8.1

SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed
to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te
processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken
during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.

Table 11. SDR Timing Specifications

Symbol

Characteristic

Symbol

Min

Max

Unit

Notes

Frequency of Operation

TBD

Mhz

SD1

Clock Period

SDCK

12.5

TBD

SD2

Clock Skew

SDSK

TBD

SD3

Pulse Width High

SDCKH

0.45

0.55

SD_CLK

FB_CLK

A[23:0]

D[31:0]

R/W

FB_CSn

FB1

FB2

FB3

FB6

FB7

BE/BWEn

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

SD4

Pulse Width Low

SDCKH

0.45

0.55

SD_CLK

SD5

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid

SDCHACV

0.5

× SD_CLK

+ 1.0

SD6

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold

SDCHACI

2.0

SD7

SD_SDR_DQS Output Valid

DQSOV

Self timed

SD8

SD_DQS[3:0] input setup relative to SD_CLK

DQVSDCH

0.25

SD_CLK

0.40

× SD_CLK

SD9

SD_DQS[3:2] input hold relative to SD_CLK

DQISDCH

Does not apply. 0.5

×SD_CLK fixed

width.

SD10

Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)

DVSDCH

0.25

SD_CLK

SD11

Data Input Hold relative to SD_CLK (reference only)

DISDCH

1.0

SD12

Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid

SDCHDMV

0.75

× SD_CLK

+ 0.5

SD13

Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold

SDCHDMI

1.5

NOTES:

The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the MCF5373 Reference Manual for more information on setting the SDRAM clock rate.

SD_CLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.

Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.

Table 11. SDR Timing Specifications (continued)

Symbol

Characteristic

Symbol

Min

Max

Unit

Notes

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 13. SDR Write Timing

Figure 14. SDR Read Timing

SD_CLK0

SD_CLK1

SDDM

D[31:0]

A[23:0]

SD_BA[1:0]

SD2

CMD

ROW

SD2

SD1

SD5

COL

SD6

WD1

WD2

WD3

WD4

SD13

SD12

SD3

SD4

SD_CSn

SD_RAS

SD_WE

SD_CAS

SD_CLK0

SD_CLK1

SD_CSn,

SDDM

D[31:0]

A[23:0],

SD_RAS,

SD_BA[1:0]

SD2

CMD

ROW

SD2

SD1

SD5

COL

WD1

WD2

WD3

WD4

SD10

3/4 MCLK

SD_DQS

SD_DDQS

Delayed

SD11

SD8

Board Delay

SD9

Board Delay

SD7

tDQS

Reference

SD_CLK

from

Memories

(Measured at Output Pin)

(Measured at Input Pin)

SD6

NOTE: Data driven from memories relative

to delayed memory clock.

SD_WE

SD_CAS,

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.8.2

DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.

Table 12. DDR Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

Notes

Frequency of Operation

DDCK

TBD

Mhz

NOTES:

The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.

DD1

Clock Period

DDSK

TBD

12.5

SD_CLK is one SDRAM clock in (ns).

DD2

Pulse Width High

DDCKH

0.45

0.55

SD_CLK

Pulse width high plus pulse width low cannot exceed min and max clock period.

DD3

Pulse Width Low

DDCKL

0.45

0.55

SD_CLK

DD4

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid

SDCHACV

0.5

× SD_CLK

+ 1.0

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.

DD5

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold

SDCHACI

2.0

DD6

Write Command to first DQS Latching Transition

CMDVDQ

1.25

SD_CLK

DD7

Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)

DQDMV

1.5

This specification relates to the required input setup time of today's DDR memories. Rigoletto's output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data
beats will be valid for each subsequent DQS edge.

DD8

Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)

DQDMI

1.0

This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].

DD9

Input Data Skew Relative to DQS (Input Setup)

DVDQ

DD10 Input Data Hold Relative to DQS.

DIDQ

0.25

× SD_CLK

+ 0.5ns

DD11 DQS falling edge from SDCLK rising (output hold time) t

DQLSDCH

0.5

DD12 DQS input read preamble width

DQRPRE

0.9

1.1

SD_CLK

DD13 DQS input read postamble width

DQRPST

0.4

0.6

SD_CLK

DD14 DQS output write preamble width

DQWPRE

0.25

SD_CLK

DD15 DQS output write postamble width

DQWPST

0.4

0.6

SD_CLK

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 15. SD_CLK and SD_CLK crossover timing

Figure 16. DDR Write Timing

Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).

Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line

becomes invalid.

SD_CLK

SD_CSn,SD_WE,

DM3/DM2

D[31:24]/D[23:16]

A[13:0]

SD_RAS, SD_CAS

CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SD_DQS3/SD_DQS2

DD8

DD7

SD_CLK

DD3

DD2

DD6

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 17. DDR Read Timing

5.9

General Purpose I/O Timing

Table 13. GPIO Timing

NOTES:

GPIO pins include: IRQn, PWM, UART, and Timer pins.

Num

Characteristic

Symbol

Min

Max

Unit

FB_CLK High to GPIO Output Valid

CHPOV

FB_CLK High to GPIO Output Invalid

CHPOI

1.5

GPIO Input Valid to FB_CLK High

PVCH

FB_CLK High to GPIO Input Invalid

CHPI

1.5

SD_CLK

SD_CSn,SD_WE,

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

A[13:0]

SD_RAS, SD_CAS

CMD

ROW

DD1

DD5

DD4

WD1 WD2 WD3 WD4

SD_DQS3/SD_DQS2

DD9

SD_CLK

DD3

DD2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble

DQS Read

Postamble

DQS Read

Preamble

DQS Read

Postamble

= 2

.
5

= 2

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 18. GPIO Timing

5.10 Reset and Configuration Override Timing

Figure 19. RESET and Configuration Override Timing

Table 14. Reset and Configuration Override Timing

Num

Characteristic

Symbol

Min

Max

Unit

RESET Input valid to FB_CLK High

RVCH

FB_CLK High to RESET Input invalid

CHRI

1.5

RESET Input valid Time

NOTES:

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.

RIVT

CYC

FB_CLK High to RSTOUT Valid

CHROV

RSTOUT valid to Config. Overrides valid

ROVCV

Configuration Override Setup Time to RSTOUT invalid

COS

CYC

Configuration Override Hold Time after RSTOUT invalid

COH

RSTOUT invalid to Configuration Override High Impedance

ROICZ

CYC

FB_CLK

GPIO Outputs

GPIO Inputs

FB_CLK

RESET

RSTOUT

Configuration Overrides*:

(RCON, Override pins])

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

NOTE

Refer to the CCM chapter of the MCF5373 Reference Manual for more
information.

5.11 USB On-The-Go

The MCF5373 device is compliant with industry standard USB 2.0 specification.

5.12 SSI Timing Specifications

The following figure and table lists the specifications for the SSI module.

Figure 20. SSI External Continous Clock Timing Diagram

Table 15. SSI Timing

Num

Description

1.8 +/- 0.10V

Unit

Minimum

Maximum

SSI_BCLK clock period

1/(64f

)

SSI_BCK high-level time

SSI_BCK low-level time

SSI_BCLK

STFS

SSI_TXD (Output)

SSI_RXD (Input)

Note: SSI External. Continous clock Synchronous mode only

SSI_MCLK

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

5.13 I

C Input/Output Timing Specifications

Table 16

lists specifications for the I

C input timing parameters shown in

Figure 21

Table 17

lists specifications for the I

C output timing parameters shown in

Figure 21

SSI_BCK rising edge to SSI_MCLK edge

SSI_MCLK edge to SSI_BCLK rising edge

SSI_TXD/SSI_RXD data set-up time

SSI_TXD/SSI_RXD data hold time

NOTES:

s is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz

Table 16. I

C Input Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

cyc

Clock low period

cyc

I2C_SCL/I2C_SDA rise time (V

= 0.5 V to V

= 2.4 V)

Data hold time

I2C_SCL/I2C_SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

cyc

Data setup time

Start condition setup time (for repeated start condition only)

cyc

Stop condition setup time

cyc

Table 17. I

C Output Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

cyc

Clock low period

cyc

I2C_SCL/I2C_SDA rise time (V

= 0.5 V to V

= 2.4 V)

µs

Data hold time

cyc

I2C_SCL/I2C_SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

cyc

Data setup time

cyc

Start condition setup time (for repeated start condition only)

cyc

Stop condition setup time

cyc

Table 15. SSI Timing (continued)

Num

Description

1.8 +/- 0.10V

Unit

Minimum

Maximum

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 21

shows timing for the values in

Table 17

and

Table 16

Figure 21. I

C Input/Output Timings

5.14 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

5.14.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_RXCLK frequency.

Table 18

lists MII receive channel timings.

Figure 22

shows MII receive signal timings listed in

Table 18

NOTES:

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in

Table 17

. The I

C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in

Table 17

are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively
drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.

Specified at a nominal 50-pF load.

Table 18. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

FEC_RXCLK pulse width high

35%

65%

FEC_RXCLK period

FEC_RXCLK pulse width low

35%

65%

FEC_RXCLK period

I2C_SCL

I2C_SDA

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 22. MII Receive Signal Timing Diagram

5.14.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,

FEC_TXER, FEC_TXCLK)

Table 19

lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_TXCLK frequency.

The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from
either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options
allows the use of non-compliant MII PHYs.

Refer to the Ethernet chapter for details of this option and how to enable it.

Table 19. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

FEC_TXCLK pulse width high

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

35%

65%

FEC_TXCLK period

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 23

shows MII transmit signal timings listed in

Table 19

Figure 23. MII Transmit Signal Timing Diagram

5.14.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 20

lists MII asynchronous inputs signal timing.

Figure 24

shows MII asynchronous input timings listed in

Table 20

Figure 24. MII Async Inputs Timing Diagram

5.14.4 MII Serial Management Channel Timing (FEC_MDIO and

FEC_MDC)

Table 21

lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 20. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_CRS, FEC_COL minimum pulse width

1.5

FEC_TXCLK period

Table 21. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)

M11

FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)

M12

FEC_MDIO (input) to FEC_MDC rising edge setup

M13

FEC_MDIO (input) to FEC_MDC rising edge hold

FEC_TXCLK (input)

FEC_TXD[3:0] (outputs)

FEC_TXEN
FEC_TXER

FEC_CRS

FEC_COL

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 25

shows MII serial management channel timings listed in

Table 21

Figure 25. MII Serial Management Channel Timing Diagram

5.15 32-Bit Timer Module Timing Specifications

Table 22

lists timer module AC timings.

5.16 QSPI Electrical Specifications

Table 23

lists QSPI timings.

M14

FEC_MDC pulse width high

40%

60%

FEC_MDC period

M15

FEC_MDC pulse width low

40%

60%

FEC_MDC period

Table 22. Timer Module AC Timing Specifications

Name

Characteristic Unit

Min

Max

DT0IN / DT1IN / DT2IN / DT3IN cycle time

CYC

DT0IN / DT1IN / DT2IN / DT3IN pulse width

CYC

Table 21. MII Serial Management Channel Timing (continued)

Num

Characteristic

Min

Max

Unit

M11

FEC_MDC (output)

FEC_MDIO (output)

M12

M13

FEC_MDIO (input)

M10

M14

M15

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

The values in

Table 23

correspond to

Figure 26

Figure 26. QSPI Timing

5.17 JTAG and Boundary Scan Timing

Table 23. QSPI Modules AC Timing Specifications

Name

Characteristic Min

Max

Unit

QS1

QSPI_CS[3:0] to QSPI_CLK

510

CYC

QS2

QSPI_CLK high to QSPI_DOUT valid.

QS3

QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QS4

QSPI_DIN to QSPI_CLK (Input setup)

QS5

QSPI_DIN to QSPI_CLK (Input hold)

Table 24. JTAG and Boundary Scan Timing

Num

Characteristics

Symbol

Min

Max

Unit

TCLK Frequency of Operation

JCYC

1/4

sys/3

TCLK Cycle Period

JCYC

CYC

TCLK Clock Pulse Width

JCW

TCLK Rise and Fall Times

JCRF

Boundary Scan Input Data Setup Time to TCLK Rise

BSDST

Boundary Scan Input Data Hold Time after TCLK Rise

BSDHT

TCLK Low to Boundary Scan Output Data Valid

BSDV

TCLK Low to Boundary Scan Output High Z

BSDZ

TMS, TDI Input Data Setup Time to TCLK Rise

TAPBST

J10

TMS, TDI Input Data Hold Time after TCLK Rise

TAPBHT

QSPI_CS[3:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3

QS4

QS2

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

Figure 27. Test Clock Input Timing

Figure 28. Boundary Scan (JTAG) Timing

J11

TCLK Low to TDO Data Valid

TDODV

J12

TCLK Low to TDO High Z

TDODZ

J13

TRST Assert Time

TRSTAT

100

J14

TRST Setup Time (Negation) to TCLK High

TRSTST

NOTES:

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Table 24. JTAG and Boundary Scan Timing (continued)

Num

Characteristics

Symbol

Min

Max

Unit

TCLK

(input)

Input Data Valid

Output Data Valid

TCLK

Data Inputs

Data Outputs

Preliminary Electrical Characteristics

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 29. Test Access Port Timing

Figure 30. TRST Timing

5.18 Debug AC Timing Specifications

Table 25

lists specifications for the debug AC timing parameters shown in

Figure 32

Table 25. Debug AC Timing Specification

Num

Characteristic

Units

Min

Max

DE0

PSTCLK cycle time

0.3

cyc

DE1

PST valid to PSTCLK high

DE2

PSTCLK high to PST invalid

1.5

DE3

DSCLK cycle time

cyc

DE4

DSI valid to DSCLK high

cyc

DE5

NOTES:

DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input
relative to the rising edge of FB_CLK.

DSCLK high to DSO invalid

cyc

DE6

BKPT input data setup time to FB_CLK high

DE7

FB_CLK high to BKPT invalid

0 --

Input Data Valid

Output Data Valid

TCLK

TDI

TDO

TMS

J10

J11

J12

J11

TCLK

TRST

J13

J14

MCF5373 ColdFire

Microprocessor Data Sheet, Rev. 0.3

Preliminary

Revision History

Freescale Semiconductor

Figure 31

shows real-time trace timing for the values in

Table 25

Figure 31. Real-Time Trace AC Timing

Figure 32

shows BDM serial port AC timing and BKPT pin timing for the values in

Table 25

Figure 32. BDM Serial Port AC Timing

Revision History

Table 26. MCF5373DS Document Revision History

Rev. No.

Substantive Changes

Date of Release

· Initial release.

11/2005

0.1

· Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL

(H11->J11) in

Table 3

Figure 1

is correct.

12/2005

0.2

· Added not to

Section 4, "Mechanicals and Pinouts."

· Added "top view" and "bottom view" where appropriate in mechanical

drawings and pinout figures.

Figure 10

: Corrected "FB_CLK (75MHz)" label to "FB_CLK (80MHz)"

3/2006

0.3

· Changed 160QFP pinouts in

Figure 3

and

Table 3

: Removed IRQ3

pin, shifted pins 8999 up one pin to 90100. Pin 89 is now VSS.

Table 3

: Rearranged GPIO signal names for FEC pins.

· Removed ULPI specifications as the device does not support ULPI.

4/2006

PSTCLK

PST[3:0]

DE2

DE1

DDATA[3:0]

DE0

DSI

DSO

Current

FB_CLK

Past

Current

DSCLK

DE3

DE4

DE5

BKPT

DE6

DE7

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MCF5373DS
Rev. 0.3
04/2006

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