Freescale Semiconductor
Data Sheet

MCF5485EC

Rev. 2.1, 12/2004

Table of Contents

This chapter contains electrical specification tables and
reference timing diagrams for the MCF548x
microprocessor. This section contains detailed
information on power considerations, DC/AC electrical
characteristics, and AC timing specifications of the
MCF548x.

NOTE

The parameters specified
in this MPU document
supersede any values
found in the module
specifications.

Maximum Ratings

Table 1

lists maximum and minimum ratings for supply

and operating voltages and storage temperature.
Operating outside of these ranges may cause erratic
behavior or damage to the processor.

Maximum Ratings................................................ 1

Thermal Characteristics ......................................2

DC Electrical Specifications ................................ 3

Supply Voltage Sequencing and Separation
Cautions .............................................................. 5

Output Driver Capability and Loading ................. 6

PLL Timing Specifications ................................... 7

Reset Timing Specifications ................................ 8

FlexBus................................................................ 9

SDRAM Bus ...................................................... 11

PCI Bus ............................................................. 17

Fast Ethernet AC Timing Specifications ............ 18

General Timing Specifications........................... 21

C Input/Output Timing Specifications ............. 21

JTAG and Boundary Scan Timing ..................... 23

DSPI Electrical Specifications ........................... 26

Timer Module AC Timing Specifications............ 26

MCF548x Integrated
Microprocessor Electrical
Characteristics

Applies to the MCF5480, MCF5481, MCF5482, MCF5483,
MCF5484, and MCF5485

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Thermal Characteristics

Freescale Semiconductor

Thermal Characteristics

2.1

Operating Temperatures

Table 2

lists junction and ambient operating temperatures.

2.2

Thermal Resistance

Table 3

lists thermal resistance values.

Table 1. Absolute Maximum Ratings

Rating

Symbol

Value

Units

External (I/O pads) supply voltage (3.3-V power pins)

0.3 to +4.0

Internal logic supply voltage

0.5 to +2.0

Memory (I/O pads) supply voltage (2.5-V power pins)

SD V

0.3 to +4.0 SDR Memory
0.3 to +2.8 DDR Memory

PLL supply voltage

PLL V

0.5 to +2.0

Internal logic supply voltage, input voltage level

0.5 to +3.6

Storage temperature range

stg

55 to +150

Table 2. Operating Temperatures

Characteristic

Symbol

Value

Units

Maximum operating junction temperature

105

Maximum operating ambient temperature

Amax

<85

NOTES:

This published maximum operating ambient temperature should be used only as a system design guideline. All
device operating parameters are guaranteed only when the junction temperature lies within the specified range.

Minimum operating ambient temperature

Amin

Table 3. Thermal Resistance

Characteristic

Symbol

Value

Unit

324 pin TEPBGA -- Junction to ambient, natural
convection

Four layer board (2s2p)

JMA

2224

1,2

°C/W

388 pin TEPBGA -- Junction to ambient, natural
convection

Four layer board (2s2p)

JMA

2022

°C/W

Junction to ambient (@200 ft/min)

Four layer board (2s2p)

JMA

°C/W

Junction to board

°C/W

Junction to case

°C/W

Junction to top of package

Natural convection

°C/W

DC Electrical Specifications

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

DC Electrical Specifications

Table 4

lists DC electrical operating temperatures. This table is based on an operating voltage of

= 3.3 V

± 0.3 V

and IV

of 1.5 ± 0.07 V

NOTES:

and

parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection.

Freescale recommends the use of

and power dissipation specifications in the system design to prevent device

junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer's system using
the

parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.

Table 4.

DC Electrical Specifications

Characteristic

Symbol

Min

Max

Units

External (I/O pads) operation voltage range

3.0

3.6

Memory (I/O pads) operation voltage range (DDR Memory)

SD V

2.30

2.70

Internal logic operation voltage range

NOTES:

and PLL V

should be at the same voltage. PLL V

should have a filtered input. Please see

Figure 1

for an

example circuit. Note: There are three PLL V

inputs. A filter circuit should used on each PLL V

input.

1.43

1.58

PLL Analog operation voltage range

PLL V

1.43

1.58

USB oscillator operation voltage range

USB_OSV

3.0

3.6

USB digital logic operation voltage range

USBV

3.0

3.6

USB PHY operation voltage range

USB_PHYV

3.0

3.6

USB oscillator analog operation voltage range

USB_OSCAV

1.43

1.58

USB PLL operation voltage range

USB_PLLV

1.43

1.58

Input high voltage SSTL 3.3V (SDR DRAM)

2.0

3.6

Input low voltage SSTL 3.3V (SDR DRAM)

0.5

0.8

Input high voltage SSTL 2.5V (DDR DRAM)

2.0

2.8

Input low voltage SSTL 2.5V (DDR DRAM)

0.5

0.8

Output high voltage I

= 8 mA, 16 mA,24 mA

2.4

-- V

Output low voltage I

= 8 mA, 16 mA,24 mA

0.5

Capacitance

, V

= 0 V, f = 1 MHz

Capacitance C

is periodically sampled rather than 100% tested.

TBD

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

DC Electrical Specifications

Freescale Semiconductor

3.1

PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V

pins.

The filter shown in

Figure 1

should be connected between the board V

and the PLL V

pins. The

resistor and capacitors should be placed as close to the dedicated PLL V

pin as possible.

Figure 1. System PLL V

Power Filter

3.2

USB Power Filtering

To minimize noise, a external filters are required for each of the USB power pins. The filter shown in

Figure 2

should be connected between the board EV

or IV

and each of the USB V

pins. The

resistor and capacitors should be placed as close to the dedicated USB V

pin as possible. A separate

filter circuit should be included for each USB V

pin, a total of five circuits.

Figure 2. USB V

Power Filter

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also
recommended in parallel with those shown.

Table 5

lists the resistor values and supply voltages to be used in the circuit for each of the USB V

pins.

Table 5. USB Filter Circuit Values

USB V

Pin

Nominal Voltage

Resistor Value (R)

USB_OSCVDD

3.3V

USBVDD

3.3V

USB_PHYVDD

3.3V

USB_OSCAVDD

1.5V

USB_PLLVDD

1.5V

Board V

10 W

0.1 µF

PLL V

10 µF

GND

Board EV

/IV

0.1 µF

USB V

10 µF

GND

Supply Voltage Sequencing and Separation Cautions

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Supply Voltage Sequencing and Separation
Cautions

Figure 3

shows situations in sequencing the I/O V

(EV

), SDRAM V

(SD V

), PLL V

(PLL

), and Core V

(IV

Figure 3. Supply Voltage Sequencing and Separation Cautions

The relationship between SD V

and EV

is non-critical during power-up and power-down sequences.

Both SD V

(2.5V or 3.3V) and EV

are specified relative to IV

4.1

Power Up Sequence

If EV

/SD V

are powered up with the IV

at 0V, then the sense circuits in the I/O pads will cause

all pad output drivers connected to the EV

/SD V

to be in a high impedance state. There is no limit

on how long after EV

/SD V

powers up before IV

must power up. IV

should not lead the EV

SD V

or PLL V

by more than 0.4V during power ramp up, or there will be high current in the internal

ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid
turning on the internal ESD protection clamp diodes.

, SD V

(3.3V)

SD V

(2.5V)

, PLL V

Supplies Stable

3.3V

2.5V

1.5V

Time

NOTES:

should not exceed EV

, SD V

or PLL V

by more than

0.4V at any time, including power-up.
Recommended that IV

/PLL V

should track EV

/SD V

up to

0.9V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EV

, SD V

, or PLL V

) by more than 0.5V at any time, including during power-up.

Use 1 microsecond or slower rise time for all supplies.

DC P

r Supp

ly V

ltage

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Output Driver Capability and Loading

Freescale Semiconductor

The recommended power up sequence is as follows:

1. Use 1 microsecond or slower rise time for all supplies.
2. IV

/PLL V

and EV

/SD V

should track up to 0.9V, then separate for the completion of

ramps with EV

/SD V

going to the higher external voltages. One way to accomplish this is to

use a low drop-out voltage regulator.

4.2

Power Down Sequence

If IV

PLL V

are powered down first, then sense circuits in the I/O pads will cause all output drivers

to be in a high impedance state. There is no limit on how long after IV

and PLL V

power down before

or SD V

must power down. IV

should not lag EV

, SD V

, or PLL V

going low by

more than 0.4V during power down or there will be undesired high current in the ESD protection diodes.
There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV

/PLL V

to 0V

2. Drop EV

/SD V

supplies

Output Driver Capability and Loading

Table 6

lists values for drive capability and output loading.

Table 6. I/O Driver Capability

Signal

Drive

Capability

Output

Load (C

)

SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0],
SDWE, SDBA[1:0]

24 mA

15 pF

SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0],
SDCLK[1:0], SDCKE)

24 mA

15 pF

SDRAMC chip selects (SDCS[3:0])

24 mA

15 pF

FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE)

16 mA

20 pF

FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER

8 mA

15 pF

Timer (TOUT[3:0])

8 mA

50 pF

FlexCAN (CANTX)

8 mA

30 pF

DACK[1:0]

8 mA

30 pF

PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,

8 mA

30 pF

DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)

24 mA

50 pF

PLL Timing Specifications

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

PLL Timing Specifications

The specifications in

Table 7

are for the CLKIN pin.

Figure 4. Input Clock Timing Diagram

PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL,
PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP,
PCIPAR, PCITRDY, PCIIRDY

16 mA

50 pF

I2C (SCL, SDA)

8 mA

50 pF

BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO,

8 mA

25 pF

RSTO

8 mA

50 pF

Table 7. Clock Timing Specification

Num Characteristic

Min

Max

Units

Cycle time

15.15

33.3

Rise time (20% of Vdd to 80% of vdd)

Fall time (80% of Vdd to 20% of Vdd)

Duty cycle (at 50% of Vdd)

Table 6. I/O Driver Capability (continued)

Signal

Drive

Capability

Output

Load (C

)

CLKIN

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Reset Timing Specifications

Freescale Semiconductor

Figure 5

correlates CLKIN, internal bus, and core clock frequencies for the 1x4x multipliers.

Figure 5. CLKIN, Internal Bus, and Core Clock Ratios

Reset Timing Specifications

Table 9

lists specifications for the reset timing parameters shown in

Figure 6

shows reset timing for the values in

Table 9

Table 8. MCF548X Divide Ratio Encodings

AD[12:8]

NOTES:

All other values of AD[12:8] are reserved.

Clock

Ratio

CLKIN--PCI and FlexBus

Frequency Range (MHz)

Internal XLB, SDRAM

Bus, and PSTCLK Frequency

Range (MHz)

Core Frequency Range

(MHz)

00011

1:2

41.650.0

83.33100

166.66200

00101

1:2

25.041.5

50.083.0

Note that DDR memories typically have a minimum speed of 83 MHz. Some vendors specify down to 75 MHz.
Check with memory component specifications to verify.

100.0166.66

01111

1:4

100

200

Table 9. Reset Timing Specification

Num

Characteristic

66 MHz CLKIN

Units

Min

Max

NOTES:

RSTI and FlexBus data lines are synchronized internally. Setup and hold
times must be met only if recognition on a particular clock is required.

Valid to CLKIN (setup)

CLKIN to invalid (hold)

1.0

RSTI to invalid (hold)

1.0

25 40 50 60 70

70 80 90 100 110 120 130 140 150 160 170 180 190 200

25.0

50.0

100.0

CLKIN (MHz)

Core Clock (MHz)

Core Clock

CLKIN

200.0

40 50 60 70 80 90 100

50.0

100.0

Internal Clock

Internal Clock (MHz)

25.0

200.0

100.0

FlexBus

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Figure 6. Reset Timing

FlexBus

A multi-function external bus interface called FlexBus is provided on the MCF5482 with basic
functionality to interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be
directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories,
gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six
general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and
can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing
is compatible with common ROM / flash memories.

8.1

FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.

Table 10. FlexBus AC Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

Mhz

FB1

Clock Period (CLKIN)

15.15

33.33

FB2

Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

7.0

FB3

Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

, 4

FB4

Data Input Setup

3.5

FB5

Data Input Hold

CLKIN

RSTI

Mode Select

FlexBus

NOTE:

Mode selects are registered on the rising clock edge before
the cycle in which RSTI is recognized as being negated.

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

FlexBus

Freescale Semiconductor

Figure 7. FlexBus Read Timing

FB6

Transfer Acknowledge (TA) Input Setup

FB7

Transfer Acknowledge (TA) Input Hold

FB8

Address Output Valid (PCIAD[31:0])

7.0

FB9

Address Output Hold (PCIAD[31:0])

NOTES:

The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.

Max cycle rate is determined by CLKIN and how the user has the system PLL configured.

Timing for chip selects only applies to the FBCS[5:0] signals. Please see

Section 9.2, "DDR SDRAM AC

Timing Characteristics

" for SDCS[3:0] timing.

The FlexBus supports programming an extension of the address hold. Please consult the MCF548X
specification manual for more information.

These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.

Table 10. FlexBus AC Timing Specifications (continued)

Num

Characteristic

Min

Max

Unit

Notes

CLKIN

AD[X:0]

AD[31:Y]

R/W

ALE

TSIZ[1:0]

FBCSn, BE/BWEn

FB1

A[X:0]

FB2

FB3

TSIZ[1:0]

FB4

FB5

FB6

FB7

DATA

A[31:Y]

SDRAM Bus

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Figure 8. FlexBus Write Timing

SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.

9.1

SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read
cycles. The MCF548x SDRAM controller is a DDR controller that has an SDR mode. Because it is
designed to support DDR, a DQS pulse must still be supplied to the MCF548x for each data beat of an
SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SDR_DQS signal and its usage.

CLKIN

AD[X:0]

AD[31:Y]

R/W

ALE

TSIZ[1:0]

FBCSn, BE/BWEn

FB1

A[X:0]

A[31:Y]

DATA

FB2

FB3

TSIZ[1:0]

FB3

FB6

FB7

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

SDRAM Bus

Freescale Semiconductor

Table 11. SDR Timing Specifications

Symbol

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

133

Mhz

NOTES:

The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Specification for
more information on setting the SDRAM clock rate.

SD1

Clock Period (t

)

7.52

SDCLK is one SDRAM clock in (ns).

SD2

Clock Skew (t

)

TBD

SD3

Pulse Width High (t

CKH

)

0.45

0.55

SDCLK

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD4

Pulse Width Low (t

CKL

)

0.45

0.55

SDCLK

Pulse width high plus pulse width low cannot exceed min and max clock period.

SD5

Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (t

CMV

)

0.5

× SDCLK +

1.0ns

SD6

Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (t

CMH

)

2.0

SD7

SDRDQS Output Valid (t

DQSOV

)

Self timed

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.

SD8

SDDQS[3:0] input setup relative to SDCLK (t

DQSIS

)

0.25

× SDCLK 0.40 × SDCLK

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.

SD9

SDDQS[3:0] input hold relative to SDCLK (t

DQSIH

)

Does not apply. 0.5 SDCLK fixed width.

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.

SD10

Data Input Setup relative to SDCLK (reference only) (t

DIS

)

0.25

× SDCLK

Since a read cycle in SDR mode still uses the DQS circuit within the MCF548X, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input
setup spec is just provided as guidance.

SD11

Data Input Hold relative to SDCLK (reference only) (t

DIH

)

1.0

SD12

Data and Data Mask Output Valid (t

)

0.75

× SDCLK

+0.500ns

SD13

Data and Data Mask Output Hold (t

)

1.5

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

SDRAM Bus

Freescale Semiconductor

Figure 10. SDR Read Timing

9.2

DDR SDRAM AC Timing Characteristics

When using the DDR SDRAM controller, the following timing numbers must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.

Table 12

shows the DDR clock crossover specifications.

Table 12. DDR Clock Crossover Specifications

Symbol

Characteristic

Min

Max

Unit

Clock output mid-point voltage

1.05

1.45

OUT

Clock output voltage level

0.3

SD_VDD + 0.3

Clock output differential voltage (peak to peak swing)

0.7

SD_VDD + 0.6

Clock crossing point voltage

NOTES:

The clock crossover voltage is only guaranteed when using the highest drive strength option for the
SDCLK[1:0] and SDCLK[1:0] signals.

1.05 1.45

SDCLK0

SDCLK1

SDCSn,SDWE,

SDDM

SDDATA

SDADDR,

RAS, CAS

SDBA[1:0]

SD2

CMD

ROW

SD2

SD1

SD5

COL

WD1

WD2

WD3

WD4

SD10

3/4 MCLK

SDRQS

SDDQS

Delayed

SD11

SD8

Board Delay

SD9

Board Delay

SD7

tDQS

Reference

SDCLK

form

Memories

(Measured at Output Pin)

(Measured at Input Pin)

SD6

NOTE: Data driven from memories relative

to delayed memory clock.

SDRAM Bus

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Figure 11. DDR Clock Timing Diagram

Table 13. DDR Timing Specifications

Symbol

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

NOTES:

Note that DDR memories typically have a minimum speed specification of 83 MHz. Some vendors go to 75 MHz. Check
with memory component specifications to verify.

133

MHz

DD1

Clock Period (t

)

7.52

SDCLK is one memory clock in (ns).

DD2

Pulse Width High (t

CKH

)

0.45

0.55

SDCLK

Pulse width high plus pulse width low cannot exceed max clock period.

DD3

Pulse Width Low (t

CKL

)

0.45

0.55

SDCLK

Pulse width high plus pulse width low cannot exceed max clock period.

DD4

Address, SDCKE, CAS, RAS, WE, SDBA, SDCS--Output
Valid (t

CMV

)

0.5

× SDCLK

+ 1.0 ns

Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.

DD5

Address, SDCKE, CAS, RAS, WE, SDBA, SDCS--Output Hold
(t

CMH

)

2.0

DD6

Write Command to first DQS Latching Transition (t

DQSS

)

1.25

SDCLK

DD7

Data and Data Mask Output Setup (DQ

->DQS) Relative to

DQS (DDR Write Mode) (t

)

1.0

This specification relates to the required input setup time of today's DDR memories. SDDATA[31:24] is relative to
SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative
SDDQS0.

DD8

Data and Data Mask Output Hold (DQS

->DQ) Relative to DQS

(DDR Write Mode) (t

)

1.0

DD9

Input Data Skew Relative to DQS (Input Setup) (t

)

DD10

Input Data Hold Relative to DQS (t

)

0.25

× SDCLK

+ 0.5ns

DD11

DQS falling edge to SDCLK rising (output setup time) (t

DSS

)

0.5

DD12

DQS falling edge from SDCLK rising (output hold time) (t

DSH

)

0.5

DD13

DQS input read preamble width (t

RPRE

)

0.9

1.1

SDCLK

DD14

DQS input read postamble width (t

RPST

)

0.4

0.6

SDCLK

DD15

DQS output write preamble width (t

WPRE

)

0.25

SDCLK

DD16

DQS output write postamble width (t

WPST

)

0.4

0.6

SDCLK

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

SDRAM Bus

Freescale Semiconductor

Figure 12. DDR Write Timing

The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining
data beats will be valid for each subsequent SDDQS edge.

This specification relates to the required hold time of today's DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.

Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).

Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.

SDCLK0

SDCLK1

SDCSn,SDWE,

SDDM

SDDATA

SDADDR,

RAS, CAS

SDBA[1:0]

CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SDDQS

DD8

DD7

SDCLK0

SDCLK1

DD3

DD2

DD6

PCI Bus

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Figure 13. DDR Read Timing

PCI Bus

The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the
PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis.

Table 14. PCI Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

MHz

Clock Period (t

)

15.15

33.33

Address, Data, and Command (33

< PCI 66 Mhz)--Input Setup (t

)

3.0

Address, Data, and Command (0

< PCI 33 Mhz)--Input Setup (t

)

7.0

Address, Data, and Command (33-66 Mhz) - Output Valid (t

)

6.0

Address, Data, and Command (0 -33 Mhz) - Output Valid (t

)

11.0

SDCLK0

SDCLK1

SDCSn,SDWE,

SDDQS

SDDATA

SDADDR,

RAS, CAS

SDBA[1:0]

CMD

ROW

DD1

DD5

DD4

WD1 WD2 WD3 WD4

SDDQS

DD9

SDCLK0

SDCLK1

DD3

DD2

SDDATA

WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble

DQS Read
Postamble

DQS Read

Preamble

DQS Read
Postamble

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Fast Ethernet AC Timing Specifications

Freescale Semiconductor

Figure 14. PCI Timing

Fast Ethernet AC Timing Specifications

11.1 MII/7-WIRE Interface Timing Specs

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the EMAC_10_100 I/O signals.

The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of
transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may
be altered to match that specific transceiver.

PCI signals (0 - 66 Mhz) - Output Hold (t

)

PCI signals (0 - 66 Mhz) - Input Hold (t

)

PCI REQ/GNT (33

< PCI 66Mhz) - Output valid (t

)

PCI REQ/GNT (0

< PCI 33Mhz) - Output valid (t

)

P10

PCI REQ/GNT (33

< PCI 66Mhz) - Input Setup (t

)

P11

PCI REQ (0

< PCI 33Mhz) - Input Setup (t

)

P12

PCI GNT (0

< PCI 33Mhz) - Input Setup (t

)

NOTES:

Please see Section 2.2.6, "Reset Configuration Pins," for more information on setting the PCI clock rate. Also
specific guidelines may need to be followed when operating the system PLL below certain frequencies.

Max cycle rate is determined by CLKIN and how the user has the system PLL configured.

All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.

PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.

PCI 2.2 spec requires zero input hold.

These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.

Table 14. PCI Timing Specifications (continued)

Num

Characteristic

Min

Max

Unit

Notes

CLKIN

Input

Setup/Hold

Output Valid

Input Valid

Output

Valid/Hold

Fast Ethernet AC Timing Specifications

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Figure 15. MII Receive Signal Timing Diagram

11.2 MII Transmit Signal Timing

Figure 16. MII Transmit Signal Timing Diagram

Table 15. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

RXCLK pulse width high

35%

65%

RXCLK period

RXCLK pulse width low

35%

65%

RXCLK period

Table 16. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

TXCLK pulse width high

35%

65%

TXCLK period

TXCLK pulse width low

35%

65%

TXCLK period

RXCLK (Input)

RXD[3:0] (Inputs)

RXDV,

RXER

TXCLK (Input)

TXD[3:0] (Outputs)

TXEN,

TXER

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Fast Ethernet AC Timing Specifications

Freescale Semiconductor

11.3 MII Async Inputs Signal Timing (CRS, COL)

Figure 17. MII Async Inputs Timing Diagram

11.4 MII Serial Management Channel Timing (MDIO,MDC)

Figure 18. MII Serial Management Channel TIming Diagram

Table 17. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

CRS, COL minimum pulse width

1.5

TX_CLK period

Table 18. MII Serial Management Channel Signal Timing

Num

Characteristic

Min

Max

Unit

M10

MDC falling edge to MDIO output invalid
(min prop delay)

M11

MDC falling edge to MDIO output valid
(max prop delay)

M12

MDIO (input) to MDC rising edge setup

M13

MDIO (input) to MDC rising edge hold

M14

MDC pulse width high

40%

60%

MDC period

M15

MDC pulse width low

40%

60%

MDC period

CRS, COL

MDC (Output)

M14

MDIO (Output)

MDIO (Input)

M15

M10

M11

M12

M13

General Timing Specifications

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

General Timing Specifications

Table 19

lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts.

C Input/Output Timing Specifications

Table 20

lists specifications for the I

C input timing parameters shown in

Figure 19

Table 21

lists specifications for the I

C output timing parameters shown in

Figure 19

Table 19. General AC Timing Specifications

Name

Characteristic Min

Max

Unit

CLKIN high to signal output valid

PSTCLK

CLKIN high to signal invalid (output hold)

Signal input pulse width

PSTCLK

Table 20. I

C Input Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

Start condition hold time

Bus clocks

Clock low period

Bus clocks

SCL/SDA rise time (V

= 0.5 V to V

= 2.4 V)

Data hold time

SCL/SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

Bus clocks

Data setup time

Start condition setup time (for repeated start condition only)

Bus clocks

Stop condition setup time

Bus clocks

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

C Input/Output Timing Specifications

Freescale Semiconductor

Figure 19

shows timing for the values in

Table 20

and

Table 21

Figure 19. I

C Input/Output Timings

Table 21. I

C Output Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

NOTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in

Table 21

. The I

C interface is designed to scale the actual data transition time to move it to the

middle of the SCL low period. The actual position is affected by the prescale and division values
programmed into the IFDR; however, the numbers given in

Table 21

are minimum values.

Start condition hold time

Bus clocks

Clock low period

Bus clocks

Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.

SCL/SDA rise time (V

= 0.5 V to V

= 2.4 V)

µS

Data hold time

Bus clocks

Specified at a nominal 50-pF load.

SCL/SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

Bus clocks

Data setup time

Bus clocks

Start condition setup time (for repeated start
condition only)

Bus clocks

Stop condition setup time

Bus clocks

SCL

SDA

JTAG and Boundary Scan Timing

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

JTAG and Boundary Scan Timing

Figure 20. Test Clock Input Timing

Table 22. JTAG and Boundary Scan Timing

Num

Characteristics

NOTES:

MTMOD is expected to be a static signal. Hence, it is not associated with any timing

Symbol

Min

Max

Unit

TCLK Frequency of Operation

JCYC

MHz

TCLK Cycle Period

JCYC

TCLK Clock Pulse Width

JCW

15.15

TCLK Rise and Fall Times

JCRF

0.0

3.0

Boundary Scan Input Data Setup Time to TCLK Rise

BSDST

5.0

Boundary Scan Input Data Hold Time after TCLK Rise

BSDHT

24.0

TCLK Low to Boundary Scan Output Data Valid

BSDV

0.0

15.0

TCLK Low to Boundary Scan Output High Z

BSDZ

0.0

15.0

TMS, TDI Input Data Setup Time to TCLK Rise

TAPBST

5.0

J10

TMS, TDI Input Data Hold Time after TCLK Rise

TAPBHT

10.0

J11

TCLK Low to TDO Data Valid

TDODV

0.0

15.0

J12

TCLK Low to TDO High Z

TDODZ

0.0

15.0

J13

TRST Assert Time

TRSTAT

100.0

J14

TRST Setup Time (Negation) to TCLK High

TRSTST

10.0

TCLK (Input)

JTAG and Boundary Scan Timing

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

Table 23

lists specifications for the debug AC timing parameters shown in

Figure 25

Figure 24

shows real-time trace timing for the values in

Table 23

Figure 24. Real-Time Trace AC Timing

Figure 25

shows BDM serial port AC timing for the values in

Table 23

Figure 25. BDM Serial Port AC Timing

Table 23. Debug AC Timing Specification

Num

Characteristic

66 MHz

Units

Min

Max

PSTDDATA to PSTCLK setup

4.5

PSTCLK to PSTDDATA hold

4.5

DSI-to-DSCLK setup

PSTCLKs

NOTES:

DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.

DSCLK-to-DSO hold

PSTCLKs

DSCLK cycle time

PSTCLKs

PSTCLK

PSTDDATA[7:0]

Past

Current

DSCLK

DSI

DSO

Current

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

DSPI Electrical Specifications

Freescale Semiconductor

DSPI Electrical Specifications

Table 24

lists DSPI timings.

The values in

Table 24

correspond to

Figure 26

Figure 26. DSPI Timing

Timer Module AC Timing Specifications

Table 25

lists timer module AC timings.

Table 24. DSPI Modules AC Timing Specifications

Name

Characteristic Min

Max

Unit

DS1

DSPI_CS[3:0] to DSPI_CLK

× tck

510

× tck

DS2

DSPI_CLK high to DSPI_DOUT valid.

DS3

DSPI_CLK high to DSPI_DOUT invalid. (Output hold)

DS4

DSPI_DIN to DSPI_CLK (Input setup)

DS5

DSPI_DIN to DSPI_CLK (Input hold)

Table 25. Timer Module AC Timing Specifications

Name

Characteristic

066 MHz

Unit

Min

Max

TIN0 / TIN1 / TIN2 / TIN3 cycle time

PSTCLK

TIN0 / TIN1 / TIN2 / TIN3 pulse width

PSTCLK

DSPI_CS[3:0]

DSPI_CLK

DSPI_DOUT

DSPI_DIN

DS5

DS4

DS1

DS2

DS3

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MCF5485EC
Rev. 2.1
12/2004

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Document Outline

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Document Outline

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