Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Freescale Semiconductor
Technical Data
The MPC8343EA contains a PowerPCTM processor core
(built on Power ArchitectureTM technology) with system
logic for networking, storage, and general-purpose
embedded applications. For functional characteristics of the
processor, refer to the MPC8349EA PowerQUICCTM II Pro
Integrated Host Processor Reference Manual, Rev. 0.
To locate published errata or updates for this document,
contact your Freescale sales office.
NOTE
The information in this document is accurate
for revision 3.x silicon and later (in other
words, for devices with part numbers ending
in A or B, such as the MPC8343EA or
MPC8343EB). For information on revision
1.1 silicon and earlier versions
(MPC8343E/MPC8343), see the
PowerQUICCTM II Pro Integrated Host
Processor Hardware Specifications.
See
Section 23.1, "Part Numbers Fully
Addressed by this Document,"
for silicon
revision level determination.
MPC8343EAEC
Rev. 3, 11/2006
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Ethernet: Three-Speed Ethernet, MII Management . 24
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
21. System Design Information . . . . . . . . . . . . . . . . . . . 81
22. Document Revision History . . . . . . . . . . . . . . . . . . . 86
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 86
MPC8343EA PowerQUICCTM II Pro
Integrated Host Processor Hardware
Specifications
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
2
Freescale Semiconductor
Overview
1
Overview
This section provides a high-level overview of the MPC8343EA features.
Figure 1
shows the major
functional units within the MPC8343EA.
Figure 1. MPC8343EA Block Diagram
Major features of the MPC8343EA are as follows:
Embedded PowerPC e300 processor core; operates at up to 400 MHz
-- High-performance, superscalar processor core
-- Floating-point, integer, load/store, system register, and branch processing units
-- 32-Kbyte instruction cache, 32-Kbyte data cache
-- Lockable portion of L1 cache
-- Dynamic power management
-- Software-compatible with the other Freescale processor families that implement the PowerPC
architecture
Double data rate, DDR1/DDR2 SDRAM memory controller
-- Programmable timing supporting DDR1 and DDR2 SDRAM
-- 32- bit data interface, up to 266 MHz data rate
-- Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
-- DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
-- Full error checking and correction (ECC) support
-- Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
-- Contiguous or discontiguous memory mapping
-- Read-modify-write support
-- Sleep-mode support for SDRAM self refresh
-- Auto refresh
DUART
Dual I
2
C
Timers
GPIO
Security
Interrupt
Controller
Dual
Role
High-Speed
Local Bus
DDR
SDRAM
Controller
32KB
D-Cache
e300 Core
32KB
I-Cache
USB 2.0
10/100/1000
SEQ
PCI DMA
Ethernet
10/100/1000
Ethernet
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
3
Overview
-- On-the-fly power management using CKE
-- Registered DIMM support
-- 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
-- Dual controllers designed to comply with IEEE Std. 802.3TM, 802.3u, 820.3x, 802.3z, 802.3ac
-- Ethernet physical interfaces:
1000 Mbps IEEE Std. 802.3 RGMII, IEEE Std. 802.3z RTBI, full-duplex
10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
-- Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
-- 9.6-Kbyte jumbo frame support
-- RMON statistics support
-- Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
-- MII management interface for control and status
-- Programmable CRC generation and checking
PCI interface
-- Designed to comply with PCI specification revision 2.3
-- Data bus width:
32-bit data PCI interface operating at up to 66 MHz
-- PCI 3.3-V compatible
-- PCI host bridge capabilities
-- PCI agent mode on PCI interface
-- PCI-to-memory and memory-to-PCI streaming
-- Memory prefetching of PCI read accesses and support for delayed read transactions
-- Posting of processor-to-PCI and PCI-to-memory writes
-- On-chip arbitration supporting five masters on PCI
-- Accesses to all PCI address spaces
-- Parity supported
-- Selectable hardware-enforced coherency
-- Address translation units for address mapping between host and peripheral
-- Dual address cycle for target
-- Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11iTM, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
-- Public key execution unit (PKEU) :
RSA and Diffie-Hellman algorithms
Programmable field size up to 2048 bits
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
Elliptic curve cryptography
F2m and F(p) modes
Programmable field size up to 511 bits
-- Data encryption standard (DES) execution unit (DEU)
DES and 3DES algorithms
Two key (K1, K2) or three key (K1, K2, K3) for 3DES
ECB and CBC modes for both DES and 3DES
-- Advanced encryption standard unit (AESU)
Implements the Rijndael symmetric-key cipher
Key lengths of 128, 192, and 256 bits
ECB, CBC, CCM, and counter (CTR) modes
-- XOR parity generation accelerator for RAID applications
-- ARC four execution unit (AFEU)
Stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
-- Message digest execution unit (MDEU)
SHA with 160-, 224-, or 256-bit message digest
MD5 with 128-bit message digest
HMAC with either algorithm
-- Random number generator (RNG)
-- Four crypto-channels, each supporting multi-command descriptor chains
Static and/or dynamic assignment of crypto-execution units through an integrated controller
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Universal serial bus (USB) dual role controller
-- USB on-the-go mode with both device and host functionality
-- Complies with USB specification Rev. 2.0
-- Can operate as a stand-alone USB device
One upstream facing port
Six programmable USB endpoints
-- Can operate as a stand-alone USB host controller
USB root hub with one downstream-facing port
Enhanced host controller interface (EHCI) compatible
High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
-- External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
Local bus controller (LBC)
-- Multiplexed 32-bit address and data operating at up to 133 MHz
-- Eight chip selects for eight external slaves
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
5
Overview
-- Up to eight-beat burst transfers
-- 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
-- Three protocol engines on a per chip select basis:
General-purpose chip select machine (GPCM)
Three user-programmable machines (UPMs)
Dedicated single data rate SDRAM controller
-- Parity support
-- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
-- Functional and programming compatibility with the MPC8260 interrupt controller
-- Support for 8 external and 35 internal discrete interrupt sources
-- Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
-- Programmable highest priority request
-- Four groups of interrupts with programmable priority
-- External and internal interrupts directed to host processor
-- Redirects interrupts to external INTA pin in core disable mode.
-- Unique vector number for each interrupt source
Dual industry-standard I
2
C interfaces
-- Two-wire interface
-- Multiple master support
-- Master or slave I
2
C mode support
-- On-chip digital filtering rejects spikes on the bus
-- System initialization data optionally loaded from I
2
C-1 EPROM by boot sequencer embedded
hardware
DMA controller
-- Four independent virtual channels
-- Concurrent execution across multiple channels with programmable bandwidth control
-- Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
-- All channels accessible to local core and remote PCI masters
-- Misaligned transfer capability
-- Data chaining and direct mode
-- Interrupt on completed segment and chain
DUART
-- Two 4-wire interfaces (RxD, TxD, RTS, CTS)
-- Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI) for master or slave
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