Freescale Semiconductor

Technical Data

This document contains detailed information for the MPC852T
about power considerations, DC/AC electrical characteristics, AC
timing specifications, and pertinent electrical and physical
characteristics of the MPC852T. For information about functional
characteristics of the processor, refer to the MPC866
PowerQUICC Family Users Manual (MPC866UM). The
MPC852T contains a PowerPC

processor core.

1 Overview

The MPC852T PowerQUICC

is a 0.18-micron derivative of

the MPC860 PowerQUICC family, and can operate up to 100
MHz on the MPC8xx core with a 66-MHz external bus. The
MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V
TTL compatibility. The MPC852T integrated communications
controller is a versatile one-chip integrated microprocessor and
peripheral combination that can be used in a variety of controller
applications. It particularly excels in Ethernet control applications,
including CPE equipment, Ethernet routers and hubs, VoIP clients,
and WiFi access points.

The MPC852T is a PowerPC architecture-based derivative of the
Motorola MPC860 Quad Integrated Communications Controller
(PowerQUICC). The CPU on the MPC852T is the MPC8xx core,
a 32-bit microprocessor that implements the PowerPC
architecture, incorporating memory management units (MMUs)
and instruction and data caches. The MPC852T is the subset of
this family of devices.

MPC852TEC

Rev. 3.1, 01/2005

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7. Thermal Calculation and Measurement . . . . . . . . . . . 8
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9. Power Supply and Power Sequencing . . . . . . . . . . . 10

10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 11
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 56
16. Mechanical Data and Ordering Information . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 78

MPC852T

Hardware Specifications

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Features

2 Features

The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system
integration unit (SIU), and the communication processor module (CPM).

Figure 1

shows the MPC852T block

diagram.

The following list summarizes the key MPC852T features:

Embedded MPC8xx core up to 100 MHz

Maximum frequency operation of the external bus is 66 MHz
-- The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
-- The 80 MHz / 100 MHz core frequencies support 2:1 mode only.

Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit
general-purpose registers (GPRs)
-- The core performs branch prediction with conditional prefetch, without conditional execution.
-- 4-Kbyte data cache and 4-Kbyte instruction cache

4-Kbyte instruction cache is two-way, set-associative with 128 sets.
4-Kbyte data cacheis two-way, set-associative with 128 sets.
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache

blocks.

Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and

are lockable on a cache block basis.

-- MMUs with 32-entry TLB, fully associative instruction, and data TLBs
-- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces,

and 16 protection groups

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

32 address lines

Memory controller (eight banks)
-- Contains complete dynamic RAM (DRAM) controller
-- Each bank can be a chip select or RAS to support a DRAM bank
-- Up to 30 wait states programmable per memory bank
-- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
-- DRAM controller-programmable to support most size and speed memory interfaces
-- Four CAS lines, four WE lines, and one OE line
-- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
-- Variable block sizes (32 Kbytes256 Mbytes)
-- Selectable write protection
-- On-chip bus arbitration logic

Fast Ethernet Controller (FEC)

General-purpose timers
-- Two 16-bit timers or one 32-bit timer
-- Gate mode can enable or disable counting.
-- Interrupt can be masked on reference match and event capture.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Features

System integration unit (SIU)
-- Bus monitor
-- Software watchdog
-- Periodic interrupt timer (PIT)
-- Clock synthesizer
-- Decrementer and time base
-- Reset controller
-- IEEE 1149.1 test access port (JTAG)

Interrupts
-- Seven external interrupt request (IRQ) lines
-- Seven port pins with interrupt capability
-- Eighteen internal interrupt sources
-- Programmable priority between SCCs
-- Programmable highest-priority request

Communications processor module (CPM)
-- RISC controller
-- Communication-specific commands (for example,

GRACEFUL STOP TRANSMIT

ENTER HUNT MODE

, and

RESTART TRANSMIT

)

-- Supports continuous mode transmission and reception on all serial channels
-- 8-Kbytes of dual-port RAM
-- 8 serial DMA (SDMA) channels
-- Three parallel I/O registers with open-drain capability

Two baud rate generators
-- Independent (can be connected toany SCC3/4 or SMC1)
-- Allows changes during operation
-- Autobaud support option

Two SCCs (serial communication controllers)
-- Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
-- HDLC/SDLC
-- HDLC bus (implements an HDLC-based local area network (LAN))
-- Universal asynchronous receiver transmitter (UART)
-- Totally transparent (bit streams)
-- Totally transparent (frame-based with optional cyclic redundancy check (CRC))

One SMC (serial management channels)
-- UART

One SPI (serial peripheral interface)
-- Supports master and slave modes
-- Supports multimaster operation on the same bus

PCMCIA interface
-- Master (socket) interface, release 2.1 compliant

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Features

-- Supports one independent PCMCIA socket; 8-memory or I/O windows supported

Debug interface
-- Eight comparators: four operate on instruction address, two operate on data address, and two operate on

data

-- Supports conditions: = < >
-- Each watchpoint can generate a break point internally.

Normal high and normal low power modes to conserve power

1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to

Table 5

for a listing of the 5-V

Tolerant pins.

Figure 1. MPC852T Block Diagram

Bus

System Interface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

Timers

Interrupt

Controllers

8-Kbyte

Dual-Port RAM

1 Virtual

System Functions

4-Kbyte

Instruction Cache

32-Entry ITLB

Instruction MMU

4-Kbyte

Data Cache

32-Entry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Controller

and Program

ROM

MPC8xx

Processor

Core

DMAs

FIFOs

10/100

MII

Base-T

Media Access

Serial Interface (NMSI)

Control

Fast Ethernet

Controller

PCMCIA-ATA Interface

Generators

2 Baud Rate

IDMA

Channels

DMA

8 Serial

SCC3

SCC4

SMC1

SPI

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Maximum Tolerated Ratings

3 Maximum Tolerated Ratings

This section provides the maximum tolerated voltage and temperature ranges for the MPC852T.

Table 1

provides

the maximum ratings and operating temperatures.

This device contains circuitry protecting against damage that high-static voltage or electrical fields cause; however,
Motorola recommends taking normal precautions to avoid application of any voltages higher than maximum-rated
voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (for example, either GND or V

). -- V

DDH.

4 Thermal Characteristics

Table 3

shows the thermal characteristics for the MPC852T.

Table 1. Maximum Tolerated Ratings

Rating

Symbol

Value

Unit

Supply voltage

The power supply of the device must start its ramp from 0.0 V.

DDL

(core

voltage)

0.3 to 3.4

DDH

(I/O voltage)

0.3 to 4

DDSYN

0.3 to 3.4

Difference
between V

DDL

DDSYN

100

Input voltage

Functional operating conditions are provided with the DC electrical specifications in

Table 5

Absolute maximum ratings are stress ratings only; functional operation at the maxima is not
guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V

DDH

. This restriction

applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage
greater than 2.5 V must not be applied to its inputs).

GND

0.3 to V

DDH

Storage temperature range

stg

55 to +150

Table 2. Operating Temperatures

Rating

Symbol

Value

Unit

Temperature

(standard)

Minimum temperatures are guaranteed as ambient temperature, T

. Maximum temperatures

are guaranteed as junction temperature, T

A(min)

j(max)

Temperature (extended)

A(min)

j(max)

100

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Power Dissipation

5 Power Dissipation

Table 4

provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1

mode, where CPU frequency is twice bus speed.

Table 3. MPC852T Thermal Resistance Data

Rating

Environment

Symbol

Value

Unit

Junction to ambient

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.

Natural convection

Single layer board (1s)

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal

C/W

Four layer board (2s2p)

JMA

Per JEDEC JESD51-6 with the board horizontal

Air flow (200 ft/min)

Single layer board (1s)

JMA

Four layer board (2s2p)

JMA

Junction to board

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Junction to case

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature. For exposed pad packages where the pad would be expected to be soldered, junction to
case thermal resistance is a simulated value from the junction to the exposed pad without contact
resistance.

Junction to package top

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2

Natural convection

Air flow (200 ft/min)

Table 4. Power Dissipation (P

)

Die Revision

Bus Mode

Frequency

(MHz)

Typical

Typical power dissipation is measured at 1.9 V.

Maximum

Unit

1:1

110

140

150

180

2:1

140

160

170

200

100

210

250

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

DC Characteristics

6 DC Characteristics

Table 5

provides the DC electrical characteristics for the MPC852T.

Maximum power dissipation at V

DDL

and V

DDSYN

is at 1.9 V. and V

DDH

is at 3.465 V.

NOTE

Values in

Table 4

represent V

DDL

-based power

dissipation, and do not include I/O power dissipation
over V

DDH

. I/O power dissipation varies widely by

application that buffer current can cause, depending
on external circuitry.

The V

DDSYN

power dissipation is negligible.

Table 5. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Unit

Operating voltage

DDH

3.135

3.465

DDL

1.7

1.9

DDSYN

1.7

1.9

Difference between V

DDL

DDSYN

100

Input high voltage (all inputs except
PA[0:3], PA[8:11], PB15, PB[24:25];
PB[28:31], PC[4:7], PC[12:13], PC15,
PD[3:15], TDI, TDO, TCK, TRST, TMS,
MII_TXEN, MII_MDIO)

2.0

3.465

Input low voltage

GND

0.8

EXTAL, EXTCLK input high voltage

IHC

0.7 V

DDH

Input leakage current, Vin = 5.5 V
(Except TMS, TRST, DSCK and DSDI
pins) for 5-V tolerant pins

100

Input leakage current, Vin = V

DDH

(Except TMS, TRST, DSCK, and DSDI)

Input leakage current, Vin = 0 V (Except
TMS, TRST, DSCK and DSDI pins)

Input capacitance

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Thermal Calculation and Measurement

7 Thermal Calculation and Measurement

For the following discussions, P

= (V

DDL

x IDDL) + P

I/O

, where P

I/O

is the power dissipation of the I/O drivers.

NOTE

The V

DDSYN

power dissipation is negligible.

7.1 Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, T

, in °C can be obtained from the equation:

= T

+(R

)

where:

= ambient temperature ºC

= package junction-to-ambient thermal resistance (ºC/W)

= power dissipation in package

Output high voltage, IOH = -2.0 mA,
V

DDH

= 3.0 V

Except XTAL and open drain pins

VOH

2.4

Output low voltage
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA

IOL = 5.3 mA

IOL = 7.0 mA (Txd1/pa14, txd2/pa12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB,
HRESET, SRESET)

VOL

0.5

The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO,

TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant pins.

Input capacitance is periodically sampled.

A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2,

IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CLK5/PA3,
BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31,
SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24,
BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6,
CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12,
MII-TXERR/RXD3/PD11, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8,
MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4,
MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL

BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR,

WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK,
OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)

Table 5. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Thermal Calculation and Measurement

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation
of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor
of two (in the quantity T

-T

) are possible.

7.2 Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:

= R

+ R

where:

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the

case-to-ambient thermal resistance, R

. For instance, the user can change the air flow around the device, add a

heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.

7.3 Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation
where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the
printed circuit board. Thermal performance of most plastic packages and especially PBGA packages is strongly
dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in
the environment can be made using the following equation:

= T

+(R

)

where:

= junction-to-board thermal resistance (ºC/W)

= board temperature ºC

= power dissipation in package

If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.

7.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor
model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the
package can be used in the thermal simulation.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

References

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (

) can be used to determine the junction temperature with a measurement of the

temperature at the top center of the package case using the following equation:

= T

)

where:

= thermal characterization parameter

= thermocouple temperature on top of package

= power dissipation in package

The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a
40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the
package case to avoid measurement errors that cooling effects of the thermocouple wire cause.

8 References

Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or
(Available from Global Engineering documents)303-397-7956

JEDEC Specifications http://www.jedec.org

1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

9 Power Supply and Power Sequencing

This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage
(V

DDL

) and PLL voltage (V

DDSYN

) that operates at a lower voltage than the I/O voltage V

DDH

. The I/O section of

the MPC852T is supplied with 3.3 V across V

DDH

and V

(GND).

The signal PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK,
TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant. All inputs cannot be more than 2.5 V greater than V

DDH

. In

addition, 5 V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This restriction
applies to power-on reset or power down and normal operation.

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mandatory Reset Configurations

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:

DDL

must not exceed V

DDH

during power-on reset or power down.

DDL

must not exceed 1.9 V, and V

DDH

must not exceed 3.465.

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge
(ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequencing, the circuit shown in

Figure 2

can be added to meet

these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external
bus and core power supplies on power-on reset, and the 1N5820 diodes regulate the maximum potential difference
on power-down.

Figure 2. Example Voltage Sequencing Circuit

10 Mandatory Reset Configurations

The MPC852T requires a mandatory configuration during reset.

If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET assertion,
the HRCW[DBGC] value that is needed to be set to binary X1 in the hardware reset configuration word (HRCW)
and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset.

If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET
assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset.

DDH

DDL

1N5820

MUR420

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Layout Practices

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the
mandatory value in

Table 6

in the boot code after the reset deasserts.

11 Layout Practices

Each V

pin on the MPC852T should be provided with a low-impedance path to the board's supply. Each GND

pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The V

power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors

located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip V

and GND should be kept to less than half an inch per capacitor lead. At a

minimum, a four-layer board employing two inner layers as V

and GND planes should be used.

All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized to minimize undershoot and reflections that these fast output switching times cause. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the
PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads, because these loads create higher transient currents in the V

and GND circuits. Pull up all unused

inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL

Table 6. Mandatory Reset Configuration of MPC852T

Register/Configuration

Field

Value

(binary)

HRCW
(Hardware reset configuration word)

HRCW[DBGC]

SIUMCR
(SIU module configuration register)

SIUMCR[DBGC]

MBMR
(Machine B mode register)

MBMR[GPLB4DIS}

PAPAR
(Port A pin assignment register)

PAPAR[4-7]
PAPAR[12-15]

PADIR
(Port A Data Direction Register)

PADIR[4-7]
PADIR[12-15]

PBPAR
(Port B Pin Assignment Register)

PBPAR[14]
PBPAR[16-23]
PBPAR[26-27]

PBDIR
(Port B Data Direction Register)

PBDIR[14]
PBDIR[16-23]
PBDIR[26-27]

PCPAR
(Port C Pin Assignment Register)

PCPAR[8-11]
PCDIR[14]

PCDIR
(Port C Data Direction Register)

PCDIR[8-11]
PCDIR[14]

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

supply pins. For more information, please refer to MPC866 User's Manual, Section 14.4.3, "Clock Synthesizer
Power (V

DDSYN

, V

SSSYN

, V

SSSYN1

)."

12 Bus Signal Timing

The maximum bus speed that the MPC852T supports is 66 MHz.

Table 7

shows the frequency ranges for standard

part frequencies.

Table 9

provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz.

The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay

Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)

Part

Freq

50MHz

66MHz

Min

Max

Min

Max

Core
Freq

66.67

Bus Freq

66.67

Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)

Part

Freq

50MHz

66MHz

80MHz

100MHz

Min

Max

Min

Max

Min

Max

Min

Max

Core
Freq

66.67

100

Bus Freq
2:1

33.33

Table 9. Bus Operation Timings

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Bus period (CLKOUT) See

Table 7

B1a

EXTCLK to CLKOUT phase skew - If CLKOUT
is an integer multiple of EXTCLK, then the
rising edge of EXTCLK is aligned with the
rising edge of CLKOUT. For a non-integer
multiple of EXTCLK, this synchronization is
lost, and the rising edges of EXTCLK and
CLKOUT have a continuously varying phase
skew.

-2

B1b

CLKOUT frequency jitter peak-to-peak

B1c

Frequency jitter on EXTCLK

0.50

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B1d

CLKOUT phase jitter peak-to-peak
for OSCLK 15 MHz

CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz

CLKOUT pulse width low (MIN = 0.4 x B1, MAX
= 0.6 x B1)

12.1

18.2

10.0

15.0

8.0

12.0

6.1

9.1

CLKOUT pulse width high (MIN = 0.4 x B1,
MAX = 0.6 x B1)

12.1

18.2

10.0

15.0

8.0

12.0

6.1

9.1

CLKOUT rise time

4.00

CLKOUT fall time

4.00

CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3) output hold (MIN =
0.25 x B1)

7.60

6.30

5.00

3.80

B7a

CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR
output hold (MIN = 0.25 x B1)

7.60

6.30

5.00

3.80

B7b

CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2)
IWP(0:2), LWP(0:1), STS output hold (MIN =
0.25 x B1)

7.60

6.30

5.00

3.80

CLKOUT to A(0:31), BADDR(28:30) RD/WR,
BURST, D(0:31), DP(0:3) valid (MAX = 0.25 x
B1 + 6.3)

13.80

12.50

11.30

10.00

B8a

CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR
valid (MAX = 0.25 x B1 + 6.3)

13.80

12.50

11.30

10.00

B8b

CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1), STS Valid

(MAX =

0.25 x B1 + 6.3)

13.80

12.50

11.30

10.00

CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3), TSIZ(0:1), REG,
RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

B11

CLKOUT to TS, BB assertion (MAX = 0.25 x B1
+ 6.0)

7.60

13.60

6.30

12.30

5.00

11.00

3.80

9.80

B11a CLKOUT to TA, BI assertion (when driven by

the memory controller or PCMCIA interface)
(MAX = 0.00 x B1 + 9.30

)

2.50

9.30

2.50

9.30

2.50

9.30

2.50

9.80

B12

CLKOUT to TS, BB negation (MAX = 0.25 x B1
+ 4.8)

7.60

12.30

6.30

11.00

5.00

9.80

3.80

8.50

B12a CLKOUT to TA, BI negation (when driven by

the memory controller or PCMCIA interface)
(MAX = 0.00 x B1 + 9.00)

2.50

9.00

2.50

9.00

2.50

9.00

2.50

9.00

B13

CLKOUT to TS, BB High-Z (MIN = 0.25 x B1)

7.60

21.60

6.30

20.30

5.00

19.00

3.80

14.00

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B13a CLKOUT to TA, BI High-Z (when driven by the

memory controller or PCMCIA interface) (MIN
= 0.00 x B1 + 2.5)

2.50

15.00

2.50

15.00

2.50

15.00

2.50

15.00

B14

CLKOUT to TEA assertion (MAX = 0.00 x B1 +
9.00)

2.50

9.00

2.50

9.00

2.50

9.00

2.50

9.00

B15

CLKOUT to TEA High-Z (MIN = 0.00 x B1 +
2.50)

2.50

15.00

2.50

15.00

2.50

15.00

2.50

15.00

B16

TA, BI valid to CLKOUT (setup time) (MIN =
0.00 x B1 + 6.00)

6.00

B16a TEA, KR, RETRY, CR valid to CLKOUT (setup

time) (MIN = 0.00 x B1 + 4.5)

4.50

B16b BB, BG, BR, valid to CLKOUT (setup time)

(4MIN = 0.00 x B1 +.000)

4.00

B17

CLKOUT to TA, TEA, BI, BB, BG, BR valid
(hold time) (MIN = 0.00 x B1 + 1.00

)

1.00

2.00

B17a CLKOUT to KR, RETRY, CR valid (hold time)

(MIN = 0.00 x B1 + 2.00)

2.00

B18

D(0:31), DP(0:3) valid to CLKOUT rising edge
(setup time)

(MIN = 0.00 x B1 + 6.00)

6.00

B19

CLKOUT rising edge to D(0:31), DP(0:3) valid
(hold time)

(MIN = 0.00 x B1 + 1.00

)

1.00

2.00

B20

D(0:31), DP(0:3) valid to CLKOUT falling edge
(setup time)

(MIN = 0.00 x B1 + 4.00)

4.00

B21

CLKOUT falling edge to D(0:31), DP(0:3) valid
(hold Time)

(MIN = 0.00 x B1 + 2.00)

2.00

B22

CLKOUT rising edge to CS asserted GPCM
ACS = 00 (MAX = 0.25 x B1 + 6.3)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

B22a CLKOUT falling edge to CS asserted GPCM

ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00)

8.00

B22b CLKOUT falling edge to CS asserted GPCM

ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x
B1 + 6.3)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

B22c CLKOUT falling edge to CS asserted GPCM

ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375
x B1 + 6.6)

10.90

18.00

10.90

16.00

7.00

14.10

5.20

12.30

B23

CLKOUT rising edge to CS negated GPCM
read access, GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 +
8.00)

2.00

8.00

2.00

8.00

2.00

8.00

2.00

8.00

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B24

A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1
- 2.00)

5.60

4.30

3.00

1.80

B24a A(0:31) and BADDR(28:30) to CS asserted

GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 -
2.00)

13.20

10.50

8.00

5.60

B25

CLKOUT rising edge to OE,
WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1
+ 9.00)

9.00

B26

CLKOUT rising edge to OE negated (MAX =
0.00 x B1 + 9.00)

2.00

9.00

2.00

9.00

2.00

9.00

2.00

9.00

B27

A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1
- 2.00)

35.90

29.30

23.00

16.90

B27a A(0:31) and BADDR(28:30) to CS asserted

GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 -
2.00)

43.50

35.50

28.00

20.70

B28

CLKOUT rising edge to WE(0:3)/BS_B[0:3]
negated GPCM write access CSNT = 0 (MAX
= 0.00 x B1 + 9.00)

9.00

B28a CLKOUT falling edge to WE(0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,1
CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80)

7.60

14.30

6.30

13.00

5.00

11.80

3.80

10.50

B28b CLKOUT falling edge to CS negated GPCM

write access TRLX = 0,1 CSNT = 1 ACS = 10
or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 +
6.80)

14.30

13.00

11.80

10.50

B28c CLKOUT falling edge to WE(0:3)/BS_B[0:3]

negated GPCM write access TRLX = 0,1
CSNT = 1 write access TRLX = 0,1 CSNT = 1,
EBDF = 1 (MAX = 0.375 x B1 + 6.6)

10.90

18.00

10.90

18.00

7.00

14.30

5.20

12.30

B28d CLKOUT falling edge to CS negated GPCM

write access TRLX = 0,1 CSNT = 1, ACS = 10,
or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 +
6.6)

18.00

14.30

12.30

B29

WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access, CSNT =
0, EBDF = 0 (MIN = 0.25 x B1 - 2.00)

5.60

4.30

3.00

1.80

B29a WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00)

13.20

10.50

8.00

5.60

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B29b CS negated to D(0:31), DP(0:3), High Z GPCM

write access, ACS = 00, TRLX = 0,1 & CSNT =
0 (MIN = 0.25 x B1 - 2.00)

5.60

4.30

3.00

1.80

B29c CS negated to D(0:31), DP(0:3) High-Z GPCM

write access, TRLX = 0, CSNT = 1, ACS = 10,
or ACS = 11 EBDF = 0 (MIN = 0.50 x B1 - 2.00)

13.20

10.50

8.00

5.60

B29d WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00)

43.50

35.50

28.00

20.70

B29e CS negated to D(0:31), DP(0:3) High-Z GPCM

write access, TRLX = 1, CSNT = 1, ACS = 10,
or ACS = 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00)

43.50

35.50

28.00

20.70

B29f WE(0:3/BS_B[0:3]) negated to D(0:31),

DP(0:3) High Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 6.30)

5.00

3.00

1.10

0.00

B29g CS negated to D(0:31), DP(0:3) High-Z GPCM

write access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30)

5.00

3.00

1.10

0.00

B29h WE(0:3)/BS_B[0:3] negated to D(0:31),

DP(0:3) High Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 3.30)

38.40

31.10

24.20

17.50

B29i CS negated to D(0:31), DP(0:3) High-Z GPCM

write access, TRLX = 1, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 -
3.30)

38.40

31.10

24.20

17.50

B30

CS, WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) Invalid GPCM write access

(MIN = 0.25 x B1 - 2.00)

5.60

4.30

3.00

1.80

B30a WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) Invalid GPCM, write access,
TRLX = 0, CSNT = 1, CS negated to A(0:31)
invalid GPCM write access TRLX = 0, CSNT
=1 ACS = 10, or ACS == 11, EBDF = 0 (MIN =
0.50 x B1 - 2.00)

13.20

10.50

8.00

5.60

B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid

GPCM BADDR(28:30) invalid GPCM write
access, TRLX = 1, CSNT = 1. CS negated to
A(0:31) Invalid GPCM write access TRLX = 1,
CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0
(MIN = 1.50 x B1 - 2.00)

43.50

35.50

28.00

20.70

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B30c WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write access,
TRLX = 0, CSNT = 1. CS negated to A(0:31)
invalid GPCM write access, TRLX = 0, CSNT =
1 ACS = 10, ACS == 11, EBDF = 1 (MIN =
0.375 x B1 - 3.00)

8.40

6.40

4.50

2.70

B30d WE(0:3)/BS_B[0:3] negated to A(0:31),

BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to A(0:31)
invalid GPCM write access TRLX = 1, CSNT =
1, ACS = 10 or 11, EBDF = 1

38.67

31.38

24.50

17.83

B31

CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word in the UPM (MAX = 0.00 X
B1 + 6.00)

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B31a CLKOUT falling edge to CS valid - as

requested by control bit CST1 in the
corresponding word in the UPM (MAX = 0.25 x
B1 + 6.80)

7.60

14.30

6.30

13.00

5.00

11.80

3.80

10.50

B31b CLKOUT rising edge to CS valid - as requested

by control bit CST2 in the corresponding word
in the UPM (MAX = 0.00 x B1 + 8.00)

1.50

8.00

1.50

8.00

1.50

8.00

1.50

8.00

B31c CLKOUT rising edge to CS valid- as requested

by control bit CST3 in the corresponding word
in the UPM (MAX = 0.25 x B1 + 6.30)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

B31d CLKOUT falling edge to CS valid, as requested

by control bit CST1 in the corresponding word
in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6)

13.30

18.00

11.30

16.00

9.40

14.10

7.60

12.30

B32

CLKOUT falling edge to BS valid- as requested
by control bit BST4 in the corresponding word
in the UPM (MAX = 0.00 x B1 + 6.00)

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B32a CLKOUT falling edge to BS valid - as

requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 x B1 + 6.80)

7.60

14.30

6.30

13.00

5.00

11.80

3.80

10.50

B32b CLKOUT rising edge to BS valid - as requested

by control bit BST2 in the corresponding word
in the UPM (MAX = 0.00 x B1 + 8.00)

1.50

8.00

1.50

8.00

1.50

8.00

1.50

8.00

B32c CLKOUT rising edge to BS valid - as requested

by control bit BST3 in the corresponding word
in the UPM (MAX = 0.25 x B1 + 6.80)

7.60

14.30

6.30

13.00

5.00

11.80

3.80

10.50

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B32d CLKOUT falling edge to BS valid- as requested

by control bit BST1 in the corresponding word
in the UPM, EBDF = 1 (MAX = 0.375 x B1 +
6.60)

13.30

18.00

11.30

16.00

9.40

14.10

7.60

12.30

B33

CLKOUT falling edge to GPL valid - as
requested by control bit GxT4 in the
corresponding word in the UPM (MAX = 0.00 x
B1 + 6.00)

1.50

6.00

1.50

6.00

1.50

6.00

1.50

6.00

B33a CLKOUT rising edge to GPL Valid - as

requested by control bit GxT3 in the
corresponding word in the UPM (MAX = 0.25 x
B1 + 6.80)

7.60

14.30

6.30

13.00

5.00

11.80

3.80

10.50

B34 A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by control bit CST4 in the
corresponding word in the UPM (MIN = 0.25 x
B1 - 2.00)

5.60

4.30

3.00

1.80

B34a A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by control bit CST1 in the
corresponding word in the UPM (MIN = 0.50 x
B1 - 2.00)

13.20

10.50

8.00

5.60

B34b A(0:31), BADDR(28:30), and D(0:31) to CS

valid - as requested by CST2 in the
corresponding word in UPM (MIN = 0.75 x B1 -
2.00)

20.70

16.70

13.00

9.40

B35

A(0:31), BADDR(28:30) to CS valid - as
requested by control bit BST4 in the
corresponding word in the UPM (MIN = 0.25 x
B1 - 2.00)

5.60

4.30

3.00

1.80

B35a A(0:31), BADDR(28:30), and D(0:31) to BS

valid - As Requested by BST1 in the
corresponding word in the UPM (MIN = 0.50 x
B1 - 2.00)

13.20

10.50

8.00

5.60

B35b A(0:31), BADDR(28:30), and D(0:31) to BS

valid - as requested by control bit BST2 in the
corresponding word in the UPM (MIN = 0.75 x
B1 - 2.00)

20.70

16.70

13.00

9.40

B36

A(0:31), BADDR(28:30), and D(0:31) to GPL
valid as requested by control bit GxT4 in the
corresponding word in the UPM (MIN = 0.25 x
B1 - 2.00)

5.60

4.30

3.00

1.80

B37

UPWAIT valid to CLKOUT falling edge

(MIN

= 0.00 x B1 + 6.00)

6.00

B38

CLKOUT falling edge to UPWAIT valid

(MIN

= 0.00 x B1 + 1.00)

1.00

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

B39

AS valid to CLKOUT rising edge

(MIN = 0.00

x B1 + 7.00)

7.00

B40

A(0:31), TSIZ(0:1), RD/WR, BURST, valid to
CLKOUT rising edge (MIN = 0.00 x B1 + 7.00)

7.00

B41

TS valid to CLKOUT rising edge (setup time)
(MIN = 0.00 x B1 + 7.00)

7.00

B42

CLKOUT rising edge to TS valid (hold time)
(MIN = 0.00 x B1 + 2.00)

2.00

B43

AS negation to memory controller signals
negation (MAX = TBD)

TBD

If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values

in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum
allowed jitter on EXTAL can be up to 2%.

For part speeds above 50MHz, use 9.80ns for B11a.

The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for

BG input is relevant when the MPC852T is selected to work with external bus arbiter.

For part speeds above 50MHz, use 2ns for B17.

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is

asserted.

For part speeds above 50MHz, use 2ns for B19.

The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read

accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37

and B38 are specified to enable the freeze of the UPM output signals as described in

Figure 18

The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified

Figure 21

Table 9. Bus Operation Timings (continued)

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Figure 20

provides the timing for the synchronous external master access that the GPCM controls.

Figure 20. Synchronous External Master Access Timing (GPCM Handled ACS = 00)

Figure 21

provides the timing for the asynchronous external master memory access that the GPCM controls.

Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled

ACS = 00)

Figure 22

provides the timing for the asynchronous external master control signals negation.

Figure 22. Asynchronous External Master

Control Signals Negation Timing

CLKOUT

A[0:31],

TSIZ[0:1],

R/W, BURST

CSx

B41

B42

B40

B22

CLKOUT

A[0:31],

TSIZ[0:1],

R/W

CSx

B39

B40

B22

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

B43

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Table 10

provides interrupt timing for the MPC852T.

Figure 23

provides the interrupt detection timing for the external level-sensitive lines.

Figure 23. Interrupt Detection Timing for External Level Sensitive Lines

Figure 24

provides the interrupt detection timing for the external edge-sensitive lines.

Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines

Table 10. Interrupt Timing

Num

Characteristic

The timings I39 and I40 describe the testing conditions under which the IRQ

lines are tested when being defined as level-sensitive. The IRQ lines are
synchronized internally and need not be asserted or negated with reference to
the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the
IRQ lines detection circuitry, and have no direct relation with the total system
interrupt latency that the MPC852T is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (set
up time)

6.00

I40

IRQx hold time after CLKOUT

2.00

I41

IRQx pulse width low

3.00

I42

IRQx pulse width high

3.00

I43

IRQx edge-to-edge time

4xT

CLOCKOUT

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Table 11

shows the PCMCIA timing for the MPC852T.

Table 11. PCMCIA Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

J82

A(0:31), REG valid to PCMCIA Strobe
asserted.

(MIN = 0.75 x B1 - 2.00)

PSST = 1. Otherwise add PSST times cycle time.

PSHT = 0. Otherwise add PSHT times cycle time.

These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current
cycle. The WAITA assertion is effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface
in the MPC852T PowerQUICC User s Manual.

20.70

16.70

13.00

9.40

J83

A(0:31), REG valid to ALE negation.

(MIN =

1.00 x B1 - 2.00)

28.30

23.00

18.00

13.20

J84

CLKOUT to REG valid (MAX = 0.25 x B1 +
8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

J85

CLKOUT to REG Invalid. (MIN = 0.25 x B1 +
1.00)

8.60

7.30

6.00

4.80

J86

CLKOUT to CE1, CE2 asserted. (MAX =
0.25 x B1 + 8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

J87

CLKOUT to CE1, CE2 negated. (MAX =
0.25 x B1 + 8.00)

7.60

15.60

6.30

14.30

5.00

13.00

3.80

11.80

J88

CLKOUT to PCOE, IORD, PCWE, IOWR
assert time. (MAX = 0.00 x B1 + 11.00)

11.00

J89

CLKOUT to PCOE, IORD, PCWE, IOWR
negate time. (MAX = 0.00 x B1 + 11.00)

2.00

11.00

2.00

11.00

2.00

11.00

2.00

11.00

J90

CLKOUT to ALE assert time (MAX = 0.25 x
B1 + 6.30)

7.60

13.80

6.30

12.50

5.00

11.30

3.80

10.00

J91

CLKOUT to ALE negate time (MAX = 0.25 x
B1 + 8.00)

15.60

14.30

13.00

11.80

J92

PCWE, IOWR negated to D(0:31) invalid.

(MIN = 0.25 x B1 - 2.00)

5.60

4.30

3.00

1.80

J93

WAITA and WAITB valid to CLKOUT rising
edge.

(MIN = 0.00 x B1 + 8.00)

8.00

J94

CLKOUT rising edge to WAITA and WAITB
invalid.

(MIN = 0.00 x B1 + 2.00)

2.00

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Table 12

shows the PCMCIA port timing for the MPC852T.

Figure 28

provides the PCMCIA output port timing for the MPC852T.

Figure 28. PCMCIA Output Port Timing

Figure 29

provides the PCMCIA output port timing for the MPC852T.

Figure 29. PCMCIA Input Port Timing

Table 12. PCMCIA Port Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

J95

CLKOUT to OPx Valid (MAX = 0.00 x B1 +
19.00)

19.00

J96

HRESET negated to OPx drive

(MIN = 0.75 x

B1 + 3.00)

OP2 and OP3 only.

25.70

21.70

18.00

14.40

J97

IP_Xx valid to CLKOUT rising edge (MIN = 0.00
x B1 + 5.00)

5.00

J98

CLKOUT rising edge to IP_Xx invalid (MIN =
0.00 x B1 + 1.00)

1.00

CLKOUT

HRESET

Output

Signals

OP2, OP3

P57

P58

CLKOUT

Input

Signals

P59

P60

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Table 13

shows the debug port timing for the MPC852T.

Figure 30

provides the input timing for the debug port clock.

Figure 30. Debug Port Clock Input Timing

Figure 31

provides the timing for the debug port.

Figure 31. Debug Port Timings

Table 13. Debug Port Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

J82

DSCK cycle time

3xT

CLOCKOUT

J83

DSCK clock pulse width

1.25xT

CLOCKOUT

J84

DSCK rise and fall times

0.00

3.00

J85

DSDI input data setup time

8.00

J86

DSDI data hold time

5.00

J87

DSCK low to DSDO data valid

0.00

15.00

J88

DSCK low to DSDO invalid

0.00

2.00

DSCK

D61

D63

D62

D63

DSCK

DSDI

DSDO

D64

D65

D66

D67

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Bus Signal Timing

Table 14

shows the reset timing for the MPC852T.

Table 14. Reset Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

J82

CLKOUT to HRESET high impedance (MAX =
0.00 x B1 + 20.00)

20.00

J83

CLKOUT to SRESET high impedance (MAX =
0.00 x B1 + 20.00)

20.00

J84 RSTCONF pulse width (MIN = 17.00 x B1)

515.20

425.00

340.00

257.60

J85

J86

Configuration data to HRESET rising edge set
up time (MIN = 15.00 x B1 + 50.00)

504.50

425.00

350.00

277.30

J87

Configuration data to RSTCONF rising edge set
up time (MIN = 0.00 x B1 + 350.00)

350.00

J88

Configuration data hold time after RSTCONF
negation (MIN = 0.00 x B1 + 0.00)

0.00

J89

Configuration data hold time after HRESET
negation (MIN = 0.00 x B1 + 0.00)

0.00

J90

HRESET and RSTCONF asserted to data out
drive (MAX = 0.00 x B1 + 25.00)

25.00

J91

RSTCONF negated to data out high impedance.
(MAX = 0.00 x B1 + 25.00)

25.00

J92

CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance. (MAX = 0.00 x B1 + 25.00)

25.00

J93 DSDI, DSCK set up (MIN = 3.00 x B1)

90.90

75.00

60.00

45.50

J94 DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00)

0.00

J95

SRESET negated to CLKOUT rising edge for
DSDI and DSCK sample (MIN = 8.00 x B1)

242.40

200.00

160.00

121.20

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

IEEE 1149.1 Electrical Specifications

Figure 34

provides the reset timing for the debug port configuration.

Figure 34. Reset Timing

Debug Port Configuration

13 IEEE 1149.1 Electrical Specifications

Table 15

provides the JTAG timings for the MPC852T shown in

Figure 35

through

Figure 38

Table 15. JTAG Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

J82

TCK cycle time

100.00

J83

TCK clock pulse width measured at 1.5 V

40.00

J84

TCK rise and fall times

0.00

10.00

J85

TMS, TDI data setup time

5.00

J86

TMS, TDI data hold time

25.00

J87

TCK low to TDO data valid

27.00

J88

TCK low to TDO data invalid

0.00

J89

TCK low to TDO high impedance

20.00

J90

TRST assert time

100.00

J91

TRST setup time to TCK low

40.00

J92

TCK falling edge to output valid

50.00

J93

TCK falling edge to output valid out of high impedance

50.00

J94

TCK falling edge to output high impedance

50.00

J95

Boundary scan input valid to TCK rising edge

50.00

J96

TCK rising edge to boundary scan input invalid

50.00

CLKOUT

SRESET

DSCK, DSDI

R70

R82

R80

R81

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

Figure 38. Boundary Scan (JTAG) Timing Diagram

14 CPM Electrical Characteristics

This section provides the AC and DC electrical specifications for the communications processor module (CPM) of
the MPC852T.

14.1 Port C Interrupt AC Electrical Specifications

Table 16

provides the timings for port C interrupts.

Figure 39

shows the port C interrupt detection timing.

Figure 39. Port C Interrupt Detection Timing

Table 16. Port C Interrupt Timing

Num

Characteristic

33.34 MHz

Unit

Min

Max

Port C interrupt pulse width low (edge-triggered mode)

Port C interrupt minimum time between active edges

TCK

Output

Signals

Output

Signals

Output

Signals

J92

J94

J93

J95

J96

Port C

(Input)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

14.2 IDMA Controller AC Electrical Specifications

Table 17

provides the IDMA controller timings as shown in

Figure 40

through

Figure 43

Figure 40. IDMA External Requests Timing Diagram

Table 17. IDMA Controller Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

DREQ setup time to clock high

DREQ hold time from clock high

Applies to high-to-low mode (EDM=1)

SDACK assertion delay from clock high

SDACK negation delay from clock low

SDACK negation delay from TA low

SDACK negation delay from clock high

TA assertion to falling edge of the clock setup time (applies to external TA)

DREQ
(Input)

CLKO

(Output)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

14.4 Timer AC Electrical Specifications

Table 19

provides the general-purpose timer timings as shown in

Figure 45

Figure 45. CPM General-Purpose Timers Timing Diagram

14.5 SCC in NMSI Mode Electrical Specifications

Table 20

provides the NMSI external clock timing.

Table 19. Timer Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

TIN/TGATE rise and fall time

TIN/TGATE low time

clk

TIN/TGATE high time

clk

TIN/TGATE cycle time

clk

CLKO low to TOUT valid

Table 20. NMSI External Clock Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

100

RCLK3 and TCLK3 width high

1/SYNCCLK

101

RCLK3 and TCLK3 width low

1/SYNCCLK +5

102

RCLK3 and TCLK3 rise/fall time

15.00

103

TXD3 active delay (from TCLK3 falling edge)

0.00

50.00

104

RTS3 active/inactive delay (from TCLK3 falling edge)

0.00

50.00

105

CTS3 setup time to TCLK3 rising edge

5.00

CLKO

TIN/TGATE

(Input)

TOUT

(Output)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

Table 21

provides the NMSI internal clock timing.

106

RXD3 setup time to RCLK3 rising edge

5.00

107

RXD3 hold time from RCLK3 rising edge

5.00

108

CD3 setup Time to RCLK3 rising edge

5.00

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.

Also applies to CD and CTS hold time when they are used as an external sync signal.

Table 21. NMSI Internal Clock Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

100

RCLK3 and TCLK3 frequency

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.

0.00

SYNCCLK/3

MHz

102

RCLK3 and TCLK3 rise/fall time

103

TXD3 active delay (from TCLK3 falling edge)

0.00

30.00

104

RTS3 active/inactive delay (from TCLK3 falling edge)

0.00

30.00

105

CTS3 setup time to TCLK3 rising edge

40.00

106

RXD3 setup time to RCLK3 rising edge

40.00

107

RXD3 hold time from RCLK3 rising edge

Also applies to CD and CTS hold time when they are used as an external sync signals.

0.00

108

CD3 setup time to RCLK3 rising edge

40.00

Table 20. NMSI External Clock Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

Figure 48. HDLC Bus Timing Diagram

14.6 Ethernet Electrical Specifications

Table 22

provides the Ethernet timings as shown in

Figure 49

through

Figure 53

Table 22. Ethernet Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

120

CLSN width high

121

RCLK3 rise/fall time

122

RCLK3 width low

123

RCLK3 clock period

120

124

RXD3 setup time

125

RXD3 hold time

126

RENA active delay (from RCLK3 rising edge of the last data bit)

127

RENA width low

100

128

TCLK3 rise/fall time

129

TCLK3 width low

130

TCLK3 clock period

101

131

TXD3 active delay (from TCLK3 rising edge)

132

TXD3 inactive delay (from TCLK3 rising edge)

6.5

133

TENA active delay (from TCLK3 rising edge)

TCLK3

CTS3

(Echo Input)

102

100

104

TxD3

(Output)

102

101

RTS3

(Output)

103

104

107

105

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

Figure 49. Ethernet Collision Timing Diagram

Figure 50. Ethernet Receive Timing Diagram

134

TENA inactive delay (from TCLK3 rising edge)

135

RSTRT active delay (from TCLK3 falling edge)

136

RSTRT inactive delay (from TCLK3 falling edge)

137

REJECT width low

CLK

138

CLKO1 low to SDACK asserted

139

CLKO1 low to SDACK negated

The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.

SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

Table 22. Ethernet Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

CLSN(CTS1)

120

(Input)

RCLK3

121

RxD3

(Input)

121

RENA(CD3)

(Input)

125

124

123

127

126

Last Bit

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

14.7 SPI Master AC Electrical Specifications

Table 23

provides the SPI master timings as shown in

Figure 54

and

Figure 55

Figure 54. SPI Master (CP = 0) Timing Diagram

Table 23. SPI Master Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

160

MASTER cycle time

1024

cyc

161

MASTER clock (SCK) high or low time

512

cyc

162

MASTER data setup time (inputs)

163

Master data hold time (inputs)

164

Master data valid (after SCK edge)

165

Master data hold time (outputs)

166

Rise time output

167

Fall time output

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

162

Data

166

167

161

160

msb

lsb

msb

Data

lsb

msb

167

166

163

166

167

165

164

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

CPM Electrical Characteristics

Figure 55. SPI Master (CP = 1) Timing Diagram

14.8 SPI Slave AC Electrical Specifications

Table 24

provides the SPI slave timings as shown in

Figure 56

and

Figure 57

Table 24. SPI Slave Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

170

Slave cycle time

cyc

171

Slave enable lead time

172

Slave enable lag time

173

Slave clock (SPICLK) high or low time

cyc

174

Slave sequential transfer delay (does not require deselect)

cyc

175

Slave data setup time (inputs)

176

Slave data hold time (inputs)

177

Slave access time

SPIMOSI

(Output)

SPICLK

(CI=0)

(Output)

SPICLK

(CI=1)

(Output)

SPIMISO

(Input)

Data

166

167

161

160

msb

lsb

msb

Data

lsb

msb

167

166

163

166

167

165

164

162

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

FEC Electrical Characteristics

Figure 57. SPI Slave (CP = 1) Timing Diagram

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,

MII_RX_ER, MII_RX_CLK)

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%.

Table 25

provides information on the MII receive signal timing.

Table 25. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

MII_RX_CLK pulse width high

35%

65%

MII_RX_CLK period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CLK period

SPIMOSI

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

SPIMISO

(Output)

180

Data

181

182

msb

lsb

181

177

182

175

179

SPISEL

(Input)

174

Data

msb

lsb

Undef

178

176

182

msb

172

173

171

170

181

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

FEC Electrical Characteristics

Figure 58

shows MII receive signal timing.

Figure 58. MII Receive Signal Timing Diagram

15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,

MII_TX_ER, MII_TX_CLK)

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK
frequency - 1%.

Table 26

provides information about the MII transmit signal timing,.

Figure 59

shows the MII transmit signal timing diagram.

Table 26. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

MII_TX_CLK pulse width high

35%

65%

MII_TX_CLK period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK period

MII_RX_CLK (input)

MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

FEC Electrical Characteristics

Figure 59. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 27

provides information about the MII async inputs signal timing.

Figure 60

shows the MII asynchronous inputs signal timing diagram.

Figure 60. MII Async Inputs Timing Diagram

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 28

provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 27. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

MII_TX_CLK period

Table 28. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

M12

MII_MDIO (input) to MII_MDC rising edge setup

M13

MII_MDIO (input) to MII_MDC rising edge hold

MII_TX_CLK (input)

MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER

MII_CRS, MII_COL

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

16 Mechanical Data and Ordering Information

Table 29

identifies the packages and operating frequencies orderable for the MPC852T.

16.1 Pin Assignments

The following sections give the pinout and pin listing for the JEDEC Compliant and the non-JEDEC versions of the
16 x 16 PBGA package.

Table 29. MPC852T Package/Frequency Orderable

Package Type

Temperature (Tj)

Frequency (MHz)

Order Number

Plastic ball grid array
(VR and ZT suffix)

C to 95

MPC852TVR50
MPC852TZT50

MPC852TVR66
MPC852TZT66

MPC852TVR80
MPC852TZT80

100

MPC852TVR100
MPC852TZT100

Plastic ball grid array
(CVR suffix)

C to 100

TBD

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

16.1.1 The JEDEC Compliant Pinout

Figure 62

shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC866 PowerQUICC Family User's Manual.

NOTE: This is the top view of the device.

Figure 62. Pinout of the PBGA Package - JEDEC Standard

N/C

VDDL

BDIP

ALE_A

OP0

OP3

EXTAL

N/C

CS7 GPL_A2 WE2 BS_A0 VDDL

A28

A18

A23

A19

A14

N/C

CS0

CE2_A GPL_A3 WE3

GPL_A0

GPL_A4 CS3

CS5

WE1 BS_A2

A26

A25

A21

A17

A12

N/C

CS2

MII_CRS BS_A3

A22

A30

WE0 BS_A1

A24

TEA

A29

A27

A13

N/C

A20

A15

A10

N/C

PB29

VDDL

MII_COL BB

VFLS_1 RSV BURST

DSCK VFLS_0

AS BADDR30

OP1

OP2

BADDR29 BADDR28

VDDL

XTAL EXTCLK WAIT_A

PORST VDDSYN VSSSYN1

PC12

PA11

TMS

TRST

VDDL MDIO

PA10

PB24

PA8

PA9

PC6

PA3

PA1

PB15

VDDL

PA0

PD12

PD14

N/C

PD11

GND

VDDH

VDDL IP_A7 IP_A2

PD10

N/C

D31

IP_A0 IP_A4

DP2

D19

D27

D13

PD5

PD7

N/C

D28

D22

VDDL

D18

D8 MII_TXEN

D30

GPL_A5

HRESET

RSTCONF

VDDL

N/C

VSSSYN

DP0

DP3

IP_A5

D25

D21

D15

D10

D17

IRQ7

PD6

PD9

CLKOUT

D29

D24

D20

D16

D11

D12

IRQ0

PD4

DP1

PB31

PC13

PB30

TDO

PB28

TDI

TCK

PB25

PC5

PC7

PD13

PA2

N/C

PC4

PD8

PD15

A31

CS6

PC15

D23

SRESET

FRZ

CE_1A

CS4

TSIZ1

A16

A11

N/C

TSIZ0

IP_A3

IP_A6

D26

D14

IRQ1

PD3

IP_A1

CS1

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

Table 30

contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments.

Table 30. Pin Assignments - JEDEC Standard

Name

Pin Number

Type

A[0:31]

B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12,
B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8,
B11, A8, B10, B9, D8

Bidirectional
Three-state (3.3V only)

TSIZ0
REG

Bidirectional
Three-state (3.3V only)

TSIZ1

Bidirectional
Three-state (3.3V only)

RD/WR

Bidirectional
Three-state (3.3V only)

BURST

Bidirectional
Three-state (3.3V only)

BDIP
GPL_B5

Output

Bidirectional
Active Pull-up (3.3V only)

TEA

Open-drain

Bidirectional
Active Pull-up (3.3V only)

IRQ2
RSV

Bidirectional
Three-state (3.3V only)

IRQ4
KR
RETRY
SPKROUT

Bidirectional
Three-state (3.3V only)

CR
IRQ3

Input (3.3V only)

D[0:31]

R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12,
R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6,
P6, T5, R5

Bidirectional
Three-state (3.3V only)

DP0
IRQ3

Bidirectional
Three-state (3.3V only)

DP1
IRQ4

Bidirectional
Three-state (3.3V only)

DP2
IRQ5

Bidirectional
Three-state (3.3V only)

DP3
IRQ6

Bidirectional
Three-state (3.3V only)

Bidirectional (3.3V only)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

Bidirectional (3.3V only)

Bidirectional
Active Pull-up (3.3V only)

FRZ
IRQ6

Bidirectional (3.3V only)

IRQ0

P13

Input (3.3V only)

IRQ1

M11

Input (3.3V only)

M_TX_CLK
IRQ7

N12

Input (3.3V only)

CS[0:5]

B2, A2, D3, C3, E6, C4

Output

CS6

Output

CS7

Output

WE0
BS_B0
IORD

Output

WE1
BS_B1
IOWR

Output

WE2
BS_B2
PCOE

Output

WE3
BS_B3
PCWE

Output

BS_A[0:3]

A6, D7, C7, B7

Output

GPL_A0
GPL_B0

Output

OE
GPL_A1
GPL_B1

Output

GPL_A[2:3]
GPL_B[2:3]
CS[2

A4, B4

Output

UPWAITA
GPL_A4

Bidirectional (3.3V only)

GPL_A5

Output

PORESET

Input (3.3V only)

RSTCONF

Input (3.3V only)

HRESET

Open-drain

Table 30. Pin Assignments - JEDEC Standard (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

SRESET

Open-drain

XTAL

Analog Output

EXTAL

Analog Input (1.8V only)

CLKOUT

Output

EXTCLK

Input (1.8V only)

ALE_A

Output

CE1_A

Output

CE2_A

Output

WAIT_A

Input (3.3V only)

IP_A0

Input (3.3V only)

IP_A1

Input (3.3V only)

IP_A2
IOIS16_A

Input (3.3V only)

IP_A3

Input (3.3V only)

IP_A4

Input (3.3V only)

IP_A5

Input (3.3V only)

IP_A6

Input (3.3V only)

IP_A7

Input (3.3V only)

DSCK

Bidirectional
Three-state (3.3V only)

IWP[0:1]
VFLS[0:1]

H3, G1

Bidirectional (3.3V only)

OP0

Bidirectional (3.3V only)

OP1

Output

OP2
MODCK1
STS

Bidirectional (3.3V only)

OP3
MODCK2
DSDO

Bidirectional (3.3V only)

BADDR[28:29]

L3, L2

Output

BADDR30
REG

Output

Input (3.3V only)

PA11
RXD3

E16

Bidirectional
(Optional: Open-drain)
(5V tolerant)

Table 30. Pin Assignments - JEDEC Standard (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

PA10
TXD3

H15

Bidirectional
(5V tolerant)

PA9
RXD4

J16

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PA8
TXD4

J15

Bidirectional
(5V tolerant)

PA3
CLK5
BRGO3
TIN3

K16

Bidirectional
(5V tolerant)

PA2
CLK6
TOUT3

K14

Bidirectional
(5V tolerant)

PA1
CLK7
BRGO4
TIN4

L15

Bidirectional
(5V tolerant)

PA0
CLK8
TOUT4

M16

Bidirectional
(5V tolerant)

PB31
SPISEL

E13

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB30
SPICLK

F13

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB29
SPIMOSI

D15

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB28
SPIMISO
BRGO4

G13

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB25
SMTXD1

H14

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB24
SMRXD1

H16

Bidirectional
(Optional: Open-drain)
(5V tolerant)

PB15
BRGO3

L16

Bidirectional
(5V tolerant)

Table 30. Pin Assignments - JEDEC Standard (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

PC15
DREQ0

C16

Bidirectional
(5V tolerant)

PC13
RTS3

E14

Bidirectional
(5V tolerant)

PC12
RTS4

E15

Bidirectional
(5V tolerant)

PC7
CTS3

J14

Bidirectional
(5V tolerant)

PC6
CD3

K15

Bidirectional
(5V tolerant)

PC5
CTS4
SDACK1

J13

Bidirectional
(5V tolerant)

PC4
CD4

L14

Bidirectional
(5V tolerant)

PD15
MII_RXD3

M14

Bidirectional
(5V tolerant)

PD14
MII_RXD2

N16

Bidirectional
(5V tolerant)

PD13
MII_RXD1

K13

Bidirectional
(5V tolerant)

PD12
MII_MDC

N15

Bidirectional
(5V tolerant)

PD11
RXD3
MII_TX_ER

P16

Bidirectional
(5V tolerant)

PD10
TXD3
MII_RXD0

R15

Bidirectional
(5V tolerant)

PD9
RXD4
MII_TXD0

N14

Bidirectional
(5V tolerant)

PD8
TXD4
MII_RX_CLK

M13

Bidirectional
(5V tolerant)

PD7
RTS3
MII_RX_ER

T15

Bidirectional
(5V tolerant)

Table 30. Pin Assignments - JEDEC Standard (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

PD6
RTS4
MII_RX_DV

N13

Bidirectional
(5V tolerant)

PD5
MII_TXD3

R14

Bidirectional
(5V tolerant)

PD4
MII_TXD2

P14

Bidirectional
(5V tolerant)

PD3
MII_TXD1

M12

Bidirectional
(5V tolerant)

TMS

F15

Input
(5V tolerant)

TDI
DSDI

G14

Input
(5V tolerant)

TCK
DSCK

H13

Input
(5V tolerant)

TRST

F16

Input
(5V tolerant)

TDO
DSDO

F14

Output
(5V tolerant)

MII_CRS

Input

MII_MDIO

G16

Bidirectional
(5V tolerant)

MII_TXEN

T14

Output
(5V tolerant)

MII_COL

Input

SSSYN

PLL analog GND

SSSYN1

PLL analog GND

DDSYN

PLL analog V

GND

G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9,
J10, J11, K6, K7, K8, K9, K10, K11

Power

VDDL

A7, C1, D16, G15, L4, M2, R1, M15, T8

Power

VDDH

F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12,
K5, K12, L5, L6, L7, L8, L9, L10, L11, L12

Power

N/C

A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16

No-connect

Table 30. Pin Assignments - JEDEC Standard (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

16.1.2 The non-JEDEC Pinout

Figure 63

shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional

information, see the MPC866 PowerQUICC Family User's Manual.

NOTE: This figure shows the top view of the device.

Figure 63. Pinout of the PBGA Package - non-JEDEC

N/C

DDL

BDIP

ALE_A

OP0

OP3

EXTAL

N/C

CS7 GPL_A2 WE2 BS_A0 V

DDL

A28

A18

A23

A19

A14

N/C

CS0

CE2_A GPL_A3 WE3

GPL_A0

GPL_A4 CS3

CS5

WE1 BS_A2

A26

A25

A21

A17

A12

N/C

CS2

MII_CRS BS_A3

A22

A30

WE0 BS_A1

A24

TEA

A29

A27

A13

N/C

A20

A15

A10

N/C

PB29

DDL

MII_COL BB

VFLS_1 RSV BURST

DSCK VFLS_0

AS BADDR30

OP1

OP2

BADDR29 BADDR28

DDL

XTAL EXTCLK WAIT_A

PORST V

DDSYN

VSSSYN1

PC12

PA11

TMS

TRST

DDL

MDIO

PA10

PB24

PA8

PA9

PC6

PA3

PA1

PB15

DDL

PA0

PD12

PD14

N/C

PD11

GND

DDH

DDL

IP_A7 IP_A2

PD10

N/C

D31

IP_A0 IP_A4

DP2

D19

D27

D13

PD5

PD7

N/C

D28

D22

DDL

D18

D8 MII_TXEN

D30

GPL_A5

HRESET

RSTCONF

DDL

N/C

VSSSYN

DP0

DP3

IP_A5

D25

D21

D15

D10

D17

IRQ7

PD6

PD9

CLKOUT

D29

D24

D20

D16

D11

D12

IRQ0

PD4

DP1

PB31

PC13

PB30

TDO

PB28

TDI

TCK

PB25

PC5

PC7

PD13

PA2

N/C

PC4

PD8

PD15

A31

CS6

PC15

D23

SRESET

FRZ

CE_1A

CS4

TSIZ1

A16

A11

N/C

TSIZ0

IP_A3

IP_A6

D26

D14

IRQ1

PD3

IP_A1

CS1

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

Table 31

contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments.

Table 31. Pin Assignments - non-JEDEC

Name

Pin Number

Type

A[0:31]

C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13,
C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10,
D9, C12, B9, C11, C10, E9

Bidirectional
Three-state (3.3 V only)

TSIZ0
REG

Bidirectional
Three-state (3.3 V only)

TSIZ1

Bidirectional
Three-state (3.3 V only)

RD/WR

Bidirectional
Three-state (3.3 V only)

BURST

Bidirectional
Three-state (3.3 V only)

BDIP
GPL_B5

Output

Bidirectional
Active Pull-up (3.3 V only)

TEA

Open-drain

Bidirectional
Active Pull-up (3.3 V only)

IRQ2
RSV

Bidirectional
Three-state (3.3 V only)

IRQ4
KR
RETRY
SPKROUT

Bidirectional
Three-state (3.3 V only)

CR
IRQ3

Input (3.3 V only)

D[0:31]

T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13,
T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9,
T12, T7, R7, U6, T6

Bidirectional
Three-state (3.3 V only)

DP0
IRQ3

Bidirectional
Three-state (3.3 V only)

DP1
IRQ4

Bidirectional
Three-state (3.3 V only)

DP2
IRQ5

Bidirectional
Three-state (3.3 V only)

DP3
IRQ6

Bidirectional
Three-state (3.3 V only)

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

Bidirectional (3.3 V only)

Bidirectional
Active Pull-up (3.3 V only)

FRZ
IRQ6

Bidirectional (3.3 V only)

IRQ0

R14

Input (3.3 V only)

IRQ1

N12

Input (3.3 V only)

IRQ7
M_TX_CLK

P13

Input (3.3 V only)

CS[0:5]

C3, B3, E4, D4, F7, D5

Output

CS6

Output

CS7

Output

WE0
BS_B0
IORD

Output

WE1
BS_B1
IOWR

Output

WE2
BS_B2
PCOE

Output

WE3
BS_B3
PCWE

Output

BS_A[0:3]

B7, E8, D8, C8

Output

GPL_A0
GPL_B0

Output

OE
GPL_A1
GPL_B1

Output

GPL_A[2:3]
GPL_B[2:3]
CS[2

B5, C5

Output

UPWAITA
GPL_A4

Bidirectional (3.3 V only)

GPL_A5

Output

PORESET

Input (3.3 V only)

Table 31. Pin Assignments - non-JEDEC (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

RSTCONF

Input (3.3 V only)

HRESET

Open-drain

SRESET

Open-drain

XTAL

Analog Output

EXTAL

Analog Input (3.3 V only)

CLKOUT

Output

EXTCLK

Input (3.3 V only)

ALE_A

Output

CE1_A

Output

CE2_A

Output

WAIT_A

Input (3.3 V only)

IP_A0

Input (3.3 V only)

IP_A1

Input (3.3 V only)

IP_A2
IOIS16_A

Input (3.3 V only)

IP_A3

Input (3.3 V only)

IP_A4

Input (3.3 V only)

IP_A5

Input (3.3 V only)

IP_A6

Input (3.3 V only)

IP_A7

Input (3.3 V only)

DSCK

Bidirectional
Three-state (3.3 V only)

IWP[0:1]
VFLS[0:1]

J4, H2

Bidirectional (3.3 V only)

OP0

Bidirectional (3.3 V only)

OP1

Output

OP2
MODCK1
STS

Bidirectional (3.3 V only)

OP3
MODCK2
DSDO

Bidirectional (3.3 V only)

BADDR[28:29]

M4, M3

Output

BADDR30
REG

Output

Table 31. Pin Assignments - non-JEDEC (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

Input (3.3 V only)

PA11
RXD3

F17

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PA10
TXD3

J16

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PA9
RXD4

K17

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PA8
TXD4

K16

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PA3
CLK5
BRGO3
TIN3

L17

Bidirectional
(5 V-tolerant)

PA2
CLK6
TOUT3

L15

Bidirectional
(5 V-tolerant)

PA1
CLK7
BRGO4
TIN4

M16

Bidirectional
(5 V-tolerant)

PA0
CLK8
TOUT4

N17

Bidirectional
(5 V-tolerant)

PB31
SPISEL

F14

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PB30
SPICLK

G14

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PB29
SPIMOSI

E16

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PB28
SPIMISO
BRGO4

H14

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

Table 31. Pin Assignments - non-JEDEC (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

PB25
SMTXD1

J15

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PB24
SMRXD1

J17

Bidirectional
(Optional: Open-drain)
(5 V-tolerant)

PB15
BRGO3

M17

Bidirectional
(5 V-tolerant)

PC15
DREQ0

D17

Bidirectional
(5 V-tolerant)

PC13
RTS3

F15

Bidirectional
(5 V-tolerant)

PC12
RTS4

F16

Bidirectional
(5 V-tolerant)

PC7
CTS3

K15

Bidirectional
(5 V-tolerant)

PC6
CD3

L16

Bidirectional
(5 V-tolerant)

PC5
CTS4
SDACK1

K14

Bidirectional
(5 V-tolerant)

PC4
CD4

M15

Bidirectional
(5 V-tolerant)

PD15
MII_RXD3

N15

Bidirectional
(5 V-tolerant)

PD14
MII_RXD2

P17

Bidirectional
(5 V-tolerant)

PD13
MII_RXD1

L14

Bidirectional
(5 V-tolerant)

PD12
MII_MDC

P16

Bidirectional
(5 V-tolerant)

PD11
RXD3
MII_TX_ER

R17

Bidirectional
(5 V-tolerant)

PD10
TXD3
MII_RXD0

T16

Bidirectional
(5 V-tolerant)

Table 31. Pin Assignments - non-JEDEC (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Mechanical Data and Ordering Information

PD9
RXD4
MII_TXD0

P15

Bidirectional
(5 V-tolerant)

PD8
TXD4
MII_RX_CLK

N14

Bidirectional
(5 V-tolerant)

PD7
RTS3
MII_RX_ER

U16

Bidirectional
(5 V-tolerant)

PD6
RTS4
MII_RX_DV

P14

Bidirectional
(5 V-tolerant)

PD5
MII_TXD3

T15

Bidirectional
(5 V-tolerant)

PD4
MII_TXD2

R15

Bidirectional
(5 V-tolerant)

PD3
MII_TXD1

N13

Bidirectional
(5 V-tolerant)

TMS

G16

Input
(5 V-tolerant)

TDI
DSDI

H15

Input
(5 V-tolerant)

TCK
DSCK

J14

Input
(5 V-tolerant)

TRST

G17

Input
(5 V-tolerant)

TDO
DSDO

G15

Output
(5 V-tolerant)

MII_CRS

Input

MII_MDIO

H17

Bidirectional
(5 V-tolerant)

MII_TX_EN

U15

Output
(5 V-tolerant)

MII_COL

Input

SSSYN

PLL analog GND

SSSYN1

PLL analog GND

DDSYN

PLL analog V

Table 31. Pin Assignments - non-JEDEC (continued)

Name

Pin Number

Type

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Document Revision History

17 Document Revision History

Table 32

lists significant changes between revisions of this document.

Table 32. Document Revision History

Revision

Date

Changes

3.1

1/18/2005

Document template update.

3.0

11/2004

Added sentence to Spec B1A about EXTCLK and CLKOUT being in
Alignment for Integer Values

Added a footnote to Spec 41 specifying that EDM = 1

Broke the

Section 16.1,

Pin Assignments

into 2 smaller sections

for the JEDEC and non-JEDEC pinouts.

2.0

12/2003

Put 852T on the 1st page in place of 8245.
Figure 62 on page 59 had overbars added on signals CR (pin G2) and
WAIT_A (pin P4).

1.8

7/2003

Changed the pinout to be JEDEC Compliant, changed timing
parameters B28a through B28d, and B29d to show that TRLX can be 0
or 1.

1.7

5/2003

Changed the SPI Master Timing Specs. 162 and 164

1.6

4/2003

Changed the package drawing in Figure 15-63

1.5

4/2003

Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added
the Note: solder sphere composition for MPC852TVR and
MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63

1.4

2/2003

Changed Table 15-30 Pin Assignments for the PLL Pins V

SSSYN1

SSSYN

, V

DDSYN

1.3

1/2003

Added subscripts to timing diagrams for B1-B35, to specify memory
controller settings for the specific edges.

1.2

1/2003

In Table 15-30, specified EXTCLK as 3.3 V.

1.1

12/2002

Added fast Ethernet controller to the features

11/2002

Added values for 80 and 100 MHz

10/2002

Initial release

MPC852TEC
Rev. 3.1
01/2005

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