Электронный компонент: MPC8540

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MPC8540 PowerQUICC IIITM

Integrated Host Processor

Reference Manual

MPC8540RM

Rev. 1

07/2004

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� Freescale Semiconductor, Inc. 2004.

MPC8540RM
Rev. 1
07/2004

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IND

Part I--Overview

Overview

Memory Map

Signal Descriptions

Reset, Clocking, and Initialization

Part II--e500 Core Complex and L2 Cache

e500 Core Complex Overview

e500 Register Summary

L2 Look-Aside Cache/SRAM

Part III--Memory and I/O Interfaces

e500 Coherency Module

DDR Memory Controller

Programmable Interrupt Controller

I

2

C Interface

DUART

Local Bus Controller

Three-Speed Ethernet Controllers

DMA Controller

PCI/PCI-X Bus Interface

RapidIO Interface

Part IV--Global Functions and Debug

Global Utilities

Performance Monitor

Debug Features and Watchpoint Facility

10/100 Fast Ethernet Controller

Appendix A--Revision History

Glossary of Terms and Abbreviations

Register Index (Memory-Mapped Registers)

General Index

I

III

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9

10

11

12

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14

15

16

17

1

2

3

4

IV

18

19

20

21

II

5

6

7

A

GLO

REG

IND

Part I--Overview
Overview

Memory Map

Signal Descriptions

Reset, Clocking, and Initialization

Part II--e500 Core Complex and L2 Cache
e500 Core Complex Overview

e500 Register Summary

L2 Look-Aside Cache/SRAM

Part III--Memory and I/O Interfaces
e500 Coherency Module

DDR Memory Controller

Programmable Interrupt Controller

I

2

C Interface

DUART

Local Bus Controller

Three-Speed Ethernet Controllers

DMA Controller

PCI/PCI-X Bus Interface

RapidIO Interface

Part IV--Global Functions and Debug
Global Utilities

Performance Monitor

Debug Features and Watchpoint Facility

10/100 Fast Ethernet Controller

Appendix A--Revision History

Glossary of Terms and Abbreviations

Register Index (Memory-Mapped Registers)

General Index

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

v

Contents

Paragraph
Number

Title

Page

Number

Cont ents

About This Book

Audience ..................................................................................................................... lxxxiii
Organization................................................................................................................ lxxxiii
Suggested Reading...................................................................................................... lxxxvi

General Information............................................................................................ lxxxvi
Related Documentation ...................................................................................... lxxxvi

Conventions ............................................................................................................... lxxxvii
Signal Conventions ................................................................................................... lxxxviii
Acronyms and Abbreviations ................................................................................... lxxxviii

Part I

Overview

Chapter 1

Overview

1.1

Introduction...................................................................................................................... 1-1

1.2

MPC8540 Overview ........................................................................................................ 1-1

1.2.1

Key Features ................................................................................................................ 1-2

1.3

MPC8540 Architecture Overview ................................................................................... 1-8

1.3.1

e500 Core Overview .................................................................................................... 1-8

1.3.2

On-Chip Memory Unit............................................................................................... 1-12

1.3.2.1

On-Chip Memory as Memory-Mapped SRAM..................................................... 1-13

1.3.2.2

On-Chip Memory as L2 Cache.............................................................................. 1-13

1.3.3

e500 Coherency Module (ECM)................................................................................ 1-14

1.3.4

DDR SDRAM Controller .......................................................................................... 1-14

1.3.5

Programmable Interrupt Controller (PIC).................................................................. 1-15

1.3.6

I

2

C Controller ............................................................................................................ 1-15

1.3.7

Boot Sequencer .......................................................................................................... 1-16

1.3.8

Dual Universal Asynchronous Receiver/Transmitter (DUART) ............................... 1-16

1.3.9

10/100 Fast Ethernet Controller................................................................................. 1-16

1.3.10

Local Bus Controller (LBC) ...................................................................................... 1-17

1.3.11

Three-Speed Ethernet Controllers (10/100/1Gb)....................................................... 1-17

1.3.12

Integrated DMA ......................................................................................................... 1-18

1.3.13

PCI Controller............................................................................................................ 1-18

1.3.14

RapidIO Controller .................................................................................................... 1-18

Document Outline

• MPC8540 PowerQUICC III� Integrated Host Processor Reference Manual
  • Contents
  • Figures
  • Tables
  • About This Book
    • Audience
    • Organization
    • Suggested Reading
      • General Information
      • Related Documentation
    • Conventions
    • Signal Conventions
    • Acronyms and Abbreviations
      • Table1. Acronyms and Abbreviated Terms
  • PartI Overview
    • Chapter1 Overview
      • 1.1 Introduction
      • 1.2 MPC8540 Overview
        • Figure1-1. MPC8540 Block Diagram
        • 1.2.1 Key Features
      • 1.3 MPC8540 Architecture Overview
        • 1.3.1 e500 Core Overview
        • 1.3.2 On-Chip Memory Unit
          • 1.3.2.1 On-Chip Memory as Memory-Mapped SRAM
          • 1.3.2.2 On-Chip Memory as L2 Cache
        • 1.3.3 e500 Coherency Module (ECM)
        • 1.3.4 DDR SDRAM Controller
        • 1.3.5 Programmable Interrupt Controller (PIC)
        • 1.3.6 I2C Controller
        • 1.3.7 Boot Sequencer
        • 1.3.8 Dual Universal Asynchronous Receiver/Transmitter (DUART)
        • 1.3.9 10/100 Fast Ethernet Controller
        • 1.3.10 Local Bus Controller (LBC)
        • 1.3.11 Three-Speed Ethernet Controllers (10/100/1Gb)
        • 1.3.12 Integrated DMA
        • 1.3.13 PCI Controller
        • 1.3.14 RapidIO Controller
          • 1.3.14.1 RapidIO Message Unit
        • 1.3.15 Power Management
        • 1.3.16 Clocking
        • 1.3.17 Address Map
        • 1.3.18 OCeaN Switch Fabric
        • 1.3.19 Processing Across the On-Chip Fabric
          • Figure1-2. Processing Transactions Across the On-Chip Fabric
        • 1.3.20 Data Processing with the e500 Coherency Module
      • 1.4 MPC8540 Application Examples
        • 1.4.1 MPC8540 Applications
          • Figure1-3. High-Performance Communication System Using SMP
          • Figure1-4. High-Performance Communication System Using MPC8540
          • Figure1-5. RAID Controller Application Using MPC8540
          • Figure1-6. VPN Access Point Enabled by RapidIO and Ethernet
          • Figure1-7. MPC8540 with SERDES
          • Figure1-8. MPC8540 with a DSP Farm Enabled by General-Purpose Chip Select Machine or User Progra...
    • Chapter2 Memory Map
      • 2.1 Local Memory Map Overview and Example
        • Table2-1. Target Interface Codes
        • Figure2-1. Local Memory Map Example
        • Table2-2. Local Access Windows Example
      • 2.2 Address Translation and Mapping
        • Table2-3. Format of ATMU Window Definitions
        • 2.2.1 SRAM Windows
        • 2.2.2 Window into Configuration Space
        • 2.2.3 Local Access Windows
          • 2.2.3.1 Local Access Register Memory Map
            • Table2-4. Local Access Register Memory Map
          • 2.2.3.2 Local Access Window n Base Address Registers (LAWBAR0�LAWBAR7)
            • Figure2-2. Local Access Window n Base Address Registers (LAWBAR0�LAWBAR7)
            • Table2-5. LAWBARn Field Descriptions
          • 2.2.3.3 Local Access Window n Attributes Registers (LAWAR0�LAWAR7)
            • Figure2-3. Local Access Window n Attributes Registers (LAWAR0�LAWAR7)
            • Table2-6. LAWARn Field Descriptions
          • 2.2.3.4 Precedence of Local Access Windows
            • Table2-7. Overlapping Local Access Windows
          • 2.2.3.5 Configuring Local Access Windows
          • 2.2.3.6 Distinguishing Local Access Windows from Other Mapping Functions
          • 2.2.3.7 Illegal Interaction Between Local Access Windows and DDR SDRAM Chip Selects
        • 2.2.4 Outbound Address Translation and Mapping Windows
        • 2.2.5 Inbound Address Translation and Mapping Windows
          • 2.2.5.1 RapidIO Inbound ATMU
          • 2.2.5.2 PCI/PCI-X Inbound ATMU
          • 2.2.5.3 Illegal Interaction Between Inbound ATMUs and Local Access Windows
      • 2.3 Configuration, Control, and Status Register Map
        • Figure2-4. Top-Level Register Map Example
        • 2.3.1 Accessing CCSR Memory from External Masters
        • 2.3.2 Organization of CCSR Memory
          • Table2-8. Local Memory Configuration, Control, and Status Register Summary
        • 2.3.3 General Utilities Registers
          • Figure2-5. General Utilities Registers Mapping to Configuration, Control, and Status Memory Block
        • 2.3.4 Interrupt Controller and CCSR
          • Figure2-6. PIC Mapping to Configuration, Control, and Status Memory Block
        • 2.3.5 RapidIO and CCSR
          • Figure2-7. RapidIO Mapping to Configuration, Control, and Status Memory Block
        • 2.3.6 Device-Specific Utilities
          • Figure2-8. Device-Specific Register Mapping to Configuration, Control, and Status Memory Block
      • 2.4 Complete CCSR Map
        • Table2-9. Memory Map
    • Chapter3 Signal Descriptions
      • 3.1 Signals Overview
        • Figure3-1. MPC8540 Signal Groupings
        • Table3-1. MPC8540 Signal Reference by Functional Block
        • Table3-2. MPC8540 Alphabetical Signal Reference
      • 3.2 Configuration Signals Sampled at Reset
        • Table3-3. MPC8540 Reset Configuration Signals
      • 3.3 Output Signal States During Reset
        • Table3-4. Output Signal States During System Reset
    • Chapter4 Reset, Clocking, and Initialization
      • 4.1 Overview
      • 4.2 External Signal Descriptions
        • Table4-1. Signal Summary
        • 4.2.1 System Control Signals
          • Table4-2. System Control Signals�Detailed Signal Descriptions
        • 4.2.2 Clock Signals
          • Table4-3. Clock Signals�Detailed Signal Descriptions
      • 4.3 Memory Map/Register Definition
        • 4.3.1 Local Configuration Control
          • Table4-4. Local Configuration Control Register Map
          • 4.3.1.1 Accessing Configuration, Control, and Status Registers
            • 4.3.1.1.1 Updating CCSRBAR
            • 4.3.1.1.2 Configuration, Control, and Status Base Address Register (CCSRBAR)
              • Figure4-1. Configuration, Control, and Status Register Base Address Register (CCSRBAR)
              • Table4-5. CCSRBAR Field Descriptions
          • 4.3.1.2 Accessing Alternate Configuration Space
            • 4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)
              • Figure4-2. Alternate Configuration Base Address Register (ALTCBAR)
              • Table4-6. ALTCBAR Field Descriptions
            • 4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)
              • Figure4-3. Alternate Configuration Attribute Register (ALTCAR)
              • Table4-7. ALTCAR Field Descriptions
          • 4.3.1.3 Boot Page Translation
            • 4.3.1.3.1 Boot Page Translation Register (BPTR)
              • Figure4-4. Boot Page Translation Register (BPTR)
              • Table4-8. BPTR Field Descriptions
        • 4.3.2 Boot Sequencer
      • 4.4 Functional Description
        • 4.4.1 Reset Operations
          • 4.4.1.1 Soft Reset
          • 4.4.1.2 Hard Reset
        • 4.4.2 Power-On Reset Sequence
          • Figure4-5. Power-On Reset Sequence
        • 4.4.3 Power-On Reset Configuration
          • 4.4.3.1 System PLL Ratio
            • Table4-9. CCB Clock PLL Ratio
          • 4.4.3.2 e500 Core PLL Ratio
            • Table4-10. e500 Core Clock PLL Ratios
          • 4.4.3.3 Boot ROM Location
            • Table4-11. Boot ROM Location
          • 4.4.3.4 Host/Agent Configuration
            • Table4-12. Host/Agent Configuration
          • 4.4.3.5 CPU Boot Configuration
            • Table4-13. CPU Boot Configuration
          • 4.4.3.6 Boot Sequencer Configuration
            • Table4-14. Boot Sequencer Configuration
          • 4.4.3.7 TSEC Width
            • Table4-15. TSEC Width Configuration
          • 4.4.3.8 TSEC1 Protocol
            • Table4-16. TSEC1 Protocol Configuration
          • 4.4.3.9 TSEC2 Protocol
            • Table4-17. TSEC2 Protocol Configuration
          • 4.4.3.10 RapidIO Transmit Clock Source
            • Table4-18. RapidIO Transmit Clock Source
          • 4.4.3.11 RapidIO Device ID
            • Table4-19. RapidIO Device ID
          • 4.4.3.12 PCI Width Configuration
            • Table4-20. PCI-32 Configuration
          • 4.4.3.13 PCI I/O Impedance
            • Table4-21. PCI I/O Impedance
          • 4.4.3.14 PCI Arbiter Configuration
            • Table4-22. PCI Arbiter Configuration
          • 4.4.3.15 PCI Debug Configuration
            • Table4-23. PCI Debug Configuration
          • 4.4.3.16 PCI-X Configuration
            • Table4-24. PCI/PCI-X Configuration
          • 4.4.3.17 Memory Debug Configuration
            • Table4-25. Memory Debug Configuration
          • 4.4.3.18 DDR Debug Configuration
            • Table4-26. DDR Debug Configuration
          • 4.4.3.19 PCI/PCI-X Output Hold Configuration
            • Table4-27. PCI Output Hold Configuration (cfg_pci_mode=1)
            • Table4-28. PCI-X Output Hold Configuration (cfg_pci_mode=0)
          • 4.4.3.20 Local Bus Output Hold Configuration
            • Table4-29. Local Bus Output Hold Configuration
          • 4.4.3.21 General-Purpose POR Configuration
            • Table4-30. General-Purpose POR Configuration
        • 4.4.4 Clocking
          • 4.4.4.1 System Clock/PCI Clock
            • Figure4-6. Clock Subsystem Block Diagram
          • 4.4.4.2 RapidIO Clocks
            • Figure4-7. RapidIO Transmit Clock Options
          • 4.4.4.3 Ethernet Clocks
          • 4.4.4.4 Real Time Clock
            • Figure4-8. RTC and Core Timer Facilities Clocking Options
  • PartII e500 Core Complex and L2 Cache
    • Chapter5 Core Complex Overview
      • 5.1 Overview
        • Figure5-1. e500 Core Complex Block Diagram
        • 5.1.1 Upward Compatibility
        • 5.1.2 Core Complex Summary
      • 5.2 e500 Processor and System Version Numbers
        • Table5-1. Revision Level-to-Device Marking Cross-Reference
      • 5.3 Features
        • Figure5-2. Four-Stage MU Pipeline, Showing Divide Bypass
        • Figure5-3. Three-Stage Load/Store Unit
      • 5.4 Instruction Set
        • Table5-2. Performance Monitor APU Instructions
        • Table5-3. Cache Block Lock and Unlock APU Instructions
        • Table5-4. Scalar and Vector Embedded Floating-Point APU Instructions
        • Table5-5. BTB Locking APU Instructions
      • 5.5 Instruction Flow
        • 5.5.1 Initial Instruction Fetch
        • 5.5.2 Branch Detection and Prediction
        • 5.5.3 e500 Execution Pipeline
          • Figure5-4. Instruction Pipeline Flow
          • Figure5-5. GPR Issue Queue (GIQ)
      • 5.6 Programming Model
        • Figure5-6. e500 Core Programming Model
      • 5.7 On-Chip Cache Implementation
      • 5.8 Interrupts and Exception Handling
        • 5.8.1 Exception Handling
        • 5.8.2 Interrupt Classes
        • 5.8.3 Interrupt Types
        • 5.8.4 Upper Bound on Interrupt Latencies
        • 5.8.5 Interrupt Registers
          • Table5-6. Interrupt Registers
          • Table5-7. Interrupt Vector Registers and Exception Conditions
      • 5.9 Memory Management
        • Figure5-7. MMU Structure
        • 5.9.1 Address Translation
          • Figure5-8. Effective-to-Real Address Translation Flow
        • 5.9.2 MMU Assist Registers (MAS1�MAS4 and MAS6)
        • 5.9.3 Process ID Registers (PID0�PID2)
        • 5.9.4 TLB Coherency
      • 5.10 Memory Coherency
        • 5.10.1 Atomic Update Memory References
        • 5.10.2 Memory Access Ordering
        • 5.10.3 Cache Control Instructions
        • 5.10.4 Programmable Page Characteristics
      • 5.11 Core Complex Bus (CCB)
      • 5.12 Performance Monitoring
        • 5.12.1 Global Control Register
        • 5.12.2 Performance Monitor Counter Registers
        • 5.12.3 Local Control Registers
      • 5.13 Legacy Support of PowerPC Architecture
        • 5.13.1 Instruction Set Compatibility
          • 5.13.1.1 User Instruction Set
          • 5.13.1.2 Supervisor Instruction Set
        • 5.13.2 Memory Subsystem
        • 5.13.3 Exception Handling
        • 5.13.4 Memory Management
        • 5.13.5 Reset
        • 5.13.6 Little-Endian Mode
      • 5.14 PowerQUICC III Implementation Details
        • Table5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation
    • Chapter6 Core Register Summary
      • 6.1 Overview
        • 6.1.1 Register Set
          • Figure6-1. Core Register Model
      • 6.2 Register Model for 32-Bit Implementations
        • 6.2.1 Special-Purpose Registers (SPRs)
          • Table6-1. Book E Special-Purpose Registers (by SPR Abbreviation)
          • Table6-2. Implementation-Specific SPRs (by SPR Abbreviation)
      • 6.3 Registers for Computational Operations
        • 6.3.1 General-Purpose Registers (GPRs)
        • 6.3.2 Integer Exception Register (XER)
          • Figure6-2. Integer Exception Register (XER)
          • Table6-3. XER Field Description
      • 6.4 Registers for Branch Operations
        • 6.4.1 Condition Register (CR)
          • Figure6-3. Condition Register (CR)
          • Table6-4. BI Operand Settings for CR Fields
          • Table6-5. CR0 Bit Descriptions
        • 6.4.2 Link Register (LR)
          • Figure6-4. Link Register (LR)
        • 6.4.3 Count Register (CTR)
          • Figure6-5. Count Register (CTR)
      • 6.5 Processor Control Registers
        • 6.5.1 Machine State Register (MSR)
          • Figure6-6. Machine State Register (MSR)
          • Table6-6. MSR Field Descriptions
        • 6.5.2 Processor ID Register (PIR)
          • Figure6-7. Processor ID Register (PIR)
        • 6.5.3 Processor Version Register (PVR)
          • Figure6-8. Processor Version Register (PVR)
          • Table6-7. PVR Field Descriptions
        • 6.5.4 System Version Register (SVR)
          • Figure6-9. System Version Register (SVR)
      • 6.6 Timer Registers
        • 6.6.1 Timer Control Register (TCR)
          • Figure6-10. Timer Control Register (TCR)
          • Table6-8. TCR Field Descriptions
        • 6.6.2 Timer Status Register (TSR)
          • Figure6-11. Timer Status Register (TSR)
          • Table6-9. TSR Field Descriptions
        • 6.6.3 Time Base Registers
          • Figure6-12. Time Base Upper/Lower Registers (TBU/TBL)
        • 6.6.4 Decrementer Register
          • Figure6-13. Decrementer Register (DEC)
        • 6.6.5 Decrementer Auto-Reload Register (DECAR)
          • Figure6-14. Decrementer Auto-Reload Register (DECAR)
      • 6.7 Interrupt Registers
        • 6.7.1 Interrupt Registers Defined by Book E
          • 6.7.1.1 Save/Restore Register 0 (SRR0)
            • Figure6-15. Save/Restore Register 0 (SRR0)
          • 6.7.1.2 Save/Restore Register 1 (SRR1)
            • Figure6-16. Save/Restore Register 1 (SRR1)
          • 6.7.1.3 Critical Save/Restore Register 0 (CSRR0)
            • Figure6-17. Critical Save/Restore Register 0 (CSRR0)
          • 6.7.1.4 Critical Save/Restore Register 1 (CSRR1)
            • Figure6-18. Critical Save/Restore Register 1 (CSRR1)
          • 6.7.1.5 Data Exception Address Register (DEAR)
            • Figure6-19. Data Exception Address Register (DEAR)
          • 6.7.1.6 Interrupt Vector Prefix Register (IVPR)
            • Figure6-20. Interrupt Vector Prefix Register (IVPR)
          • 6.7.1.7 Interrupt Vector Offset Registers (IVORn)
            • Figure6-21. Interrupt Vector Offset Registers (IVORn)
            • Table6-10. IVOR Assignments
          • 6.7.1.8 Exception Syndrome Register (ESR)
            • Figure6-22. Exception Syndrome Register (ESR)
            • Table6-11. ESR Field Descriptions
        • 6.7.2 EIS-Defined Interrupt Registers
          • 6.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)
            • Figure6-23. Machine Check Save/Restore Register 0 (MCSRR0)
          • 6.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)
            • Figure6-24. Machine Check Save/Restore Register 1 (MCSRR1)
          • 6.7.2.3 Machine Check Address Register (MCAR)
            • Figure6-25. Machine Check Address Register (MCAR)
          • 6.7.2.4 Machine Check Syndrome Register (MCSR)
            • Figure6-26. Machine Check Syndrome Register (MCSR)
            • Table6-12. MCSR Field Descriptions
      • 6.8 Software-Use SPRs (SPRG0�SPRG7 and USPRG0)
        • Figure6-27. Software-Use SPRs (SPRG0�SPRG7 and USPRG0)
      • 6.9 Branch Target Buffer (BTB) Registers
        • 6.9.1 Branch Buffer Entry Address Register (BBEAR)
          • Figure6-28. Branch Buffer Entry Address Register (BBEAR)
          • Table6-13. BBEAR Field Descriptions
        • 6.9.2 Branch Buffer Target Address Register (BBTAR)
          • Figure6-29. Branch Buffer Target Address Register (BBTAR)
          • Table6-14. BBTAR Field Descriptions
        • 6.9.3 Branch Unit Control and Status Register (BUCSR)
          • Figure6-30. Branch Unit Control and Status Register (BUCSR)
          • Table6-15. BUCSR Field Descriptions
      • 6.10 Hardware Implementation-Dependent Registers
        • 6.10.1 Hardware Implementation-Dependent Register 0 (HID0)
          • Figure6-31. Hardware Implementation-Dependent Register 0 (HID0)
          • Table6-16. HID0 Field Descriptions
        • 6.10.2 Hardware Implementation-Dependent Register 1 (HID1)
          • Figure6-32. Hardware Implementation-Dependent Register 1 (HID1)
          • Table6-17. HID1 Field Descriptions
      • 6.11 L1 Cache Configuration Registers
        • 6.11.1 L1 Cache Control and Status Register 0 (L1CSR0)
          • Figure6-33. L1 Cache Control and Status Register 0 (L1CSR0)
          • Table6-18. L1CSR0 Field Descriptions
        • 6.11.2 L1 Cache Control and Status Register 1 (L1CSR1)
          • Figure6-34. L1 Cache Control and Status Register 1 (L1CSR1)
          • Table6-19. L1CSR1 Field Descriptions
        • 6.11.3 L1 Cache Configuration Register 0 (L1CFG0)
          • Figure6-35. L1 Cache Configuration Register 0 (L1CFG0)
          • Table6-20. L1CFG0 Field Descriptions
        • 6.11.4 L1 Cache Configuration Register 1 (L1CFG1)
          • Figure6-36. L1 Cache Configuration Register 1 (L1CFG1)
          • Table6-21. L1CFG1 Field Descriptions
      • 6.12 MMU Registers
        • 6.12.1 Process ID Registers (PID0�PID2)
          • Figure6-37. Process ID Registers (PID0�PID2)
        • 6.12.2 MMU Control and Status Register 0 (MMUCSR0)
          • Figure6-38. MMU Control and Status Register 0 (MMUCSR0)
          • Table6-22. MMUCSR0 Field Descriptions
        • 6.12.3 MMU Configuration Register (MMUCFG)
          • Figure6-39. MMU Configuration Register (MMUCFG)
          • Table6-23. MMUCFG Field Descriptions
        • 6.12.4 TLB Configuration Registers (TLBnCFG)
          • 6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG)
            • Figure6-40. TLB Configuration Register 0 (TLB0CFG)
            • Table6-24. TLB0CFG Field Descriptions
          • 6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)
            • Figure6-41. TLB Configuration Register 1 (TLB1CFG)
            • Table6-25. TLB1CFG Field Descriptions
        • 6.12.5 MMU Assist Registers
          • 6.12.5.1 MAS Register 0 (MAS0)
            • Figure6-42. MAS Register 0 (MAS0)
            • Table6-26. MAS0 Field Descriptions�MMU Read/Write and Replacement Control
          • 6.12.5.2 MAS Register 1 (MAS1)
            • Figure6-43. MAS Register 1 (MAS1)
            • Table6-27. MAS1 Field Descriptions�Descriptor Context and Configuration Control
          • 6.12.5.3 MAS Register 2 (MAS2)
            • Figure6-44. MAS Register 2 (MAS2)
            • Table6-28. MAS2 Field Descriptions�EPN and Page Attributes
          • 6.12.5.4 MAS Register 3 (MAS3)
            • Figure6-45. MAS Register 3 (MAS3)
            • Table6-29. MAS3 Field Descriptions�RPN and Access Control
          • 6.12.5.5 MAS Register 4 (MAS4)
            • Figure6-46. MAS Register 4 (MAS4)
            • Table6-30. MAS4 Field Descriptions�Hardware Replacement Assist Configuration
          • 6.12.5.6 MAS Register 6 (MAS6)
            • Figure6-47. MAS Register 6 (MAS6)
            • Table6-31. MAS6�TLB Search Context Register 0
      • 6.13 Debug Registers
        • 6.13.1 Debug Control Registers (DBCR0�DBCR2)
          • 6.13.1.1 Debug Control Register 0 (DBCR0)
            • Figure6-48. Debug Control Register 0 (DBCR0)
            • Table6-32. DBCR0 Field Descriptions
          • 6.13.1.2 Debug Control Register 1 (DBCR1)
            • Figure6-49. Debug Control Register 1 (DBCR1)
            • Table6-33. DBCR1 Field Descriptions
          • 6.13.1.3 Debug Control Register 2 (DBCR2)
            • Figure6-50. Debug Control Register 2 (DBCR2)
            • Table6-34. DBCR2 Field Descriptions
        • 6.13.2 Debug Status Register (DBSR)
          • Figure6-51. Debug Status Register (DBSR)
          • Table6-35. DBSR Field Descriptions
        • 6.13.3 Instruction Address Compare Registers (IAC1�IAC2)
          • Figure6-52. Instruction Address Compare Registers (IAC1�IAC2)
        • 6.13.4 Data Address Compare Registers (DAC1�DAC2)
          • Figure6-53. Data Address Compare Registers (DAC1�DAC2)
      • 6.14 Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)
        • Figure6-54. Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)
        • Table6-36. SPEFSCR Field Descriptions
        • 6.14.1 Accumulator (ACC)
          • Figure6-55. Accumulator (ACC)
          • Table6-37. ACC FIeld Descriptions
      • 6.15 Performance Monitor Registers (PMRs)
        • Table6-38. Supervisor-Level PMRs (PMR[5] = 1)
        • Table6-39. User-Level PMRs (PMR[5] = 0) (Read Only)
        • 6.15.1 Global Control Register 0 (PMGC0, UPMGC0)
          • Figure6-56. Performance Monitor Global Control Register 0 (PMGC0), UserPerformance Monitor Glob...
          • Table6-40. PMGC0 Field Descriptions
        • 6.15.2 Local Control A Registers (PMLCa0�PMLCa3, UPMLCa0�UPMLCa3)
          • Figure6-57. Local Control A Registers (PMLCa0�PMLCa3), User Local Control A Registers (UPMLCa0�U...
          • Table6-41. PMLCa0�PMLCa3 Field Descriptions
        • 6.15.3 Local Control B Registers (PMLCb0�PMLCb3, UPMLCb0�UPMLCb3)
          • Figure6-58. Local Control B Registers (PMLCb0�PMLCb3), User Local Control B Registers (UPMLCb0�U...
          • Table6-42. PMLCb0�PMLCb3 Field Descriptions
        • 6.15.4 Performance Monitor Counter Registers (PMC0�PMC3, UPMC0�UPMC3)
          • Figure6-59. Performance Monitor Counter Registers (PMC0�PMC3), User Performance Monitor Counter ...
          • Table6-43. PMC0�PMC3 Field Descriptions
    • Chapter7 L2 Look-Aside Cache/SRAM
      • 7.1 L2 Cache Overview
        • Figure7-1. L2 Cache/SRAM Configuration
        • 7.1.1 L2 Cache and SRAM Features
      • 7.2 Cache Organization
        • Figure7-2. Cache Organization
        • Figure7-3. 256-Kbyte L2 Cache Address Configuration�Full Cache Mode
        • Figure7-4. 128-Kbyte L2 Cache Address Configuration�Half SRAM, Half Cache Mode
        • Figure7-5. Data Bus Connection of CCB
        • Figure7-6. Address Bus Connection of CCB
      • 7.3 Memory Map/Register Definition
        • Table7-1. L2/SRAM Memory-Mapped Registers
        • 7.3.1 L2/SRAM Register Descriptions
          • 7.3.1.1 L2 Control Register (L2CTL)
            • Figure7-7. L2 Control Register (L2CTL)
            • Table7-2. L2CTL Field Descriptions
          • 7.3.1.2 L2 Cache External Write Address Registers0�3 (L2CEWARn)
            • Figure7-8. L2 Cache External Write Address Registers (L2CEWARn)
            • Table7-3. L2CEWARn Field Descriptions
          • 7.3.1.3 L2 Cache External Write Control Registers 0�3 (L2CEWCRn)
            • Figure7-9. L2 Cache External Write Control Registers (L2CEWCR0�L2CEWCR3)
            • Table7-4. L2CEWCRn Field Descriptions
          • 7.3.1.4 L2 Memory-Mapped SRAM Base Address Registers0�1 (L2SRBARn)
            • Figure7-10. L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)
            • Table7-5. L2SRBARn Field Descriptions
          • 7.3.1.5 L2 Error Registers
            • 7.3.1.5.1 Error Injection Registers
              • Figure7-11. L2 Error Injection Mask High Register (L2ERRINJHI)
              • Table7-6. L2ERRINJHI Field Description
              • Figure7-12. L2 Error Injection Mask Low Register (L2ERRINJLO)
              • Table7-7. L2ERRINJLO Field Description
              • Figure7-13. L2 Error Injection Mask Control Register (L2ERRINJCTL)
              • Table7-8. L2ERRINJCTL Field Descriptions
            • 7.3.1.5.2 Error Control and Capture Registers
              • Figure7-14. L2 Error Capture Data High Register (L2CAPTDATAHI)
              • Table7-9. L2CAPTDATAHI Field Description
              • Figure7-15. L2 Error Capture Data Low Register (L2CAPTDATALO)
              • Table7-10. L2CAPTDATALO Field Description
              • Figure7-16. L2 Error Syndrome Register (L2CAPTECC)
              • Table7-11. L2CAPTECC Field Descriptions
              • Figure7-17. L2 Error Detect Register (L2ERRDET)
              • Table7-12. L2ERRDET Field Descriptions
              • Figure7-18. L2 Error Disable Register (L2ERRDIS)
              • Table7-13. L2ERRDIS Field Descriptions
              • Figure7-19. L2 Error Interrupt Enable Register (L2ERRINTEN)
              • Table7-14. L2ERRINTEN Field Descriptions
              • Figure7-20. L2 Error Attributes Capture Register (L2ERRATTR)
              • Table7-15. L2ERRATTR Field Descriptions
              • Figure7-21. L2 Error Address Capture Register (L2ERRADDR)
              • Table7-16. L2ERRADDR Field Description
              • Figure7-22. L2 Error Control Register (L2ERRCTL)
              • Table7-17. L2ERRCTL Field Descriptions
      • 7.4 External Writes to the L2 Cache (Cache Stashing)
      • 7.5 L2 Cache Timing
        • Table7-18. Fastest Read Timing�Hit in L2
      • 7.6 L2 Cache and SRAM Coherency
        • 7.6.1 L2 Cache Coherency Rules
        • 7.6.2 Memory-Mapped SRAM Coherency Rules
      • 7.7 L2 Cache Locking
        • 7.7.1 Locking the Entire L2 Cache
        • 7.7.2 Locking Programmed Memory Ranges
        • 7.7.3 Locking Selected Lines
        • 7.7.4 Clearing Locks on Selected Lines
        • 7.7.5 Flash Clearing of Instruction and Data Locks
        • 7.7.6 Locks with Stale Data
      • 7.8 PLRU L2 Replacement Policy
        • Figure7-23. L2 Cache Line Replacement Algorithm
        • 7.8.1 PLRU Bit Update Considerations
          • Table7-19. PLRU Bit Update Algorithm
        • 7.8.2 Allocation of Lines
          • Table7-20. PLRU-Based Victim Selection Mechanism
      • 7.9 L2 Cache Operation
        • 7.9.1 L2 Cache States
          • Table7-21. L2 Cache States
        • 7.9.2 Flash Invalidation of the L2 Cache
        • 7.9.3 L2 State Transitions
          • Table7-22. State Transitions Due to Core-Initiated Transactions
          • Table7-23. State Transitions Due to System-Initiated Transactions
      • 7.10 Initialization/Application Information
        • 7.10.1 Initialization
          • 7.10.1.1 L2 Cache Initialization
          • 7.10.1.2 Memory-Mapped SRAM Initialization
        • 7.10.2 Managing Errors
          • 7.10.2.1 ECC Errors
          • 7.10.2.2 Tag Parity Errors
  • PartIII Memory and I/O Interfaces
    • Chapter8 e500 Coherency Module
      • 8.1 Introduction
        • Figure8-1. e500 Coherency Module Block Diagram
        • 8.1.1 Overview
        • 8.1.2 Features
      • 8.2 Memory Map/Register Definition
        • Table8-1. ECM Memory Map
        • 8.2.1 Register Descriptions
          • 8.2.1.1 ECM CCB Address Configuration Register (EEBACR)
            • Figure8-2. ECM CCB Address Configuration Register (EEBACR)
            • Table8-2. EEBACR Field Descriptions
          • 8.2.1.2 ECM CCB Port Configuration Register (EEBPCR)
            • Figure8-3. ECM CCB Port Configuration Register (EEBPCR)
            • Table8-3. EEBPCR Field Descriptions
          • 8.2.1.3 ECM Error Detect Register (EEDR)
            • Figure8-4. ECM Error Detect Register (EEDR)
            • Table8-4. EEDR Field Descriptions
          • 8.2.1.4 ECM Error Enable Register (EEER)
            • Figure8-5. ECM Error Enable Register (EEER)
            • Table8-5. EEER Field Descriptions
          • 8.2.1.5 ECM Error Attributes Capture Register (EEATR)
            • Figure8-6. ECM Error Attributes Capture Register (EEATR)
            • Table8-6. EEATR Field Descriptions
          • 8.2.1.6 ECM Error Address Capture Register (EEADR)
            • Figure8-7. ECM Error Address Capture Register (EEADR)
            • Table8-7. EEADR Field Descriptions
      • 8.3 Functional Description
        • 8.3.1 I/O Arbiter
        • 8.3.2 CCB Arbiter
        • 8.3.3 Transaction Queue
        • 8.3.4 Global Data Multiplexor
        • 8.3.5 CCB Interface
      • 8.4 Initialization/Application Information
    • Chapter9 DDR Memory Controller
      • 9.1 Introduction
        • Figure9-1. DDR Memory Controller Simplified Block Diagram
      • 9.2 Features
        • 9.2.1 Modes of Operation
      • 9.3 External Signal Descriptions
        • 9.3.1 Signals Overview
          • Table9-1. DDR Memory Interface Signal Summary
          • Table9-2. Memory Address Signal Mappings
        • 9.3.2 Detailed Signal Descriptions
          • 9.3.2.1 Memory Interface Signals
            • Table9-3. Memory Interface Signals�Detailed Signal Descriptions
          • 9.3.2.2 Clock Interface Signals
            • Table9-4. Clock Signals�Detailed Signal Descriptions
          • 9.3.2.3 Debug Signals
      • 9.4 Memory Map/Register Definition
        • Table9-5. DDR Memory Controller Memory Map
        • 9.4.1 Register Descriptions
          • 9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)
            • Figure9-2. Chip Select Bounds Registers (CSn_BNDS)
            • Table9-6. CSn_BNDS Field Descriptions
          • 9.4.1.2 Chip Select Configuration (CSn_CONFIG)
            • Figure9-3. Chip Select Configuration Register (CSn_CONFIG)
            • Table9-7. CSn_CONFIG Field Descriptions
          • 9.4.1.3 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
            • Figure9-4. DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1)
            • Table9-8. TIMING_CFG_1 Field Descriptions
          • 9.4.1.4 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
            • Figure9-5. DDR SDRAM Timing Configuration Register 2 (TIMING_CFG_2)
            • Table9-9. TIMING_CFG_2 Register Field Descriptions
          • 9.4.1.5 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
            • Figure9-6. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
            • Table9-10. DDR_SDRAM_CFG Field Descriptions
          • 9.4.1.6 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
            • Figure9-7. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
            • Table9-11. DDR_SDRAM_MODE Field Descriptions
          • 9.4.1.7 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
            • Figure9-8. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
            • Table9-12. DDR_SDRAM_INTERVAL Field Descriptions
          • 9.4.1.8 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)
            • Figure9-9. Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)
            • Table9-13. DATA_ERR_INJECT_HI Field Descriptions
          • 9.4.1.9 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)
            • Figure9-10. Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)
            • Table9-14. DATA_ERR_INJECT_LO Field Descriptions
          • 9.4.1.10 Memory Data Path Error Injection Mask ECC (ECC_ERR_INJECT)
            • Figure9-11. Memory Data Path Error Injection Mask ECC Register (ECC_ERR_INJECT)
            • Table9-15. ECC_ERR_INJECT Field Descriptions
          • 9.4.1.11 Memory Data Path Read Capture High (CAPTURE_DATA_HI)
            • Figure9-12. Memory Data Path Read Capture High Register (CAPTURE_DATA_HI)
            • Table9-16. CAPTURE_DATA_HI Field Descriptions
          • 9.4.1.12 Memory Data Path Read Capture Low (CAPTURE_DATA_LO)
            • Figure9-13. Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO)
            • Table9-17. CAPTURE_DATA_LO Field Descriptions
          • 9.4.1.13 Memory Data Path Read Capture ECC (CAPTURE_ECC)
            • Figure9-14. Memory Data Path Read Capture ECC Register (CAPTURE_ECC)
            • Table9-18. CAPTURE_ECC Field Descriptions
          • 9.4.1.14 Memory Error Detect (ERR_DETECT)
            • Figure9-15. Memory Error Detect Register (ERR_DETECT)
            • Table9-19. ERR_DETECT Field Descriptions
          • 9.4.1.15 Memory Error Disable (ERR_DISABLE)
            • Figure9-16. Memory Error Disable Register (ERR_DISABLE)
            • Table9-20. ERR_DISABLE Field Descriptions
          • 9.4.1.16 Memory Error Interrupt Enable (ERR_INT_EN)
            • Figure9-17. Memory Error Interrupt Enable Register (ERR_INT_EN)
            • Table9-21. ERR_INT_EN Field Descriptions
          • 9.4.1.17 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)
            • Figure9-18. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
            • Table9-22. CAPTURE_ATTRIBUTES Field Descriptions
          • 9.4.1.18 Memory Error Address Capture (CAPTURE_ADDRESS)
            • Figure9-19. Memory Error Address Capture Register (CAPTURE_ADDRESS)
            • Table9-23. CAPTURE_ADDRESS Field Descriptions
          • 9.4.1.19 Single-Bit ECC Memory Error Management (ERR_SBE)
            • Figure9-20. Single-Bit ECC Memory Error Management Register (ERR_SBE)
            • Table9-24. ERR_SBE Field Descriptions
      • 9.5 Functional Description
        • Figure9-21. DDR Memory Controller Block Diagram
        • Figure9-22. Controller DLL Timing Loop
        • Figure9-23. Typical Dual Data Rate SDRAM Internal Organization
        • Figure9-24. Typical DDR SDRAM Interface Signals
        • Figure9-25. Example 256-Mbyte DDR SDRAM Configuration with ECC
        • 9.5.1 DDR SDRAM Interface Operation
          • Table9-25. Byte Lane to Data Relationship
          • 9.5.1.1 Supported DDR SDRAM Organizations
            • Table9-26. Supported DDR SDRAM Device Configurations
        • 9.5.2 DDR SDRAM Address Multiplexing
          • Table9-27. DDR SDRAM Address Multiplexing
        • 9.5.3 JEDEC Standard DDR SDRAM Interface Commands
          • Table9-28. SDRAM Command Table
        • 9.5.4 SDRAM Interface Timing
          • Table9-29. DDR SDRAM Interface Timing Intervals
          • Figure9-26. DDR SDRAM Burst Read Timing�ACTTORW=3, MCAS Latency=2
          • Figure9-27. DDR SDRAM Single-Beat (Double-Word) Write Timing�ACTTORW=3
          • Figure9-28. DDR SDRAM Burst Write Timing�ACTTORW=4
          • 9.5.4.1 Clock Distribution
            • Figure9-29. DDR SDRAM Clock Distribution Example
        • 9.5.5 DDR SDRAM Mode-Set Command Timing
          • Figure9-30. DDR SDRAM Mode-Set Command Timing
        • 9.5.6 DDR SDRAM Registered DIMM Mode
          • Figure9-31. Registered DDR SDRAM DIMM Burst Write Timing
        • 9.5.7 DDR SDRAM Write Timing Adjustments
          • Figure9-32. Write Timing Adjustments Example
        • 9.5.8 DDR SDRAM Refresh
          • 9.5.8.1 DDR SDRAM Refresh Timing
            • Figure9-33. DDR SDRAM Bank-Staggered Auto-Refresh Timing
          • 9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes
            • Table9-30. DDR SDRAM Power-Saving Modes Refresh Configuration
            • Figure9-34. DDR SDRAM Power-Down Mode
            • 9.5.8.2.1 Self-Refresh in Sleep Mode
              • Figure9-35. DDR SDRAM Self-Refresh Entry Timing
              • Figure9-36. DDR SDRAM Self-Refresh Exit Timing
        • 9.5.9 DDR Data Beat Ordering
          • Table9-31. Memory Controller�Data Beat Ordering
        • 9.5.10 Page Mode and Logical Bank Retention
        • 9.5.11 Error Checking and Correcting (ECC)
          • Table9-32. DDR SDRAM ECC Syndrome Encoding
          • Table9-33. DDR SDRAM ECC Syndrome Encoding (Check Bits)
        • 9.5.12 Error Management
          • Table9-34. Memory Controller Errors
      • 9.6 Initialization/Application Information
        • Table9-35. Memory Interface Configuration Register Initialization Parameters
        • 9.6.1 DDR SDRAM Initialization Sequence
    • Chapter10 Programmable Interrupt Controller
      • 10.1 Introduction
        • Table10-1. Interrupt Source Signalling Options
        • 10.1.1 Overview
          • Figure10-1. MPC8540 Interrupt Sources Block Diagram
        • 10.1.2 Features
        • 10.1.3 Interrupts to the Processor Core
          • Table10-2. Processor Interrupts Generated Outside the Core�Types and Sources
          • Table10-3. e500 Core-Generated Interrupts that Cause a Wake-up
        • 10.1.4 Modes of Operation
          • 10.1.4.1 Mixed Mode (GCR[M]=1)
          • 10.1.4.2 Pass-Through Mode (GCR[M]=0)
            • Figure10-2. Pass-Through Mode Example
        • 10.1.5 Interrupt Sources
          • 10.1.5.1 Interrupt Routing�Mixed Mode
          • 10.1.5.2 Internal Interrupt Sources
            • Table10-4. Internal Interrupt Assignments
      • 10.2 External Signal Descriptions
        • 10.2.1 Signal Overview
          • Table10-5. PIC Interface Signals 
        • 10.2.2 Detailed Signal Descriptions
          • Table10-6. Interrupt Signals�Detailed Signal Descriptions
      • 10.3 Memory Map/Register Definition
        • Table10-7. PIC Register Address Map 
        • 10.3.1 Global Registers
          • 10.3.1.1 Feature Reporting Register (FRR)
            • Figure10-3. Feature Reporting Register (FRR)
            • Table10-8. FRR Field Descriptions
          • 10.3.1.2 Global Configuration Register (GCR)
            • Figure10-4. Global Configuration Register (GCR)
            • Table10-9. GCR Field Descriptions
          • 10.3.1.3 Vendor Identification Register (VIR)
            • Figure10-5. Vendor Identification Register (VIR)
            • Table10-10. VIR Field Descriptions
          • 10.3.1.4 Processor Initialization Register (PIR)
            • Figure10-6. Processor Initialization Register (PIR)
            • Table10-11. PIR Field Descriptions
          • 10.3.1.5 IPI Vector/Priority Registers (IPIVPRn)
            • Figure10-7. IPI Vector/Priority Registers (IPIVPRn)
            • Table10-12. IPIVPRn Field Descriptions
          • 10.3.1.6 Spurious Vector Register (SVR)
            • Figure10-8. Spurious Vector Register (SVR)
            • Table10-13. SVR Field Descriptions
        • 10.3.2 Global Timer Registers
          • 10.3.2.1 Timer Frequency Reporting Register (TFRR)
            • Figure10-9. Timer Frequency Reporting Register (TFRR)
            • Table10-14. TFRR Field Descriptions
          • 10.3.2.2 Global Timer Current Count Registers (GTCCRn)
            • Figure10-10. Global Timer Current Count Registers (GTCCRn)
            • Table10-15. GTCCRn Field Descriptions
          • 10.3.2.3 Global Timer Base Count Registers (GTBCRn)
            • Figure10-11. Global Timer Base Count Registers (GTBCRn)
            • Table10-16. GTBCRn Field Descriptions
          • 10.3.2.4 Global Timer Vector/Priority Registers (GTVPRn)
            • Figure10-12. Global Timer Vector/Priority Registers (GTVPRn)
            • Table10-17. GTVPRn Field Descriptions
          • 10.3.2.5 Global Timer Destination Registers (GTDRn)
            • Figure10-13. Global Timer Destination Registers (GTDRn)
            • Table10-18. GTDRn Field Descriptions
          • 10.3.2.6 Timer Control Register (TCR)
            • Table10-19. Parameters for Hourly Interrupt Timer Cascade Example
            • Figure10-14. Example Calculation for Cascaded Timers
            • Figure10-15. Timer Control Register (TCR)
            • Table10-20. TCR Field Descriptions
        • 10.3.3 IRQ_OUT and Critical Interrupt Summary Registers
          • 10.3.3.1 IRQ_OUT Summary Register 0 (IRQSR0)
            • Figure10-16. IRQ_OUT Summary Register 0 (IRQSR0)
            • Table10-21. IRQSR0 Field Descriptions
          • 10.3.3.2 IRQ_OUT Summary Register 1 (IRQSR1)
            • Figure10-17. IRQ_OUT Summary Register 1 (IRQSR1)
            • Table10-22. IRQSR1 Field Descriptions
          • 10.3.3.3 Critical Interrupt Summary Register 0 (CISR0)
            • Figure10-18. Critical Interrupt Summary Register 0 (CISR0)
            • Table10-23. CISR0 Field Descriptions
          • 10.3.3.4 Critical Interrupt Summary Register 1 (CISR1)
            • Figure10-19. Critical Interrupt Summary Register 1 (CISR1)
            • Table10-24. CISR1 Field Descriptions
        • 10.3.4 Performance Monitor Mask Registers (PMMRs)
          • 10.3.4.1 Performance Monitor Mask Register (Lower) (PMnMR0)
            • Figure10-20. Performance Monitor Mask Registers (PMnMR0)
            • Table10-25. PMnMR0 Field Descriptions
          • 10.3.4.2 Performance Monitor Mask Registers (Upper) (PMnMR1)
            • Figure10-21. Performance Monitor Mask Registers (PMnMR1)
            • Table10-26. PMnMR1 Field Descriptions
        • 10.3.5 Message Registers
          • 10.3.5.1 Message Registers (MSGR0�MSGR3)
            • Figure10-22. Message Registers (MSGRs)
            • Table10-27. MSGRn Field Descriptions
          • 10.3.5.2 Message Enable Register (MER)
            • Figure10-23. Message Enable Register (MER)
            • Table10-28. MER Field Descriptions
          • 10.3.5.3 Message Status Register (MSR)
            • Figure10-24. Message Status Register (MSR)
            • Table10-29. MSR Field Descriptions
        • 10.3.6 Interrupt Source Configuration Registers
          • 10.3.6.1 External Interrupt Vector/Priority Registers (EIVPR0�EIVPR11)
            • Figure10-25. External Interrupt Vector/Priority Registers (EIVPR0�EIVPR11)
            • Table10-30. EIVPRn Field Descriptions
          • 10.3.6.2 External Interrupt Destination Registers (EIDR0�EIDR11)
            • Figure10-26. External Interrupt Destination Registers (EIDRn)
            • Table10-31. EIDRn Field Descriptions
          • 10.3.6.3 Internal Interrupt Vector/Priority Registers (IIVPR0�IIVPR31)
            • Figure10-27. Internal Interrupt Vector/Priority Registers (IIVPRn)
            • Table10-32. IIVPRn Field Descriptions
          • 10.3.6.4 Internal Interrupt Destination Registers (IIDR0�IIDR31)
            • Figure10-28. Internal Interrupt Destination Registers (IIDRn)
            • Table10-33. IIDRn Field Descriptions
          • 10.3.6.5 Messaging Interrupt Vector/Priority Registers (MIVPR0�MIVPR3)
            • Figure10-29. Messaging Interrupt Vector/Priority Registers (MIVPRn)
            • Table10-34. MIVPRn Field Descriptions
          • 10.3.6.6 Messaging Interrupt Destination Registers (MIDR0�MIDR3)
            • Figure10-30. Messaging Interrupt Destination Registers (MIDRn)
            • Table10-35. MIDRn Field Descriptions
        • 10.3.7 Per-CPU Registers
          • Table10-36. Per-CPU Registers�Private Access Address Offsets
          • Figure10-31. Per-CPU Register Address Decoding in a Four-Core Device
          • 10.3.7.1 Interprocessor Interrupt Dispatch Register (IPIDR0�IPIDR3)
            • Figure10-32. Interprocessor Interrupt Dispatch Registers (IPIDR0�IPIDR3)
            • Table10-37. IPIDRn Field Descriptions
          • 10.3.7.2 Processor Current Task Priority Register (CTPR)
            • Figure10-33. Processor Current Task Priority Register (CTPR)
            • Table10-38. CTPR Field Descriptions
          • 10.3.7.3 Who Am I Register (WHOAMI)
            • Figure10-34. Processor Who Am I Register (WHOAMI)
            • Table10-39. WHOAMI Field Descriptions
          • 10.3.7.4 Processor Interrupt Acknowledge Register (IACK)
            • Figure10-35. Processor Interrupt Acknowledge Register (IACK)
            • Table10-40. IACK Field Descriptions
          • 10.3.7.5 Processor End of Interrupt Register (EOI)
            • Figure10-36. End of Interrupt Register (EOI)
            • Table10-41. EOI Field Descriptions
      • 10.4 Functional Description
        • 10.4.1 Flow of Interrupt Control
          • Figure10-37. PIC Interrupt Processing Flow Diagram
          • 10.4.1.1 Interrupt Source Priority
          • 10.4.1.2 Processor Current Task Priority
          • 10.4.1.3 Interrupt Acknowledge
        • 10.4.2 Nesting of Interrupts
        • 10.4.3 Processor Initialization
        • 10.4.4 Spurious Vector Generation
        • 10.4.5 Messaging Interrupts
        • 10.4.6 Global Timers
        • 10.4.7 Reset of the PIC
      • 10.5 Initialization/Application Information
        • 10.5.1 Programming Guidelines
          • 10.5.1.1 PIC Registers
          • 10.5.1.2 Changing Interrupt Source Configuration
    • Chapter11 I2C Interface
      • 11.1 Introduction
        • Figure11-1. I2C Block Diagram
        • 11.1.1 Overview
        • 11.1.2 Features
        • 11.1.3 Modes of Operation
      • 11.2 External Signal Descriptions
        • 11.2.1 Signal Overview
          • Table11-1. I2C Interface Signal Description
        • 11.2.2 Detailed Signal Descriptions
          • Table11-2. I2C Interface Signal�Detailed Signal Descriptions
      • 11.3 Memory Map/Register Definition
        • Table11-3. I2C Memory Map
        • 11.3.1 Register Descriptions
          • 11.3.1.1 I2C Address Register (I2CADR)
            • Figure11-2. I2C Address Register (I2CADR)
            • Table11-4. I2CADR Field Descriptions
          • 11.3.1.2 I2C Frequency Divider Register (I2CFDR)
            • Figure11-3. I2C Frequency Divider Register (I2CFDR)
            • Table11-5. I2CFDR Field Descriptions
          • 11.3.1.3 I2C Control Register (I2CCR)
            • Figure11-4. I2C Control Register (I2CCR)
            • Table11-6. I2CCR Field Descriptions
          • 11.3.1.4 I2C Status Register (I2CSR)
            • Figure11-5. I2C Status Register (I2CSR)
            • Table11-7. I2CSR Field Descriptions
          • 11.3.1.5 I2C Data Register (I2CDR)
            • Figure11-6. I2C Data Register (I2CDR)
            • Table11-8. I2CDR Field Description
          • 11.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR)
            • Figure11-7. I2C Digital Filter Sampling Rate Register (I2CDFSRR)
            • Table11-9. I2CDFSRR Field Descriptions
      • 11.4 Functional Description
        • 11.4.1 Transaction Protocol
          • Figure11-8. I2C Interface Transaction Protocol
          • 11.4.1.1 START Condition
          • 11.4.1.2 Slave Address Transmission
          • 11.4.1.3 Repeated START Condition
          • 11.4.1.4 STOP Condition
          • 11.4.1.5 Protocol Implementation Details
            • 11.4.1.5.1 Transaction Monitoring�Implementation Details
            • 11.4.1.5.2 Control Transfer�Implementation Details
          • 11.4.1.6 Address Compare�Implementation Details
        • 11.4.2 Arbitration Procedure
          • 11.4.2.1 Arbitration Control
        • 11.4.3 Handshaking
        • 11.4.4 Clock Control
          • 11.4.4.1 Clock Synchronization
          • 11.4.4.2 Input Synchronization and Digital Filter
            • 11.4.4.2.1 Input Signal Synchronization
            • 11.4.4.2.2 Filtering of SCL and SDA Lines
          • 11.4.4.3 Clock Stretching
        • 11.4.5 Boot Sequencer Mode
          • 11.4.5.1 EEPROM Calling Address
          • 11.4.5.2 EEPROM Data Format
            • Figure11-9. EEPROM Data Format for One Register Preload Command
            • Figure11-10. EEPROM Contents
      • 11.5 Initialization/Application Information
        • 11.5.1 Initialization Sequence
        • 11.5.2 Generation of START
        • 11.5.3 Post-Transfer Software Response
        • 11.5.4 Generation of STOP
        • 11.5.5 Generation of Repeated START
        • 11.5.6 Generation of SCL When SDA Low
        • 11.5.7 Slave Mode Interrupt Service Routine
          • 11.5.7.1 Slave Transmitter and Received Acknowledge
          • 11.5.7.2 Loss of Arbitration and Forcing of Slave Mode
        • 11.5.8 Interrupt Service Routine Flowchart
          • Figure11-11. Example I2C Interrupt Service Routine Flowchart
    • Chapter12 DUART
      • 12.1 Overview
        • Figure12-1. UART Block Diagram
        • 12.1.1 Features
        • 12.1.2 Modes of Operation
      • 12.2 External Signal Descriptions
        • 12.2.1 Signal Overview
          • Table12-1. DUART Signal Overview
        • 12.2.2 Detailed Signal Descriptions
          • Table12-2. DUART Signals�Detailed Signal Descriptions
      • 12.3 Memory Map/Register Definition
        • Table12-3. DUART Register Summary
        • 12.3.1 Register Descriptions
          • 12.3.1.1 Receiver Buffer Registers (URBR0, URBR1)
            • Figure12-2. Receiver Buffer Registers (URBR0, URBR1)
            • Table12-4. URBR Field Definition
          • 12.3.1.2 Transmitter Holding Registers (UTHR0, UTHR1)
            • Figure12-3. Transmitter Holding Registers (UTHR0, UTHR1)
            • Table12-5. UTHR Field Definition
          • 12.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
            • Figure12-4. Divisor Most Significant Byte Registers (UDMB0, UDMB1)
            • Table12-6. UDMB Field Definition
            • Figure12-5. Divisor Least Significant Byte Registers (UDLB0, UDLB1)
            • Table12-7. UDLB Field Definition
            • Table12-8. Baud Rate Examples
          • 12.3.1.4 Interrupt Enable Register (UIER)
            • Figure12-6. Interrupt Enable Register (UIER)
            • Table12-9. UIER Field Definitions
          • 12.3.1.5 Interrupt ID Registers (UIIR0, UIIR1)
            • Figure12-7. Interrupt ID Registers (UIIR)
            • Table12-10. UIIR Field Definitions
            • Table12-11. UIIR IID Bits Summary
          • 12.3.1.6 FIFO Control Registers (UFCR0, UFCR1)
            • Figure12-8. FIFO Control Registers (UFCR0, UFCR1)
            • Table12-12. UFCR Field Definitions
          • 12.3.1.7 Line Control Registers (ULCR0, ULCR1)
            • Figure12-9. Line Control Register (ULCR)
            • Table12-13. ULCR Field Definitions
            • Table12-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS]
          • 12.3.1.8 MODEM Control Registers (UMCR0, UMCR1)
            • Figure12-10. Modem Control Register (UMCR)
            • Table12-15. UMCR Field Definitions
          • 12.3.1.9 Line Status Registers (ULSR0, ULSR1)
            • Figure12-11. Line Status Register (ULSR)
            • Table12-16. ULSR Field Definitions
          • 12.3.1.10 MODEM Status Registers (UMSR0, UMSR1)
            • Figure12-12. Modem Status Register (UMSR)
            • Table12-17. UMSR Field Definitions
          • 12.3.1.11 Scratch Registers (USCR0, USCR1)
            • Figure12-13. Scratch Register (USCR)
            • Table12-18. USCR Field Definitions
          • 12.3.1.12 Alternate Function Registers (UAFR0, UAFR1)
            • Figure12-14. Alternate Function Register (UAFR)
            • Table12-19. UAFR Field Definitions
          • 12.3.1.13 DMA Status Registers (UDSR0, UDSR1)
            • Figure12-15. DMA Status Register (UDSR)
            • Table12-20. UDSR Field Definitions
            • Table12-21. UDSR[TXRDY] Set Conditions
            • Table12-22. UDSR[TXRDY] Cleared Conditions
            • Table12-23. UDSR[RXRDY] Set Conditions
            • Table12-24. UDSR[RXRDY] Cleared
      • 12.4 Functional Description
        • 12.4.1 Serial Interface
          • Figure12-16. UART Bus Interface Transaction Protocol Example
          • 12.4.1.1 START Bit
          • 12.4.1.2 Data Transfer
          • 12.4.1.3 Parity Bit
          • 12.4.1.4 STOP Bit
        • 12.4.2 Baud-Rate Generator Logic
        • 12.4.3 Local Loop-Back Mode
        • 12.4.4 Errors
          • 12.4.4.1 Framing Error
          • 12.4.4.2 Parity Error
          • 12.4.4.3 Overrun Error
        • 12.4.5 FIFO Mode
          • 12.4.5.1 FIFO Interrupts
          • 12.4.5.2 DMA Mode Select
          • 12.4.5.3 Interrupt Control Logic
      • 12.5 DUART Initialization/Application Information
    • Chapter13 Local Bus Controller
      • 13.1 Introduction
        • Figure13-1. Local Bus Controller Block Diagram
        • 13.1.1 Overview
        • 13.1.2 Features
        • 13.1.3 Modes of Operation
          • 13.1.3.1 LBC Bus Clock and Clock Ratios
          • 13.1.3.2 Source ID Debug Mode
        • 13.1.4 Power-Down Mode
        • 13.1.5 References
      • 13.2 External Signal Descriptions
        • Table13-1. Signal Properties�Summary
        • Table13-2. Local Bus Controller Detailed Signal Descriptions
      • 13.3 Memory Map/Register Definition
        • Table13-3. Local Bus Controller Memory Map
        • 13.3.1 Register Descriptions
          • 13.3.1.1 Base Registers (BR0�BR7)
            • Figure13-2. Base Registers (BRn)
            • Table13-4. BRn Field Descriptions
          • 13.3.1.2 Option Registers (OR0�OR7)
            • 13.3.1.2.1 Address Mask
              • Table13-5. Memory Bank Sizes in Relation to Address Mask
            • 13.3.1.2.2 Option Registers (ORn)�GPCM Mode
              • Figure13-3. Option Registers (ORn) in GPCM Mode
              • Table13-6. ORn�GPCM Field Descriptions
            • 13.3.1.2.3 Option Registers (ORn)�UPM Mode
              • Figure13-4. Option Registers (ORn) in UPM Mode
              • Table13-7. ORn�UPM Field Descriptions
            • 13.3.1.2.4 Option Registers (ORn)�SDRAM Mode
              • Figure13-5. Option Registers (ORn) in SDRAM Mode
              • Table13-8. ORn�SDRAM Field Descriptions
          • 13.3.1.3 UPM Memory Address Register (MAR)
            • Figure13-6. UPM Memory Address Register (MAR)
            • Table13-9. MAR Field Description
          • 13.3.1.4 UPM Mode Registers (MxMR)
            • Figure13-7. UPM Mode Registers (MxMR)
            • Table13-10. MxMR Field Descriptions
          • 13.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR)
            • Figure13-8. Memory Refresh Timer Prescaler Register (MRTPR)
            • Table13-11. MRTPR Field Descriptions
          • 13.3.1.6 UPM Data Register (MDR)
            • Figure13-9. UPM Data Register (MDR)
            • Table13-12. MDR Field Description
          • 13.3.1.7 SDRAM Machine Mode Register (LSDMR)
            • Figure13-10. SDRAM Machine Mode Register (LSDMR)
            • Table13-13. LSDMR Field Descriptions
          • 13.3.1.8 UPM Refresh Timer (LURT)
            • Figure13-11. UPM Refresh Timer (LURT)
            • Table13-14. LURT Field Descriptions
          • 13.3.1.9 SDRAM Refresh Timer (LSRT)
            • Figure13-12. LSRT SDRAM Refresh Timer (LSRT)
            • Table13-15. LSRT Field Descriptions
          • 13.3.1.10 Transfer Error Status Register (LTESR)
            • Figure13-13. Transfer Error Status Register (LTESR)
            • Table13-16. LTESR Field Descriptions
          • 13.3.1.11 Transfer Error Check Disable Register (LTEDR)
            • Figure13-14. Transfer Error Check Disable Register (LTEDR)
            • Table13-17. LTEDR Field Descriptions
          • 13.3.1.12 Transfer Error Interrupt Enable Register (LTEIR)
            • Figure13-15. Transfer Error Interrupt Enable Register (LTEIR)
            • Table13-18. LTEIR Field Descriptions
          • 13.3.1.13 Transfer Error Attributes Register (LTEATR)
            • Figure13-16. Transfer Error Attributes Register (LTEATR)
            • Table13-19. LTEATR Field Descriptions
          • 13.3.1.14 Transfer Error Address Register (LTEAR)
            • Figure13-17. Transfer Error Address Register (LTEAR)
            • Table13-20. LTEAR Field Descriptions 
          • 13.3.1.15 Local Bus Configuration Register (LBCR)
            • Figure13-18. Local Bus Configuration Register
            • Table13-21. LBCR Field Descriptions
          • 13.3.1.16 Clock Ratio Register (LCRR)
            • Figure13-19. Clock Ratio Register (LCRR)
            • Table13-22. LCRR Field Descriptions
      • 13.4 Functional Description
        • Figure13-20. Basic Operation of Memory Controllers in the LBC
        • 13.4.1 Basic Architecture
          • 13.4.1.1 Address and Address Space Checking
          • 13.4.1.2 External Address Latch Enable Signal (LALE)
            • Figure13-21. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420
          • 13.4.1.3 Data Transfer Acknowledge (TA)
            • Figure13-22. Basic LBC Bus Cycle with LALE, TA, and LCSn
          • 13.4.1.4 Data Buffer Control (LBCTL)
          • 13.4.1.5 Atomic Operation
          • 13.4.1.6 Parity Generation and Checking (LDP)
          • 13.4.1.7 Bus Monitor
        • 13.4.2 General-Purpose Chip-Select Machine (GPCM)
          • Figure13-23. Local Bus to GPCM Device Interface
          • Figure13-24. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV=4,8)
          • 13.4.2.1 Timing Configuration
            • Table13-23. GPCM Write Control Signal Timing for LCRR[CLKDIV]=4 or 8
            • Table13-24. GPCM Read Control Signal Timing for LCRR[CLKDIV]=4 or 8
            • Table13-25. GPCM Write Control Signal Timing for LCRR[CLKDIV]=2
            • Table13-26. GPCM Read Control Signal Timing for LCRR[CLKDIV]=2
          • 13.4.2.2 Chip-Select Assertion Timing
            • 13.4.2.2.1 Programmable Wait State Configuration
            • 13.4.2.2.2 Chip-Select and Write Enable Negation Timing
              • Figure13-25. GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = ...
            • 13.4.2.2.3 Relaxed Timing
              • Figure13-26. GPCM Relaxed Timing Read (XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX=1, CLKDIV =...
              • Figure13-27. GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRL...
              • Figure13-28. GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1, TRLX = 1, CLKDIV ...
              • Figure13-29. GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV ...
            • 13.4.2.2.4 Output Enable (LOE) Timing
            • 13.4.2.2.5 Extended Hold Time on Read Accesses
              • Figure13-30. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
              • Figure13-31. GPCM Read Followed by Write (TRLX = 0, EHTR = 1, 1-Cycle Extended Hold Time on Reads)
          • 13.4.2.3 External Access Termination (LGTA)
            • Figure13-32. External Termination of GPCM Access
          • 13.4.2.4 Boot Chip-Select Operation
            • Table13-27. Boot Bank Field Values after Reset
        • 13.4.3 SDRAM Machine
          • 13.4.3.1 Supported SDRAM Configurations
            • Figure13-33. Connection to a 32-Bit SDRAM with 12 Address Lines
          • 13.4.3.2 SDRAM Power-On Initialization
          • 13.4.3.3 Intel PC133 and JEDEC-Standard SDRAM Interface Commands
            • Table13-28. SDRAM Interface Commands
          • 13.4.3.4 Page Hit Checking
          • 13.4.3.5 Page Management
          • 13.4.3.6 SDRAM Address Multiplexing
            • Figure13-34. SDRAM Address Multiplexing
          • 13.4.3.7 SDRAM Device-Specific Parameters
            • 13.4.3.7.1 Precharge-to-Activate Interval
              • Figure13-35. PRETOACT = 2 (2 Clock Cycles)
            • 13.4.3.7.2 Activate-to-Read/Write Interval
              • Figure13-36. ACTTORW = 2 (2 Clock Cycles)
            • 13.4.3.7.3 Column Address to First Data Out�CAS Latency
              • Figure13-37. CL = 2 (2 Clock Cycles)
            • 13.4.3.7.4 Last Data In to Precharge�Write Recovery
              • Figure13-38. WRC = 2 (2 Clock Cycles)
            • 13.4.3.7.5 Refresh Recovery Interval (RFRC)
              • Figure13-39. RFRC = 4 (6 Clock Cycles)
            • 13.4.3.7.6 External Address and Command Buffers (BUFCMD)
              • Figure13-40. BUFCMD = 1, LCRR[BUFCMDC] = 2
          • 13.4.3.8 SDRAM Interface Timing
            • Figure13-41. SDRAM Single-Beat Read, Page Closed, CL = 3
            • Figure13-42. SDRAM Single-Beat Read, Page Hit, CL = 3
            • Figure13-43. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
            • Figure13-44. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
            • Figure13-45. SDRAM Single-Beat Write, Page Hit.
            • Figure13-46. SDRAM Three-Beat Write, Page Closed
            • Figure13-47. SDRAM Read-after-Read Pipelined, Page Hit, CL = 3
            • Figure13-48. SDRAM Write-after-Write Pipelined, Page Hit
            • Figure13-49. SDRAM Read-after-Write Pipelined, Page Hit
          • 13.4.3.9 SDRAM Read/Write Transactions
          • 13.4.3.10 SDRAM MODE-SET Command Timing
            • Figure13-50. SDRAM MODE-SET Command
          • 13.4.3.11 SDRAM Refresh
            • 13.4.3.11.1 SDRAM Refresh Timing
              • Figure13-51. SDRAM Bank-Staggered Auto-Refresh Timing
        • 13.4.4 User-Programmable Machines (UPMs)
          • Figure13-52. User-Programmable Machine Functional Block Diagram
          • 13.4.4.1 UPM Requests
            • Figure13-53. RAM Array Indexing
            • Table13-29. UPM Routines Start Addresses
            • 13.4.4.1.1 Memory Access Requests
            • 13.4.4.1.2 UPM Refresh Timer Requests
              • Figure13-54. Memory Refresh Timer Request Block Diagram
            • 13.4.4.1.3 Software Requests�RUN Command
            • 13.4.4.1.4 Exception Requests
          • 13.4.4.2 Programming the UPMs
          • 13.4.4.3 UPM Signal Timing
            • Figure13-55. UPM Clock Scheme for LCRR[CLKDIV]=2
            • Figure13-56. UPM Clock Scheme for LCRR[CLKDIV]=4 or 8
          • 13.4.4.4 RAM Array
            • Figure13-57. RAM Array and Signal Generation
            • 13.4.4.4.1 RAM Words
              • Figure13-58. RAM Word Field Descriptions
              • Table13-30. RAM Word Field Descriptions
            • 13.4.4.4.2 Chip-Select Signal Timing (CSTn)
              • Figure13-59. LCSn Signal Selection
            • 13.4.4.4.3 Byte Select Signal Timing (BSTn)
              • Figure13-60. LBS Signal Selection
            • 13.4.4.4.4 General-Purpose Signals (GnTn, GOn)
            • 13.4.4.4.5 Loop Control (LOOP)
              • Table13-31. MxMR Loop Field Use
            • 13.4.4.4.6 Repeat Execution of Current RAM Word (REDO)
            • 13.4.4.4.7 Address Multiplexing (AMX)
              • Table13-32. UPM Address Multiplexing
            • 13.4.4.4.8 Data Valid and Data Sample Control (UTA)
              • Figure13-61. UPM Read Access Data Sampling
            • 13.4.4.4.9 LGPL[0:5] Signal Negation (LAST)
            • 13.4.4.4.10 Wait Mechanism (WAEN)
              • Figure13-62. Effect of LUPWAIT Signal
          • 13.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
          • 13.4.4.6 Extended Hold Time on Read Accesses
          • 13.4.4.7 Memory System Interface Example Using UPM
            • Figure13-63. Single-Beat Read Access to FPM DRAM
            • Figure13-64. Single-Beat Write Access to FPM DRAM
            • Figure13-65. Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)
            • Figure13-66. Refresh Cycle (CBR) to FPM DRAM
            • Figure13-67. Exception Cycle
      • 13.5 Initialization/Application Information
        • 13.5.1 Interfacing to Peripherals
          • 13.5.1.1 Multiplexed Address/Data Bus and Unmultiplexed Address Signals
            • Figure13-68. Multiplexed Address/Data Bus
          • 13.5.1.2 Peripheral Hierarchy on the Local Bus
            • Figure13-69. Local Bus Peripheral Hierarchy
          • 13.5.1.3 Peripheral Hierarchy on the Local Bus for Very High Bus Speeds
            • Figure13-70. Local Bus Peripheral Hierarchy for Very High Bus Speeds
          • 13.5.1.4 GPCM Timings
            • Figure13-71. GPCM Address Timings
            • Figure13-72. GPCM Data timings
        • 13.5.2 Bus Turnaround
          • 13.5.2.1 Address Phase After Previous Read
          • 13.5.2.2 Read Data Phase After Address Phase
          • 13.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks
          • 13.5.2.4 UPM Cycles with Additional Address Phases
        • 13.5.3 Interface to Different Port-Size Devices
          • Figure13-73. Interface to Different Port-Size Devices
          • Table13-33. Data Bus Requirements For Read Cycle
        • 13.5.4 Interfacing to SDRAM
          • 13.5.4.1 Basic SDRAM Capabilities of the Local Bus
          • 13.5.4.2 Maximum Amount of SDRAM Supported
            • Table13-34. Micron SDRAM Devices
          • 13.5.4.3 SDRAM Machine Limitations
            • 13.5.4.3.1 Analysis of Maximum Row Number Due to Bank Select Multiplexing
            • 13.5.4.3.2 Bank Select Signals
            • 13.5.4.3.3 128-Mbyte SDRAM
              • Figure13-74. 128-Mbyte SDRAM Diagram
              • Table13-35. LADn Signal Connections to 128-Mbyte SDRAM
              • Table13-36. Logical Address Bus Partitioning
              • Table13-37. SDRAM Device Address Port during Address Phase
              • Table13-38. SDRAM Device Address Port during READ/WRITE Command
              • Table13-39. Register Settings for 128-Mbytes SDRAMs
            • 13.5.4.3.4 256-Mbyte SDRAM
            • 13.5.4.3.5 512-Mbyte SDRAM
              • Table13-40. Logical Address Partitioning
              • Table13-41. SDRAM Device Address Port During Address Phase
              • Table13-42. SDRAM Device Address Port During READ/WRITE Command
              • Table13-43. Register Settings for 512-Mbyte SDRAMs
            • 13.5.4.3.6 Power-Down Mode
              • Figure13-75. SDRAM Power-Down Timing
            • 13.5.4.3.7 Self-Refresh
              • Figure13-76. SDRAM Self-Refresh Mode Timing
            • 13.5.4.3.8 SDRAM Timing
              • Table13-44. SDRAM Capacitance
              • Table13-45. SDRAM AC Characteristics
              • Figure13-77. Local Bus DLL Operation
          • 13.5.4.4 Parity Support for SDRAM
            • Figure13-78. Parity Support for SDRAM
        • 13.5.5 Interfacing to ZBT SRAM
          • Figure13-79. Interface to ZBT SRAM
        • 13.5.6 Interfacing to DSP Host Ports
          • 13.5.6.1 Interfacing to MSC8101 HDI16
            • 13.5.6.1.1 HDI16 Peripherals
              • Figure13-80. MSC8101 HDI16 Peripheral Registers
            • 13.5.6.1.2 Physical Interconnections
              • Table13-46. Local Bus to MSC8101 HDI16 Connections
              • Figure13-81. Interface to MSC8101 HDI16
            • 13.5.6.1.3 Supporting Burst Transfers
            • 13.5.6.1.4 Host 60x Bus: HDI16 Peripheral Interface Hardware Timings
          • 13.5.6.2 Interfacing to MSC8102 DSI
            • 13.5.6.2.1 DSI in Asynchronous SRAM-Like Mode
              • Figure13-82. Interface to MSC8102 DSI in Asynchronous Mode
              • Figure13-83. Asynchronous Write to MSC8102 DSI
              • Figure13-84. Asynchronous Read from MSC8102 DSI
            • 13.5.6.2.2 DSI in Synchronous Mode
              • Figure13-85. Interface to MSC8102 DSI in Synchronous Mode
              • Figure13-86. UPM Synchronization Cycle
              • Table13-47. UPM Synchronization Cycles
              • Figure13-87. Synchronous Single Write to MSC8102 DSI
              • Figure13-88. Synchronous Single Read from MSC8102 DSI
              • Figure13-89. Synchronous Burst Write to MSC8102 DSI
              • Figure13-90. Synchronous Burst Read from MSC8102 DSI
            • 13.5.6.2.3 Broadcast Accesses
          • 13.5.6.3 Interfacing to EHPI from Texas Instruments TMS320Cxxxx DSPs
            • Table13-48. EHPI Signals
            • Figure13-91. Interface to Texas Instruments EHPI in Non-Multiplexed Mode
            • Figure13-92. EHPI Non-Multiplexed Read Timings
            • Figure13-93. EHPI Non-Multiplexed Write Timings
            • 13.5.6.3.1 Expansion to Multiple DSPs
    • Chapter14 Three-Speed Ethernet Controllers
      • 14.1 Introduction
        • Figure14-1. Ethernet Protocol in Relation to the OSI Protocol Stack
        • Figure14-2. IEEE 802.3z and 802.3ab Physical Standards
        • Figure14-3. Ethernet/IEEE 802.3 Frame Structure
        • Figure14-4. Ethernet/IEEE 802.3 Frame Structure With More Details
        • Figure14-5. TSEC Block Diagram
        • 14.1.1 Three-Speed Ethernet Controller Overview
      • 14.2 Features
      • 14.3 Modes of Operation
      • 14.4 External Signal Descriptions
        • 14.4.1 Detailed Signal Descriptions
          • Table14-1. TSEC Signals�Detailed Signal Descriptions
      • 14.5 Memory Map/Register Definition
        • 14.5.1 Top-Level Module Memory Map
          • Table14-2. Module Memory Map Summary
        • 14.5.2 Detailed Memory Map�Control/Status Registers
          • Table14-3. Module Memory Map 
        • 14.5.3 Memory-Mapped Register Descriptions
          • 14.5.3.1 TSEC General Control and Status Registers
            • 14.5.3.1.1 Interrupt Event Register (IEVENT)
              • Figure14-6. IEVENT Register Definition
              • Table14-4. IEVENT Field Descriptions
            • 14.5.3.1.2 Interrupt Mask Register (IMASK)
              • Figure14-7. IMASK Register Definition
              • Table14-5. IMASK Field Descriptions
            • 14.5.3.1.3 Error Disabled Register (EDIS)
              • Figure14-8. Error Disabled Register (EDIS)
              • Table14-6. EDIS Field Descriptions
            • 14.5.3.1.4 Ethernet Control Register (ECNTRL)
              • Figure14-9. ECNTRL Register Definition
              • Table14-7. ECNTRL Field Descriptions
            • 14.5.3.1.5 Minimum Frame Length Register (MINFLR)
              • Figure14-10. MINFLR Register Definition
              • Table14-8. MINFLR Field Descriptions
            • 14.5.3.1.6 Pause Time Value Register (PTV)
              • Figure14-11. PTV Register Definition
              • Table14-9. PTV Field Descriptions
            • 14.5.3.1.7 DMA Control Register (DMACTRL)
              • Figure14-12. DMACTRL Register Definition
              • Table14-10. DMACTRL Field Descriptions
            • 14.5.3.1.8 TBI Physical Address Register (TBIPA)
              • Figure14-13. TBIPA Register Definition
              • Table14-11. TBIPA Field Descriptions
          • 14.5.3.2 TSEC FIFO Control and Status Registers
            • 14.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)
              • Figure14-14. FIFO_PAUSE_CTRL Register Definition
              • Table14-12. FIFO_PAUSE_CTRL Field Descriptions
            • 14.5.3.2.2 FIFO Transmit Threshold Register (FIFO_TX_THR)
              • Figure14-15. FIFO_TX_THR Register Definition
              • Table14-13. FIFO_TX_THR Field Descriptions
            • 14.5.3.2.3 FIFO Transmit Starve Register (FIFO_TX_STARVE)
              • Figure14-16. FIFO_TX_STARVE Register Definition
              • Table14-14. FIFO_TX_STARVE Field Descriptions
            • 14.5.3.2.4 FIFO Transmit Starve Shutoff Register (FIFO_TX_STARVE_SHUTOFF)
              • Figure14-17. FIFO_TX_STARVE_SHUTOFF Register Definition
              • Table14-15. FIFO_TX_STARVE_SHUTOFF Field Descriptions
          • 14.5.3.3 TSEC Transmit Control and Status Registers
            • 14.5.3.3.1 Transmit Control Register (TCTRL)
              • Figure14-18. TCTRL Register Definition
              • Table14-16. TCTRL Field Descriptions
            • 14.5.3.3.2 Transmit Status Register (TSTAT)
              • Figure14-19. TSTAT Register Definition
              • Table14-17. TSTAT Field Descriptions
            • 14.5.3.3.3 TxBD Data Length Register (TBDLEN)
              • Figure14-20. TBDLEN Register Definition
              • Table14-18. TBDLEN Field Descriptions
            • 14.5.3.3.4 Transmit Interrupt Coalescing Configuration Register (TXIC)
              • Figure14-21. TXIC Register Definition
              • Table14-19. TXIC Field Descriptions
            • 14.5.3.3.5 Current Transmit Buffer Descriptor Pointer Register (CTBPTR)
              • Figure14-22. CTBPTR Register Definition
              • Table14-20. CTBPTR Field Descriptions
            • 14.5.3.3.6 Transmit Buffer Descriptor Pointer Register (TBPTR)
              • Figure14-23. TBPTR Register Definition
              • Table14-21. TBPTR Field Descriptions
            • 14.5.3.3.7 Transmit Descriptor Base Address Register (TBASE)
              • Figure14-24. TBASE Register Definition
              • Table14-22. TBASE Field Descriptions
            • 14.5.3.3.8 Out-of-Sequence TxBD Register (OSTBD)
              • Figure14-25. OSTBD Register Definition
              • Table14-23. OSTBD Field Descriptions
            • 14.5.3.3.9 Out-of-Sequence Tx Data Buffer Pointer Register (OSTBDP)
              • Figure14-26. OSTBDP Register Definition
              • Table14-24. OSTBDP Field Descriptions
          • 14.5.3.4 TSEC Receive Control and Status Registers
            • 14.5.3.4.1 Receive Control Register (RCTRL)
              • Figure14-27. RCTRL Register Definition
              • Table14-25. RCTRL Field Descriptions
            • 14.5.3.4.2 Receive Status Register (RSTAT)
              • Figure14-28. RSTAT Register Definition
              • Table14-26. RSTAT Field Descriptions
            • 14.5.3.4.3 RxBD Data Length Register (RBDLEN)
              • Figure14-29. RBDLEN Register Definition
              • Table14-27. RBDLEN Field Descriptions
            • 14.5.3.4.4 Receive Interrupt Coalescing Configuration Register (RXIC)
              • Figure14-30. RXIC Register Definition
              • Table14-28. RXIC Field Descriptions
            • 14.5.3.4.5 Current Receive Buffer Descriptor Pointer Register (CRBPTR)
              • Figure14-31. CRBPTR Register Definition
              • Table14-29. CRBPTR Field Descriptions
            • 14.5.3.4.6 Maximum Receive Buffer Length Register (MRBLR)
              • Figure14-32. MRBL Register Definition
              • Table14-30. MRBLR Field Descriptions
            • 14.5.3.4.7 Receive Buffer Descriptor Pointer Register (RBPTR)
              • Figure14-33. RBPTR Register Definition
              • Table14-31. RBPTR Field Descriptions
            • 14.5.3.4.8 Receive Descriptor Base Address Register (RBASE)
              • Figure14-34. RBASE Register Definition
              • Table14-32. RBASE Field Descriptions
          • 14.5.3.5 MAC Functionality
            • 14.5.3.5.1 Configuring the MAC
            • 14.5.3.5.2 Controlling CSMA/CD
            • 14.5.3.5.3 Handling Packet Collisions
            • 14.5.3.5.4 Controlling Packet Flow
            • 14.5.3.5.5 Controlling PHY Links
          • 14.5.3.6 MAC Registers
            • 14.5.3.6.1 MAC Configuration Register 1 (MACCFG1)
              • Figure14-35. MACCFG1 Register Definition
              • Table14-33. MACCFG1 Field Descriptions
            • 14.5.3.6.2 MAC Configuration Register 2 (MACCFG2)
              • Figure14-36. MACCFG2 Register Definition
              • Table14-34. MACCFG2 Field Descriptions
            • 14.5.3.6.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
              • Figure14-37. IPGIFG Register Definition
              • Table14-35. IPGIFG Field Descriptions
            • 14.5.3.6.4 Half-Duplex Register (HAFDUP)
              • Figure14-38. Half-Duplex Register Definition
              • Table14-36. HAFDUP Field Descriptions
            • 14.5.3.6.5 Maximum Frame Length Register (MAXFRM)
              • Figure14-39. Maximum Frame Length Register Definition
              • Table14-37. MAXFRM Field Descriptions
            • 14.5.3.6.6 MII Management Configuration Register (MIIMCFG)
              • Figure14-40. MII Management Configuration Register Definition
              • Table14-38. MIIMCFG Field Descriptions
            • 14.5.3.6.7 MII Management Command Register (MIIMCOM)
              • Figure14-41. MIIMCOM Register Definition
              • Table14-39. MIIMCOM Field Descriptions
            • 14.5.3.6.8 MII Management Address Register (MIIMADD)
              • Figure14-42. MIIMADD Register Definition
              • Table14-40. MIIMADD Field Descriptions
            • 14.5.3.6.9 MII Management Control Register (MIIMCON)
              • Figure14-43. MII Management Control Register Definition
              • Table14-41. MIIMCON Field Descriptions
            • 14.5.3.6.10 MII Management Status Register (MIIMSTAT)
              • Figure14-44. MIIMSTAT Register Definition
              • Table14-42. MIIMSTAT Field Descriptions
            • 14.5.3.6.11 MII Management Indicator Register (MIIMIND)
              • Figure14-45. MII Management Indicator Register Definition
              • Table14-43. MIIMIND Field Descriptions
            • 14.5.3.6.12 Interface Status Register (IFSTAT)
              • Figure14-46. Interface Status Register Definition
              • Table14-44. IFSTAT Field Descriptions
            • 14.5.3.6.13 Station Address Register Part 1 (MACSTNADDR1)
              • Figure14-47. Station Address Part 1 Register Definition
              • Table14-45. MACSTNADDR1 Field Descriptions
            • 14.5.3.6.14 Station Address Register Part 2 (MACSTNADDR2)
              • Figure14-48. Station Address Part 2 Register Definition
              • Table14-46. MACSTNADDR2 Field Descriptions
          • 14.5.3.7 MIB Registers
            • 14.5.3.7.1 Transmit and Receive 64-Byte Frame Counter Register (TR64)
              • Figure14-49. Transmit and Receive 64-Byte Frame Register Definition
              • Table14-47. TR64 Field Descriptions
            • 14.5.3.7.2 Transmit and Receive 65- to 127-Byte Frame Counter Register (TR127)
              • Figure14-50. Transmit and Receive 65- to 127-Byte Frame Register Definition
              • Table14-48. TR127 Field Descriptions
            • 14.5.3.7.3 Transmit and Receive 128- to 255-Byte Frame Counter Register (TR255)
              • Figure14-51. Transmit and Receive 128- to 255-Byte Frame Register Definition
              • Table14-49. TR255 Field Descriptions
            • 14.5.3.7.4 Transmit and Receive 256- to 511-Byte Frame Counter Register (TR511)
              • Figure14-52. Transmit and Receive 256- to 511-Byte Frame Register Definition
              • Table14-50. TR511 Field Descriptions
            • 14.5.3.7.5 Transmit and Receive 512- to 1023-Byte Frame Counter Register (TR1K)
              • Figure14-53. Transmit and Receive 512- to 1023-Byte Frame Register Definition
              • Table14-51. TR1K Field Descriptions
            • 14.5.3.7.6 Transmit and Receive 1024- to 1518-Byte Frame Counter Register (TRMAX)
              • Figure14-54. Transmit and Receive 1024- to 1518-Byte Frame Register Definition
              • Table14-52. TRMAX Field Descriptions
            • 14.5.3.7.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter Register (TRMGV)
              • Figure14-55. Transmit and Receive 1519- to 1522-Byte VLAN Frame Register Definition
              • Table14-53. TRMGV Field Descriptions
            • 14.5.3.7.8 Receive Byte Counter Register (RBYT)
              • Figure14-56. Receive Byte Counter Register Definition
              • Table14-54. RBYT Field Descriptions
            • 14.5.3.7.9 Receive Packet Counter Register (RPKT)
              • Figure14-57. Receive Packet Counter Register Definition
              • Table14-55. RPKT Field Descriptions
            • 14.5.3.7.10 Receive FCS Error Counter Register (RFCS)
              • Figure14-58. Receive FCS Error Counter Register Definition
              • Table14-56. RFCS Field Descriptions
            • 14.5.3.7.11 Receive Multicast Packet Counter Register (RMCA)
              • Figure14-59. Receive Multicast Packet Counter Register Definition
              • Table14-57. RMCA Field Descriptions
            • 14.5.3.7.12 Receive Broadcast Packet Counter Register (RBCA)
              • Figure14-60. Receive Broadcast Packet Counter Register Definition
              • Table14-58. RBCA Field Descriptions
            • 14.5.3.7.13 Receive Control Frame Packet Counter Register (RXCF)
              • Figure14-61. Receive Control Frame Packet Counter Register Definition
              • Table14-59. RXCF Field Descriptions
            • 14.5.3.7.14 Receive Pause Frame Packet Counter Register (RXPF)
              • Figure14-62. Receive Pause Frame Packet Counter Register Definition
              • Table14-60. RXPF Field Descriptions
            • 14.5.3.7.15 Receive Unknown Opcode Packet Counter Register (RXUO)
              • Figure14-63. Receive Unknown Opcode Packet Counter Register Definition
              • Table14-61. RXUO Field Descriptions
            • 14.5.3.7.16 Receive Alignment Error Counter Register (RALN)
              • Figure14-64. Receive Alignment Error Counter Register Definition
              • Table14-62. RALN Field Descriptions
            • 14.5.3.7.17 Receive Frame Length Error Counter Register (RFLR)
              • Figure14-65. Receive Frame Length Error Counter Register Definition
              • Table14-63. RFLR Field Descriptions
            • 14.5.3.7.18 Receive Code Error Counter Register (RCDE)
              • Figure14-66. Receive Code Error Counter Register Definition
              • Table14-64. RCDE Field Descriptions
            • 14.5.3.7.19 Receive Carrier Sense Error Counter Register (RCSE)
              • Figure14-67. Receive Carrier Sense Error Counter Register Definition
              • Table14-65. RCSE Field Descriptions
            • 14.5.3.7.20 Receive Undersize Packet Counter Register (RUND)
              • Figure14-68. Receive Undersize Packet Counter Register Definition
              • Table14-66. RUND Field Descriptions
            • 14.5.3.7.21 Receive Oversize Packet Counter Register (ROVR)
              • Figure14-69. Receive Oversize Packet Counter Register Definition
              • Table14-67. ROVR Field Descriptions
            • 14.5.3.7.22 Receive Fragments Counter Register (RFRG)
              • Figure14-70. Receive Fragments Counter Register Definition
              • Table14-68. RFRG Field Descriptions
            • 14.5.3.7.23 Receive Jabber Counter Register (RJBR)
              • Figure14-71. Receive Jabber Counter Register Definition
              • Table14-69. RJBR Field Descriptions
            • 14.5.3.7.24 Receive Dropped Packet Counter Register (RDRP)
              • Figure14-72. Receive Dropped Packet Counter Register Definition
              • Table14-70. RDRP Field Descriptions
            • 14.5.3.7.25 Transmit Byte Counter Register (TBYT)
              • Figure14-73. Transmit Byte Counter Register Definition
              • Table14-71. TBYT Field Descriptions
            • 14.5.3.7.26 Transmit Packet Counter Register (TPKT)
              • Figure14-74. Transmit Packet Counter Register Definition
              • Table14-72. TPKT Field Descriptions
            • 14.5.3.7.27 Transmit Multicast Packet Counter Register (TMCA)
              • Figure14-75. Transmit Multicast Packet Counter Register Definition
              • Table14-73. TMCA Field Descriptions
            • 14.5.3.7.28 Transmit Broadcast Packet Counter Register (TBCA)
              • Figure14-76. Transmit Broadcast Packet Counter Register Definition
              • Table14-74. TBCA Field Descriptions
            • 14.5.3.7.29 Transmit Pause Control Frame Counter Register (TXPF)
              • Figure14-77. Transmit Pause Control Frame Counter Register Definition
              • Table14-75. TXPF Field Descriptions
            • 14.5.3.7.30 Transmit Deferral Packet Counter Register (TDFR)
              • Figure14-78. Transmit Deferral Packet Counter Register Definition
              • Table14-76. TDFR Field Descriptions
            • 14.5.3.7.31 Transmit Excessive Deferral Packet Counter Register (TEDF)
              • Figure14-79. Transmit Excessive Deferral Packet Counter Register Definition
              • Table14-77. TEDF Field Descriptions
            • 14.5.3.7.32 Transmit Single Collision Packet Counter Register (TSCL)
              • Figure14-80. Transmit Single Collision Packet Counter Register Definition
              • Table14-78. TSCL Field Descriptions
            • 14.5.3.7.33 Transmit Multiple Collision Packet Counter Register (TMCL)
              • Figure14-81. Transmit Multiple Collision Packet Counter Register Definition
              • Table14-79. TMCL Field Descriptions
            • 14.5.3.7.34 Transmit Late Collision Packet Counter Register (TLCL)
              • Figure14-82. Transmit Late Collision Packet Counter Register Definition
              • Table14-80. TLCL Field Descriptions
            • 14.5.3.7.35 Transmit Excessive Collision Packet Counter Register (TXCL)
              • Figure14-83. Transmit Excessive Collision Packet Counter Register Definition
              • Table14-81. TXCL Field Descriptions
            • 14.5.3.7.36 Transmit Total Collision Counter Register (TNCL)
              • Figure14-84. Transmit Total Collision Counter Register Definition
              • Table14-82. TNCL Field Descriptions
            • 14.5.3.7.37 Transmit Drop Frame Counter Register (TDRP)
              • Figure14-85. Transmit Drop Frame Counter Register Definition
              • Table14-83. TDRP Field Descriptions
            • 14.5.3.7.38 Transmit Jabber Frame Counter Register (TJBR)
              • Figure14-86. Transmit Jabber Frame Counter Register Definition
              • Table14-84. TJBR Field Descriptions
            • 14.5.3.7.39 Transmit FCS Error Counter Register (TFCS)
              • Figure14-87. Transmit FCS Error Counter Register Definition
              • Table14-85. TFCS Field Descriptions
            • 14.5.3.7.40 Transmit Control Frame Counter Register (TXCF)
              • Figure14-88. Transmit Control Frame Counter Register Definition
              • Table14-86. TXCF Field Descriptions
            • 14.5.3.7.41 Transmit Oversize Frame Counter Register (TOVR)
              • Figure14-89. Transmit Oversized Frame Counter Register Definition
              • Table14-87. TOVR Field Descriptions
            • 14.5.3.7.42 Transmit Undersize Frame Counter Register (TUND)
              • Figure14-90. Transmit Undersize Frame Counter Register Definition
              • Table14-88. TUND Field Descriptions
            • 14.5.3.7.43 Transmit Fragment Counter Register (TFRG)
              • Figure14-91. Transmit Fragment Counter Register Definition
              • Table14-89. TFRG Field Descriptions
            • 14.5.3.7.44 Carry Register 1 (CAR1)
              • Figure14-92. Carry Register 1 (CAR1) Register Definition
              • Table14-90. CAR1 Field Descriptions
            • 14.5.3.7.45 Carry Register 2 (CAR2)
              • Figure14-93. Carry Register 2 (CAR2) Register Definition
              • Table14-91. CAR2 Field Descriptions 
            • 14.5.3.7.46 Carry Mask Register 1 (CAM1)
              • Figure14-94. Carry Mask Register 1 (CAM1) Register Definition
              • Table14-92. CAM1 Field Descriptions 
            • 14.5.3.7.47 Carry Mask Register 2 (CAM2)
              • Figure14-95. Carry Mask Register 2 (CAM2) Register Definition
              • Table14-93. CAM2 Field Descriptions
          • 14.5.3.8 Hash Function Registers
            • 14.5.3.8.1 Individual Address Registers 0�7 (IADDRn)
              • Figure14-96. IADDRn Register Definition
              • Table14-94. IADDRn Field Description
            • 14.5.3.8.2 Group Address Registers 0�7 (GADDRn)
              • Figure14-97. GADDRn Register Definition
              • Table14-95. GADDRn Field Description
          • 14.5.3.9 Attribute Registers
            • 14.5.3.9.1 Attribute Register (ATTR)
              • Figure14-98. ATTR Register Definition
              • Table14-96. ATTR Field Descriptions 
            • 14.5.3.9.2 Attribute Extract Length and Extract Index Register (ATTRELI)
              • Figure14-99. ATTRELI Register Definition
              • Table14-97. ATTRELI Field Descriptions
        • 14.5.4 Ten-Bit Interface (TBI)
          • 14.5.4.1 TBI MII Set Register Descriptions
            • Table14-98. TBI MII Register Set 
          • 14.5.4.2 Control Register (CR)
            • Figure14-100. Control Register Definition
            • Table14-99. CR Field Descriptions
          • 14.5.4.3 Status Register (SR) 
            • Figure14-101. Status Register Definition
            • Table14-100. SR Descriptions 
          • 14.5.4.4 AN Advertisement Register (ANA)
            • Figure14-102. AN Advertisement Register Definition
            • Table14-101. ANA Field Descriptions
            • Table14-102. PAUSE Priority Resolution
          • 14.5.4.5 AN Link Partner Base Page Ability Register (ANLPBPA)
            • Figure14-103. AN Link Partner Base Page Ability Register Definition
            • Table14-103. ANLPBPA Field Descriptions 
          • 14.5.4.6 AN Expansion Register (ANEX)
            • Figure14-104. AN Expansion Register Definition
            • Table14-104. ANEX Field Descriptions 
          • 14.5.4.7 AN Next Page Transmit Register (ANNPT)
            • Figure14-105. AN Next Page Transmit Register Definition
            • Table14-105. ANNPT Field Descriptions 
          • 14.5.4.8 AN Link Partner Ability Next Page Register (ANLPANP)
            • Figure14-106. AN Link Partner Ability Next Page Register Definition
            • Table14-106. ANLPANP Field Descriptions 
          • 14.5.4.9 Extended Status Register (EXST)
            • Figure14-107. Extended Status Register Definition
            • Table14-107. EXST Field Descriptions
          • 14.5.4.10 Jitter Diagnostics Register (JD)
            • Figure14-108. Jitter Diagnostics Register Definition
            • Table14-108. JD Field Description
          • 14.5.4.11 TBI Control Register (TBICON)
            • Figure14-109. TBI Control Register Definition
            • Table14-109. TBICON Field Descriptions
      • 14.6 Functional Description
        • 14.6.1 Connecting to Physical Interfaces
          • 14.6.1.1 Media-Independent Interface (MII)
            • Figure14-110. TSEC-MII Connection
          • 14.6.1.2 Gigabit Media-Independent Interface (GMII)
            • Figure14-111. TSEC-GMII Connection
          • 14.6.1.3 Reduced Gigabit Media-Independent Interface (RGMII)
            • Figure14-112. TSEC-RGMII Connection
          • 14.6.1.4 Ten-Bit Interface (TBI)
            • Figure14-113. TSEC-TBI Connection
          • 14.6.1.5 Reduced Ten-Bit Interface (RTBI)
            • Figure14-114. TSEC-RTBI Connection
            • Table14-110. GMII, MII, and TBI Signal Multiplexing
            • Table14-111. RGMII and RTBI Signal Multiplexing
            • Table14-112. Shared Signals
        • 14.6.2 Gigabit Ethernet Channel Operation
          • 14.6.2.1 Initialization Sequence
            • 14.6.2.1.1 Hardware-Controlled Initialization
            • 14.6.2.1.2 User Initialization
              • Table14-113. Steps of Minimum Register Initialization
          • 14.6.2.2 Soft Reset and Reconfiguring Procedure
          • 14.6.2.3 Gigabit Ethernet Frame Transmission
          • 14.6.2.4 Gigabit Ethernet Frame Reception
          • 14.6.2.5 RMON Support
          • 14.6.2.6 Frame Recognition
            • 14.6.2.6.1 Destination Address Recognition
              • Figure14-115. Ethernet Address Recognition Flowchart
            • 14.6.2.6.2 Hash Table Algorithm
            • 14.6.2.6.3 CRC Computation Examples
          • 14.6.2.7 Flow Control
            • Table14-114. Flow Control Frame Structure 
          • 14.6.2.8 Interrupt Handling
            • Table14-115. Non-Error Transmit Interrupts
            • Table14-116. Non-Error Receive Interrupts 
            • 14.6.2.8.1 Interrupt Coalescing
            • 14.6.2.8.2 Interrupt Coalescing By Frame Count Threshold
            • 14.6.2.8.3 Interrupt Coalescing By Timer Threshold
              • Table14-117. Interrupt Coalescing Timing Threshold Ranges
          • 14.6.2.9 Inter-Packet Gap Time
          • 14.6.2.10 Internal and External Loop Back
          • 14.6.2.11 Error-Handling Procedure
            • Table14-118. Transmission Errors
            • Table14-119. Reception Errors 
        • 14.6.3 Buffer Descriptors
          • Figure14-116. Example of TSEC Memory Structure for BD
          • Figure14-117. Buffer Descriptor Ring
          • 14.6.3.1 Transmit Data Buffer Descriptor (TxBD)
            • Figure14-118. Transmit Buffer Descriptor
            • Table14-120. Transmit Data Buffer Descriptor (TxBD) Field Descriptions
          • 14.6.3.2 Receive Buffer Descriptor (RxBD)
            • Figure14-119. Receive Buffer Descriptor
            • Table14-121. Receive Buffer Descriptor Field Descriptions 
        • 14.6.4 Data Extraction to the L2 Cache
      • 14.7 Initialization/Application Information
        • 14.7.1 Interface Mode Configuration
          • 14.7.1.1 MII Interface Mode
            • Table14-122. MII Interface Mode Signal Configuration
            • Table14-123. Shared MII Signals 
            • Table14-124. MII Mode Register Initialization Steps
          • 14.7.1.2 GMII Interface Mode
            • Table14-125. GMII Interface Mode Signal Configuration
            • Table14-126. Shared GMII Signals 
            • Table14-127. GMII Mode Register Initialization Steps
          • 14.7.1.3 TBI Interface Mode
            • Table14-128. TBI Interface Mode Signal Configuration
            • Table14-129. Shared TBI Signals
            • Table14-130. TBI Mode Register Initialization Steps
          • 14.7.1.4 RGMII Interface Mode
            • Table14-131. RGMII Interface Mode Signal Configuration
            • Table14-132. Shared RGMII Signals 
            • Table14-133. RGMII Mode Register Initialization Steps
          • 14.7.1.5 RTBI Interface Mode
            • Table14-134. RTBI Interlace Mode Signal Configuration 
            • Table14-135. Shared RTBI Signals
            • Table14-136. RTBI Mode Register Initialization Steps
    • Chapter15 DMA Controller
      • 15.1 Introduction
        • 15.1.1 Block Diagram
          • Figure15-1. DMA Block Diagram
        • 15.1.2 Overview
        • 15.1.3 Features
        • 15.1.4 Modes of Operation
          • Table15-1. Relationship of Modes and Features 
          • Table15-2. DMA Mode Field Descriptions
          • Figure15-2. DMA Operational Flow Chart
      • 15.2 External Signal Descriptions
        • 15.2.1 Signal Overview
          • Figure15-3. DMA Signal Summary
        • 15.2.2 Detailed Signal Descriptions
          • Table15-3. DMA Signals�Detailed Signal Descriptions
      • 15.3 Memory Map/Register Definition
        • 15.3.1 Module Memory Map
          • Figure15-4. DMA Register Space (Memory-Mapped)
          • Table15-4. DMA Register Summary
        • 15.3.2 DMA Register Descriptions
          • 15.3.2.1 Mode Registers (MRn)
            • Figure15-5. DMA Mode Registers (MRn)
            • Table15-5. MRn Field Descriptions
          • 15.3.2.2 Status Registers (SRn)
            • Figure15-6. Status Registers (SRn)
            • Table15-6. SRn Field Descriptions
          • 15.3.2.3 Current Link Descriptor Address Registers (CLNDARn)
            • Figure15-7. Basic Chaining Mode Flow Chart
            • Figure15-8. Current Link Descriptor Address Registers (CLNDARn)
            • Table15-7. CLNDARn Field Descriptions
          • 15.3.2.4 Source Attributes Registers (SATRn)
            • Figure15-9. Source Attributes Registers (SATRn)
            • Table15-8. SATRn Field Descriptions
          • 15.3.2.5 Source Address Registers (SARn)
            • Figure15-10. Source Address Registers (SARn)
            • Table15-9. SARn Field Descriptions
            • 15.3.2.5.1 Source Address Registers for RapidIO Maintenance Reads (SARn)
              • Figure15-11. Source Address Registers for RapidIO Maintenance Reads (SARn)
              • Table15-10. SARn Field Descriptions
          • 15.3.2.6 Destination Attributes Registers (DATRn)
            • Figure15-12. Destination Attributes Registers (DATRn)
            • Table15-11. DATRn Field Descriptions
          • 15.3.2.7 Destination Address Registers (DARn)
            • Figure15-13. Destination Address Registers (DARn)
            • Table15-12. DARn Field Descriptions
            • 15.3.2.7.1 Destination Address Registers for RapidIO Maintenance Writes (DARn)
              • Figure15-14. Destination Address Registers for RapidIO Maintenance Writes (DARn)
              • Table15-13. DARn Field Descriptions
          • 15.3.2.8 Byte Count Registers (BCRn)
            • Figure15-15. Byte Count Registers (BCRn)
            • Table15-14. BCRn Field Descriptions
          • 15.3.2.9 Next Link Descriptor Address Registers (NLNDARn)
            • Figure15-16. Next Link Descriptor Address Registers (NLNDARn)
            • Table15-15. NLNDARn Field Descriptions
          • 15.3.2.10 Current List Descriptor Address Registers (CLSDARn)
            • Figure15-17. Current List Descriptor Address Registers (CLSDARn)
            • Table15-16. CLSDARn Field Descriptions
          • 15.3.2.11 Next List Descriptor Address Registers (NLSDARn)
            • Figure15-18. Next List Descriptor Address Registers (NLSDARn)
            • Table15-17. NLSDARn Field Descriptions
          • 15.3.2.12 Source Stride Registers (SSRn)
            • Figure15-19. Source Stride Registers (SSRn)
            • Table15-18. SSRn Field Descriptions
          • 15.3.2.13 Destination Stride Registers (DSRn)
            • Figure15-20. Destination Stride Registers (DSRn)
            • Table15-19. DSRn Field Descriptions
          • 15.3.2.14 DMA General Status Register (DGSR)
            • Figure15-21. DMA General Status Register (DGSR)
            • Table15-20. DGSR Field Descriptions
      • 15.4 Functional Description
        • 15.4.1 DMA Channel Operation
          • 15.4.1.1 Basic DMA Mode Transfer
            • 15.4.1.1.1 Basic Direct Mode
            • 15.4.1.1.2 Basic Direct Single-Write Start Mode
            • 15.4.1.1.3 Basic Chaining Mode
            • 15.4.1.1.4 Basic Chaining Single-Write Start Mode
          • 15.4.1.2 Extended DMA Mode Transfer
            • 15.4.1.2.1 Extended Direct Mode
            • 15.4.1.2.2 Extended Direct Single-Write Start Mode
            • 15.4.1.2.3 Extended Chaining Mode
            • 15.4.1.2.4 Extended Chaining Single-Write Start Mode
          • 15.4.1.3 External Control Mode Transfer
            • Figure15-22. External Control Interface Timing
          • 15.4.1.4 Channel Continue Mode for Cascading Transfer Chains
            • 15.4.1.4.1 Basic Mode
            • 15.4.1.4.2 Extended Mode
          • 15.4.1.5 Channel Abort
          • 15.4.1.6 Bandwidth Control
          • 15.4.1.7 Channel State
            • Table15-21. Channel State Table
          • 15.4.1.8 Illustration of Stride Size and Stride Distance
            • Figure15-23. Stride Size and Stride Distance
        • 15.4.2 DMA Transfer Interfaces
        • 15.4.3 DMA Errors
        • 15.4.4 DMA Descriptors
          • Table15-22. DMA List Descriptor Summary 
          • Table15-23. DMA List Descriptor Summary 
          • Figure15-24. DMA Transaction Flow with DMA Descriptors
          • Figure15-25. List Descriptor Format
          • Figure15-26. Link Descriptor Format
        • 15.4.5 Limitations and Restrictions
      • 15.5 DMA System Considerations
        • Figure15-27. DMA Data Paths
        • Table15-24. DMA Paths
        • 15.5.1 Unusual DMA Scenarios
          • 15.5.1.1 DMA to e500 Core
          • 15.5.1.2 DMA to Ethernet
          • 15.5.1.3 DMA to Configuration and Control Registers
          • 15.5.1.4 DMA to I2C
          • 15.5.1.5 DMA to DUART
    • Chapter16 PCI/PCI-X Bus Interface
      • 16.1 Introduction
        • Figure16-1. PCI/X Controller Block Diagram
        • 16.1.1 Overview
          • 16.1.1.1 MPC8540 as a PCI/X Initiator
          • 16.1.1.2 MPC8540 as a PCI/X Target
        • 16.1.2 Features
        • 16.1.3 Modes of Operation
          • Table16-1. POR Parameters for PCI/X Controller
          • 16.1.3.1 Host/Agent Modes
            • 16.1.3.1.1 Host Mode
            • 16.1.3.1.2 Agent Mode
            • 16.1.3.1.3 Agent Configuration Lock Mode
          • 16.1.3.2 PCI/X Bus Width (64-/32-Bit Bus)
          • 16.1.3.3 PCI/X Arbiter (Internal/External Arbiter)
          • 16.1.3.4 PCI/X Bus Mode
          • 16.1.3.5 PCI/X Signal Output Hold Timing
          • 16.1.3.6 PCI/X Impedance
      • 16.2 External Signal Descriptions
        • Figure16-2. PCI/X Interface External Signals
        • Table16-2. PCI Interface Signals�Detailed Signal Descriptions
      • 16.3 Memory Map/Register Definitions
        • 16.3.1 PCI/X Memory Mapped Registers
          • Table16-3. PCI/X Memory-Mapped Register Map
          • 16.3.1.1 PCI/X Configuration Access Registers
            • 16.3.1.1.1 PCI/X Configuration Address Register (CFG_ADDR)
              • Figure16-3. PCI/X CFG_ADDR Register
              • Table16-4. PCI/X CFG_ADDR Field Descriptions
            • 16.3.1.1.2 PCI/X Configuration Data Register (CFG_DATA)
              • Figure16-4. PCI/X CFG_DATA Register
              • Table16-5. PCI/X CFG_DATA Field Descriptions
            • 16.3.1.1.3 PCI/X Interrupt Acknowledge Register (INT_ACK)
              • Figure16-5. PCI/X INT_ACK Register
              • Table16-6. PCI/X INT_ACK Field Descriptions
          • 16.3.1.2 PCI/X ATMU Outbound Registers
            • 16.3.1.2.1 PCI/X Outbound Translation Address Registers (POTARn)
              • Figure16-6. PCI/X Outbound Translation Address Registers
              • Table16-7. POTARn Field Descriptions
            • 16.3.1.2.2 PCI/X Outbound Translation Extended Address Registers (POTEARn)
              • Figure16-7. PCI/X Outbound Translation Extended Address Registers
              • Table16-8. POTEARn Field Descriptions
            • 16.3.1.2.3 PCI/X Outbound Window Base Address Registers (POWBARn)
              • Figure16-8. PCI/X Outbound Window Base Address Registers
              • Table16-9. POWBARn Field Descriptions
            • 16.3.1.2.4 PCI/X Outbound Window Attributes Registers (POWARn)
              • Figure16-9. PCI/X Outbound Window Attributes Register 0 (Default)
              • Figure16-10. PCI/X Outbound Window Attributes Registers 1�4
              • Table16-10. POWARn Field Descriptions
          • 16.3.1.3 PCI/X ATMU Inbound Registers
            • 16.3.1.3.1 PCI/X Inbound Translation Address Registers (PITARn)
              • Figure16-11. PCI/X Inbound Translation Address Registers
              • Table16-11. PITARn Field Descriptions
            • 16.3.1.3.2 PCI/X Inbound Window Base Address Registers (PIWBARn)
              • Figure16-12. PCI/X Inbound Window Base Address Registers
              • Table16-12. PIWBARn Field Descriptions
            • 16.3.1.3.3 PCI/X Inbound Window Base Extended Address Registers (PIWBEARn)
              • Figure16-13. PCI/X Inbound Window Base Extended Address Registers
              • Table16-13. PIWBEARn Field Descriptions
            • 16.3.1.3.4 PCI/X Inbound Window Attributes Registers (PIWARn)
              • Figure16-14. PCI/X Inbound Window Attributes Registers
              • Table16-14. PIWARn Field Descriptions
          • 16.3.1.4 PCI/X Error Management Registers
            • 16.3.1.4.1 PCI/X Error Detect Register (ERR_DR)
              • Figure16-15. PCI/X Error Detect Register (ERR_DR)
              • Table16-15. ERR_DR Field Descriptions
            • 16.3.1.4.2 PCI/X Error Capture Disable Register (ERR_CAP_DR)
              • Figure16-16. PCI/X Error Capture Disable Register (ERR_CAP_DR)
              • Table16-16. ERR_CAP_DR Field Descriptions
            • 16.3.1.4.3 PCI/X Error Enable Register (ERR_EN)
              • Figure16-17. PCI/X Error Enable Register (ERR_EN)
              • Table16-17. ERR_EN Field Descriptions
            • 16.3.1.4.4 PCI/X Error Attributes Capture Register (ERR_ATTRIB)
              • Figure16-18. PCI/X Error Attributes Capture Register (ERR_ATTRIB)
              • Table16-18. ERR_ATTRIB Field Descriptions
            • 16.3.1.4.5 PCI/X Error Address Capture Register (ERR_ADDR)
              • Figure16-19. PCI/X Error Address Capture Register (ERR_ADDR)
              • Table16-19. ERR_ADDR Field Descriptions
            • 16.3.1.4.6 PCI/X Error Extended Address Capture Register (ERR_EXT_ADDR)
              • Figure16-20. PCI/X Error Extended Address Capture Register (ERR_EXT_ADDR)
              • Table16-20. ERR_EXT_ADDR Field Descriptions
            • 16.3.1.4.7 PCI/X Error Data Low Capture Register (ERR_DL)
              • Figure16-21. PCI/X Error Data Low Capture Register (ERR_DL)
              • Table16-21. ERR_DL Field Description
            • 16.3.1.4.8 PCI/X Error Data High Capture Register (ERR_DH)
              • Figure16-22. PCI/X Error Data High Capture Register (ERR_DH)
              • Table16-22. ERR_DH Field Description
            • 16.3.1.4.9 PCI/X Gasket Timer Register (GAS_TIMR)
              • Figure16-23. PCI/X Gasket Timer Register (GAS_TIMR)
              • Table16-23. GAS_TIMR Field Descriptions
            • 16.3.1.4.10 PCI-X Split Completion Timer Register (PCIX_TIMR)
              • Figure16-24. PCI-X Split Completion Timer Register (PCIX_TIMR)
              • Table16-24. PCIX_TIMR Field Descriptions
        • 16.3.2 PCI/X Configuration Header
          • Figure16-25. MPC8540 PCI/X Configuration Header
          • Figure16-26. PCI-X Additional Configuration Registers
          • 16.3.2.1 PCI Vendor ID Register�Offset 0x00
            • Figure16-27. PCI Vendor ID Register
            • Table16-25. PCI Vendor ID Register Field Description
          • 16.3.2.2 PCI Device ID Register�Offset 0x02
            • Figure16-28. PCI Device ID Register
            • Table16-26. PCI Device ID Register Field Description
          • 16.3.2.3 PCI Bus Command Register�Offset 0x04
            • Figure16-29. PCI Bus Command Register
            • Table16-27. PCI Bus Command Register Field Descriptions
          • 16.3.2.4 PCI Bus Status Register�Offset 0x06
            • Figure16-30. PCI Bus Status Register
            • Table16-28. PCI Bus Status Register Field Descriptions
          • 16.3.2.5 PCI Revision ID Register�Offset 0x08
            • Figure16-31. PCI Revision ID Register
            • Table16-29. PCI Revision ID Register Field Descriptions
          • 16.3.2.6 PCI Bus Programming Interface Register�Offset 0x09
            • Figure16-32. PCI Bus Programming Interface Register
            • Table16-30. PCI Bus Programming Interface Register Field Description
          • 16.3.2.7 PCI Subclass Code Register�Offset 0x0A
            • Figure16-33. PCI Subclass Code Register
            • Table16-31. PCI Subclass Code Register Field Description
          • 16.3.2.8 PCI Bus Base Class Code Register�Offset 0x0B
            • Figure16-34. PCI Bus Base Class Code Register
            • Table16-32. PCI Bus Base Class Code Register Field Description
          • 16.3.2.9 PCI Bus Cache Line Size Register�Offset 0x0C
            • Figure16-35. PCI Bus Cache Line Size Register (PCLSR)
            • Table16-33. PCI Bus Cache Line Size Register (PCLSR) Field Descriptions
          • 16.3.2.10 PCI Bus Latency Timer Register�0x0D
            • Figure16-36. PCI Bus Latency Timer Register
            • Table16-34. PCI Bus Latency Timer Register Field Descriptions
          • 16.3.2.11 PCI Base Address Registers
            • Figure16-37. PCI Configuration and Status Register Base Address Register (PCSRBAR)
            • Table16-35. PCSRBAR Field Descriptions
            • Figure16-38. 32�Bit Memory Base Address Register
            • Table16-36. 32-Bit Memory Base Address Register Field Descriptions
            • Figure16-39. 64-Bit Low Memory Base Address Register
            • Table16-37. 64-Bit Low Memory Base Address Register Field Descriptions
            • Figure16-40. 64-Bit High Memory Base Address Register
            • Table16-38. 64-Bit High Memory Base Address Register Field Description
          • 16.3.2.12 PCI Subsystem Vendor ID Register
            • Figure16-41. PCI Subsystem Vendor ID Register
            • Table16-39. PCI Subsystem Vendor ID Register Field Description
          • 16.3.2.13 PCI Subsystem ID Register
            • Figure16-42. PCI Subsystem ID Register
            • Table16-40. PCI Subsystem ID Register Field Description
          • 16.3.2.14 PCI Bus Capabilities Pointer Register
            • Figure16-43. PCI Bus Capabilities Pointer Register
            • Table16-41. PCI Bus Capabilities Pointer Register Field Description
          • 16.3.2.15 PCI Bus Interrupt Line Register
            • Figure16-44. PCI Bus Interrupt Line Register
            • Table16-42. PCI Bus Interrupt Line Register Field Description
          • 16.3.2.16 PCI Bus Interrupt Pin Register
            • Figure16-45. PCI Bus Interrupt Pin Register
            • Table16-43. PCI Bus Interrupt Pin Register Field Description
          • 16.3.2.17 PCI Bus Minimum Grant (MIN_GNT) Register
            • Figure16-46. PCI Bus Minimum Grant Register
            • Table16-44. PCI Bus Minimum Grant Register Field Description
          • 16.3.2.18 PCI Bus Maximum Latency (MAX_LAT) Register
            • Figure16-47. PCI Bus Maximum Latency Register
            • Table16-45. PCI Bus Maximum Latency Register Field Description
          • 16.3.2.19 PCI Bus Function Register (PBFR)
            • Figure16-48. PCI Bus Function Register
            • Table16-46. PCI Bus Function Register Field Descriptions
          • 16.3.2.20 PCI Bus Arbiter Configuration Register (PBACR)
            • Figure16-49. PCI Bus Arbiter Configuration Register
            • Table16-47. PCI Bus Arbiter Configuration Register Field Descriptions
          • 16.3.2.21 PCI-X Next Capabilities ID Register�0x60
            • Figure16-50. PCI-X Next Capabilities ID Register
            • Table16-48. PCI-X Next Capabilities ID Register Field Descriptions
          • 16.3.2.22 PCI-X Capability Pointer Register�0x61
            • Figure16-51. PCI-X Capability Pointer Register
            • Table16-49. PCI-X Capability Pointer Register Field Description
          • 16.3.2.23 PCI-X Command Register�0x62
            • Figure16-52. PCI-X Command Register
            • Table16-50. PCI-X Command Register Field Descriptions
          • 16.3.2.24 PCI-X Status Register�0x64
            • Figure16-53. PCI-X Status Register
            • Table16-51. PCI-X Status Register Field Descriptions
      • 16.4 Functional Description
        • 16.4.1 PCI/X Bus Arbitration
          • 16.4.1.1 PCI/X Bus Arbiter Operation
            • Figure16-54. PCI/X Arbitration Example
          • 16.4.1.2 PCI/X Bus Parking
          • 16.4.1.3 Broken Master Lock-Out (PCI only)
          • 16.4.1.4 Power-Saving Modes and the PCI Arbiter
        • 16.4.2 PCI Bus Protocol
          • 16.4.2.1 Basic Transfer Control
          • 16.4.2.2 PCI Bus Commands
            • Table16-52. PCI Bus Commands
          • 16.4.2.3 Addressing
            • 16.4.2.3.1 Memory Space Addressing
              • Table16-53. Supported Combinations of PCI_AD[1:0]
            • 16.4.2.3.2 I/O Space Addressing
            • 16.4.2.3.3 Configuration Space Addressing
          • 16.4.2.4 Device Selection
          • 16.4.2.5 Byte Alignment
          • 16.4.2.6 Bus Driving and Turnaround
          • 16.4.2.7 PCI Bus Transactions
            • 16.4.2.7.1 PCI Read Transactions
              • Figure16-55. PCI Single-Beat Read Transaction
              • Figure16-56. PCI Burst Read Transaction
            • 16.4.2.7.2 PCI Write Transactions
              • Figure16-57. PCI Single-Beat Write Transaction
              • Figure16-58. PCI Burst Write Transaction
          • 16.4.2.8 Transaction Termination
            • 16.4.2.8.1 Master-Initiated Termination
            • 16.4.2.8.2 Target-Initiated Termination
              • Figure16-59. PCI Target-Initiated Terminations
          • 16.4.2.9 Fast Back-to-Back Transactions
          • 16.4.2.10 Dual Address Cycles
            • Figure16-60. DAC Single-Beat Read Example
            • Figure16-61. DAC Burst Read Example
            • Figure16-62. DAC Single-Beat Write Example
            • Figure16-63. DAC Burst Write Example
            • Figure16-64. 64-Bit Dual Address Read Cycle
          • 16.4.2.11 Configuration Cycles
            • 16.4.2.11.1 PCI Configuration Space Header
              • Figure16-65. Standard PCI Configuration Header
              • Table16-54. PCI Configuration Space Header Summary
            • 16.4.2.11.2 Accessing the PCI Configuration Space in Host Mode
            • 16.4.2.11.3 PCI Configuration in Agent and Agent Lock Modes
            • 16.4.2.11.4 PCI Type 0 Configuration Translation
              • Figure16-66. PCI Type 0 Configuration Translation
              • Table16-55. PCI Type 0 Configuration�Device Number to ADn Translation
            • 16.4.2.11.5 Type 1 Configuration Translation
          • 16.4.2.12 Other Bus Transactions
            • 16.4.2.12.1 Interrupt-Acknowledge Transactions
            • 16.4.2.12.2 Special-Cycle Transactions
              • Table16-56. Special-Cycle Message Encodings
          • 16.4.2.13 PCI Error Functions
            • 16.4.2.13.1 PCI Parity
              • Figure16-67. PCI Parity Operation
            • 16.4.2.13.2 Error Reporting
              • Table16-57. PCI Mode Error Actions
        • 16.4.3 PCI-X Bus Protocol
          • 16.4.3.1 PCI-X Terminology
          • 16.4.3.2 PCI-X Command Encodings
            • Table16-58. PCI-X Command Encodings
          • 16.4.3.3 PCI-X Attribute Phase
            • Figure16-68. AD[31:0] During PCI-X Burst/DWORD Attribute Phase
            • Table16-59. Burst/DWORD Transaction Attribute Summary 
          • 16.4.3.4 PCI-X Transactions
            • Figure16-69. Typical PCI-X Write Transaction
            • Figure16-70. Burst Memory Write Transaction
            • Figure16-71. Memory Read Block Transaction
            • Figure16-72. DWORD (4-Byte) Write Transaction
            • Figure16-73. DWORD (4-Byte) Read Transaction
          • 16.4.3.5 PCI-X Wait State and Termination Rules
          • 16.4.3.6 PCI-X Split Transactions
            • 16.4.3.6.1 Split Response
              • Figure16-74. Split Response to a Read Transaction
              • Figure16-75. Split Response to a DWORD (4-Byte) Write Transaction
            • 16.4.3.6.2 Completion Address
              • Figure16-76. Split Completion Transaction Address AD[31:0]
              • Table16-60. Split Completion Transaction Address
            • 16.4.3.6.3 Completer Attributes
              • Figure16-77. AD[31:0] During PCI-X Split Completion Attribute Phase
              • Table16-61. PCI-X Split Completion Transaction Attribute Summary 
            • 16.4.3.6.4 Split Completion Messages
              • Figure16-78. PCI-X Split Completion Message Format
              • Table16-62. PCI-X Split Completion Message Summary 
          • 16.4.3.7 PCI-X Configuration Transactions
            • Figure16-79. PCI-X Type 0 Configuration Translation
            • Table16-63. PCI-X Type 0 Configuration�Device Number to ADn Translation
            • Figure16-80. AD[31:0] During PCI-X Configuration Attribute Phase
            • Table16-64. PCI-X Configuration Transaction Attribute Summary 
          • 16.4.3.8 PCI-X Error Functions
            • 16.4.3.8.1 Error Reporting
              • Table16-65. PCI-X Mode Error Actions
      • 16.5 Initialization/Application Information
        • 16.5.1 Power-On Reset Configuration Modes
          • Table16-66. Affected Configuration Register Bits for POR
          • Table16-67. Power-On Reset Values for Affected Configuration Bits
          • 16.5.1.1 Host Mode
          • 16.5.1.2 Agent Mode
          • 16.5.1.3 Agent Configuration Lock Mode
        • 16.5.2 Nonposted Writes in PCI-X
        • 16.5.3 PCI-X Outbound Read Transaction Alignment
        • 16.5.4 PCI-X Inbound Reads that Cross Window Boundaries
        • 16.5.5 Bridging Between RapidIO and PCI/X
    • Chapter17 RapidIO Interface
      • 17.1 Introduction
        • 17.1.1 Overview
          • Figure17-1. RapidIO High Level Block Diagram
        • 17.1.2 RapidIO Terminology
          • Table17-1. RapidIO Terminology
        • 17.1.3 RapidIO Interface Features
          • 17.1.3.1 Supported Features
          • 17.1.3.2 Features Not Implemented
        • 17.1.4 RapidIO Modes of Operation
          • 17.1.4.1 Transmit Clock-Select Mode
          • 17.1.4.2 CRC Checking Modes
            • Table17-2. CRC Checking Mode
          • 17.1.4.3 Error Checking Disable Mode
          • 17.1.4.4 Output Port Enable Mode
          • 17.1.4.5 Output Port Driver Disable Mode
          • 17.1.4.6 Accept All Mode
            • Table17-3. Accept All Mode Behavior
          • 17.1.4.7 Packet Response Time-Out Disable Mode
          • 17.1.4.8 Link Response Time-Out Disable Mode
      • 17.2 External Signal Descriptions
        • 17.2.1 Signals Overview
          • Figure17-2. RapidIO Interface Signals Model
          • Table17-4. RapidIO Interface Signals Summary
        • 17.2.2 Detailed Signal Descriptions
          • Table17-5. RapidIO Interface Signals�Detailed Signal Descriptions
      • 17.3 Memory Map/Register Definition
        • Table17-6. RapidIO Module Memory Map
        • 17.3.1 Architectural Registers
          • 17.3.1.1 Device Identity Capability Register (DIDCAR)
            • Figure17-3. Device Identity Capability Register (DIDCAR)
            • Table17-7. DIDCAR Field Descriptions 
          • 17.3.1.2 Device Information Capability Register (DICAR)
            • Figure17-4. Device Information Capability Register (DICAR)
            • Table17-8. DICAR Field Description
          • 17.3.1.3 Assembly Identity Capability Register (AIDCAR)
            • Figure17-5. Assembly Identity Capability Register (AIDCAR)
            • Table17-9. AIDCAR Field Descriptions
          • 17.3.1.4 Assembly Information Capability Register (AICAR)
            • Figure17-6. Assembly Information Capability Register (AICAR)
            • Table17-10. AICAR Field Descriptions
          • 17.3.1.5 Processing Element Features Capability Register (PEFCAR)
            • Figure17-7. Processing Element Features Capability Register (PEFCAR)
            • Table17-11. PEFCAR Field Descriptions
          • 17.3.1.6 Switch Port Information Capability Register (SPICAR)
            • Figure17-8. Switch Port Information Capability Register (SPICAR)
            • Table17-12. SPICAR Field Descriptions 
          • 17.3.1.7 Source Operations Capability Register (SOCAR)
            • Figure17-9. Source Operations Capability Register (SOCAR)
            • Table17-13. SOCAR Field Descriptions
          • 17.3.1.8 Destination Operations Capability Register (DOCAR)
            • Figure17-10. Destination Operations Capability Register (DOCAR)
            • Table17-14. DOCAR Field Descriptions
          • 17.3.1.9 Mailbox Command and Status Register (MSR)
            • Figure17-11. Mailbox Status Register (MSR)
            • Table17-15. MSR Field Definitions
          • 17.3.1.10 Port-Write and Doorbell Command and Status Register (PWDCSR)
            • Figure17-12. Port-Write and Doorbell Command and Status Register (PWDCSR)
            • Table17-16. PWDCSR Field Descriptions
          • 17.3.1.11 Processing Element Logic Layer Control Command and Status Register(PELLCCSR)
            • Figure17-13. Processing Element Logic Layer Control Command and Status Register (PELLCCSR)
            • Table17-17. PELLCCSR Field Descriptions
          • 17.3.1.12 Local Configuration Space Base Address 1 Command and Status Register(LCSBA1CSR)
            • Figure17-14. Local Configuration Space Base Address 1 Command and Status Register (LCSBA1CSR)
            • Table17-18. LCSBA1CSR Field Descriptions
          • 17.3.1.13 Base Device ID Command and Status Register (BDIDCSR)
            • Figure17-15. Base Device ID Command and Status Register (BDIDCSR)
            • Table17-19. BDIDCSR Field Descriptions
          • 17.3.1.14 Host Base Device ID Lock Command and Status Register (HBDIDLCSR)
            • Figure17-16. Host Base Device ID Lock Command and Status Register (HBDIDLCSR)
            • Table17-20. HBDIDLCSR Field Descriptions
          • 17.3.1.15 Component Tag Command and Status Register (CTCSR)
            • Figure17-17. Component Tag Command and Status Register (CTCSR)
            • Table17-21. CTCSR Field Descriptions
          • 17.3.1.16 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register (PMBH0CSR)
            • Figure17-18. 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register(PMBH0CSR)
            • Table17-22. PMBH0CSR Field Descriptions
          • 17.3.1.17 Port Link Time-Out Control Command and Status Register (PLTOCCSR)
            • Figure17-19. Port Link Time-Out Control Command and Status Register (PLTOCCSR)
            • Table17-23. PLTOCCSR Field Descriptions
          • 17.3.1.18 Port Response Time-Out Control Command and Status Register (PRTOCCSR)
            • Figure17-20. Port Response Time-Out Control Command and Status Register (PRTOCCSR)
            • Table17-24. PRTOCCSR Field Descriptions
          • 17.3.1.19 Port General Control Command and Status Register (PGCCSR)
            • Figure17-21. Port General Control Command and Status Register (PGCCSR)
            • Table17-25. PGCCSR Field Descriptions
          • 17.3.1.20 Port Link Maintenance Request Command and Status Register (PLMREQCSR)
            • Figure17-22. Port Link Maintenance Request Command and Status Register (PLMREQCSR)
            • Table17-26. PLMREQCSR Field Descriptions
          • 17.3.1.21 Port Link Maintenance Response Command and Status Register (PLMRESPCSR)
            • Figure17-23. Port Link Maintenance Response Command and Status Register (PLMRESPCSR)
            • Table17-27. PLMRESPCSR Field Descriptions
          • 17.3.1.22 Port Local AckID Status Command and Status Register (PLASCSR)
            • Figure17-24. Port Local AckID Status Command and Status Register (PLASCSR)
            • Table17-28. PLASCSR Field Descriptions
          • 17.3.1.23 Port Error and Status Command and Status Register (PESCSR)
            • Figure17-25. Port Error and Status Command and Status Register (PESCSR)
            • Table17-29. PESCSR Field Descriptions 
          • 17.3.1.24 Port Control Command and Status Register (PCCSR)
            • Figure17-26. Port Control Command and Status Register (PCCSR)
            • Table17-30. PCCSR Field Descriptions
        • 17.3.2 Implementation Registers
          • 17.3.2.1 General Registers
            • 17.3.2.1.1 Configuration Register (CR)
              • Figure17-27. Configuration Register (CR)
              • Table17-31. CR Field Descriptions
            • 17.3.2.1.2 Port Configuration Register (PCR)
              • Figure17-28. Port Configuration Register (PCR)
              • Table17-32. PCR Field Descriptions
            • 17.3.2.1.3 Port Error Injection Register (PEIR)
              • Figure17-29. Port Error Injection Register (PEIR)
              • Table17-33. PEIR Field Descriptions
          • 17.3.2.2 ATMU Registers
            • 17.3.2.2.1 RapidIO Outbound Window Translation Address Registers 0�8 (ROWTARn)
              • Figure17-30. RapidIO Outbound Window Translation Address Registers 0�8 for Standard Transactions...
              • Table17-34. ROWTARn Standard Field Descriptions
              • Figure17-31. RapidIO Outbound Window Translation Address Registers 0�8 for Maintenance Transacti...
              • Table17-35. ROWTARn Maintenance Field Descriptions
            • 17.3.2.2.2 RapidIO Outbound Window Base Address Registers1�8 (ROWBARn)
              • Figure17-32. RapidIO Outbound Window Base Address Registers1�8 (ROWBARn)
              • Table17-36. ROWBARn Field Descriptions
            • 17.3.2.2.3 RapidIO Outbound Window Attributes Registers 0�8 (ROWARn)
              • Figure17-33. RapidIO Outbound Window Attributes Register0 (ROWAR0)
              • Figure17-34. RapidIO Outbound Window Attributes Registers 1�8 (ROWARn)
              • Table17-37. ROWARn Field Descriptions
            • 17.3.2.2.4 RapidIO Inbound Window Translation Address Registers0�4 (RIWTARn)
              • Figure17-35. RapidIO Inbound Window Translation Address Registers 0�4 (RIWTARn)
              • Table17-38. RIWTARn Field Descriptions
            • 17.3.2.2.5 RapidIO Inbound Window Base Address Registers1�4 (RIWBARn)
              • Figure17-36. RapidIO Inbound Window Base Address Registers 1�4 (RIWBARn)
              • Table17-39. RIWBARn Field Descriptions
            • 17.3.2.2.6 RapidIO Inbound Window Attributes Registers 0�4 (RIWARn)
              • Figure17-37. RapidIO Inbound Window Attributes Register0 (RIWAR0)
              • Figure17-38. RapidIO Inbound Window Attributes Registers 1�4 (RIWARn)
              • Table17-40. RIWARn Field Descriptions
          • 17.3.2.3 Error Management Registers
            • 17.3.2.3.1 Port Notification/Fatal Error Detect Register (PNFEDR)
              • Figure17-39. Port Notification/Fatal Error Detect Register (PNFEDR)
              • Table17-41. PNFEDR Field Descriptions
            • 17.3.2.3.2 Port Notification/Fatal Error Detect Disable Register (PNFEDiR)
              • Figure17-40. Port Notification/Fatal Error Detect Disable Register (PNFEDiR)
              • Table17-42. PNFEDiR Field Descriptions 
            • 17.3.2.3.3 Port Notification/Fatal Error Interrupt Enable Register (PNFEIER)
              • Figure17-41. Port Notification/Fatal Error Interrupt Enable Register (PNFEIER)
              • Table17-43. PNFEIER Field Descriptions 
            • 17.3.2.3.4 Port Error Capture Status Register (PECSR)
              • Figure17-42. Port Error Capture Status Register (PECSR)
              • Table17-44. PECSR Field Descriptions
            • 17.3.2.3.5 Error Packet Capture Register0 (EPCR0)
              • Figure17-43. Error Packet Capture Register0 (EPCR0)
              • Table17-45. EPCR0 Field Descriptions
            • 17.3.2.3.6 Error Packet Capture Register1 (EPCR1)
            • 17.3.2.3.7 EPCR1�Type1 Packet Format
              • Figure17-44. Error Packet Capture Register1 (EPCR1)�Type 1 Packet Format
              • Table17-46. EPCR1 Type 1 Field Descriptions
            • 17.3.2.3.8 EPCR1�Type 2 Packet Format
              • Figure17-45. Error Packet Capture Register1 (EPCR1)�Type 2 Packet Format
              • Table17-47. EPCR1 Type 2 Field Descriptions
            • 17.3.2.3.9 EPCR1�Type 5 Packet Format
              • Figure17-46. Error Packet Capture Register1 (EPCR1)�Type 5 Packet Format
              • Table17-48. EPCR1 Type 5 Field Descriptions
            • 17.3.2.3.10 EPCR1�Type 6 Packet Format
              • Figure17-47. Error Packet Capture Register1 (EPCR1)�Type 6 Packet Format
              • Table17-49. EPCR1 Type 6 Field Descriptions
            • 17.3.2.3.11 EPCR1�Type 8 Request Packet Format
              • Figure17-48. Error Packet Capture Register1 (EPCR1)�Type 8 Request Packet Format
              • Table17-50. EPCR1 Type 8 Request Field Descriptions
            • 17.3.2.3.12 EPCR1�Type 8 Response Packet Format
              • Figure17-49. Error Packet Capture Register1 (EPCR1)�Type 8 Response Packet Format
              • Table17-51. EPCR1 Type 8 Response Field Descriptions
            • 17.3.2.3.13 EPCR1�Type 10 Packet Format
              • Figure17-50. Error Packet Capture Register1 (EPCR1)�Type 10 Packet Format
              • Table17-52. EPCR1 Type 10 Field Descriptions 
            • 17.3.2.3.14 EPCR1�Type 11 Packet Format
              • Figure17-51. Error Packet Capture Register1 (EPCR1)�Type 11 Packet Format
              • Table17-53. EPCR1 Type 11 Field Descriptions
            • 17.3.2.3.15 EPCR1�Type 13 Packet Format
              • Figure17-52. Error Packet Capture Register1 (EPCR1)�Type 13 Packet Format
              • Table17-54. EPCR1 Type 13 Field Descriptions
            • 17.3.2.3.16 Error Packet Capture Register2 (EPCR2)
            • 17.3.2.3.17 EPCR2�Type 1, 2, or 5 Packet Format
              • Figure17-53. Error Packet Capture Register2 (EPCR2)�Type 1, 2, or 5 Packet Format
              • Table17-55. EPCR2 Type 1, 2, or 5 Field Descriptions
            • 17.3.2.3.18 EPCR2�Type 6 Packet Format
              • Figure17-54. Error Packet Capture Register2 (EPCR2)�Type 6 Packet Format
              • Table17-56. EPCR2 Type 6 Field Descriptions
            • 17.3.2.3.19 EPCR2�Type 8 Request Packet Format
              • Figure17-55. Error Packet Capture Register2 (EPCR2)�Type 8 Request Packet Format
              • Table17-57. EPCR2 Type 8 Request Field Descriptions 
            • 17.3.2.3.20 EPCR2�Type 8 Response Packet Format
              • Figure17-56. Error Packet Capture Register2 (EPCR2)�Type 8 Response Packet Format
              • Table17-58. EPCR2 Type 8 Response Field Descriptions
            • 17.3.2.3.21 EPCR2�Type 10 Packet Format
              • Figure17-57. Error Packet Capture Register2 (EPCR2)�Type 10 Packet Format
              • Table17-59. EPCR2 Type 10 Field Descriptions
            • 17.3.2.3.22 EPCR2�Type 11 or 13 Packet Format
              • Figure17-58. Error Packet Capture Register2 (EPCR2)�Type 11 or 13 Packet Format
              • Table17-60. EPCR2 Type 11 or 13 Field Description
            • 17.3.2.3.23 Port Recoverable Error Detect Register (PREDR)
              • Figure17-59. Port Recoverable Error Detect Register (PREDR)
              • Table17-61. PREDR Field Descriptions
            • 17.3.2.3.24 Port Error Recovery Threshold Register (PERTR)
              • Figure17-60. Port Error Recovery Threshold Register (PERTR)
              • Table17-62. PERTR Field Descriptions
            • 17.3.2.3.25 Port Retry Threshold Register (PRTR)
              • Figure17-61. Port Retry Threshold Register (PRTR)
              • Table17-63. PRTR Field Descriptions
        • 17.3.3 RapidIO Message Unit Registers
          • 17.3.3.1 RapidIO Outbound Message Registers
            • 17.3.3.1.1 Outbound Mode Register (OMR)
              • Figure17-62. Outbound Mode Register (OMR)
              • Table17-64. OMR Field Descriptions
            • 17.3.3.1.2 Outbound Status Register (OSR)
              • Figure17-63. Outbound Status Register (OSR)
              • Table17-65. OSR Field Descriptions 
            • 17.3.3.1.3 Outbound Descriptor Queue Dequeue Pointer Address Register (ODQDPAR)
              • Figure17-64. Outbound Descriptor Queue Dequeue Pointer Address Register (ODQDPAR)
              • Table17-66. ODQDPAR Field Descriptions
            • 17.3.3.1.4 Outbound Unit Source Address Register (OSAR)
              • Figure17-65. Outbound Unit Source Address Registers (OSAR)
              • Table17-67. OSAR Field Descriptions
            • 17.3.3.1.5 Outbound Destination Port Register (ODPR)
              • Figure17-66. Outbound Destination Port Registers (ODPR)
              • Table17-68. ODPR Field Descriptions
            • 17.3.3.1.6 Outbound Destination Attributes Register (ODATR)
              • Figure17-67. Outbound Destination Attributes Register (ODATR)
              • Table17-69. ODATR Field Descriptions 
            • 17.3.3.1.7 Outbound Double-Word Count Register (ODCR)
              • Figure17-68. Outbound Double-Word Count Register (ODCR)
              • Table17-70. ODCR Field Descriptions
            • 17.3.3.1.8 Outbound Descriptor Queue Enqueue Pointer Address Register (ODQEPAR)
              • Figure17-69. Outbound Descriptor Queue Enqueue Pointer Register (ODQEPAR)
              • Table17-71. ODQEPAR Field Descriptions
          • 17.3.3.2 RapidIO Inbound Message Registers
            • 17.3.3.2.1 Inbound Mode Register (IMR)
              • Figure17-70. Inbound Mode Register (IMR)
              • Table17-72. IMR Field Descriptions 
            • 17.3.3.2.2 Inbound Status Register (ISR)
              • Figure17-71. Inbound Status Register (ISR)
              • Table17-73. ISR Field Descriptions 
            • 17.3.3.2.3 Inbound Frame Queue Dequeue Pointer Address Register (IFQDPAR)
              • Figure17-72. Inbound Frame Queue Dequeue Pointer Address Registers (IFQDPAR)
              • Table17-74. IFQDPAR Field Descriptions 
            • 17.3.3.2.4 Inbound Frame Queue Enqueue Pointer Address Register (IFQEPAR)
              • Figure17-73. Inbound Frame Queue Enqueue Pointer Address Registers (IFQEPAR)
              • Table17-75. IFQEPAR Field Descriptions 
          • 17.3.3.3 RapidIO Doorbell Registers
            • 17.3.3.3.1 Doorbell Mode Register (DMR)
              • Figure17-74. Doorbell Mode Register (DMR)
              • Table17-76. DMR Field Descriptions
            • 17.3.3.3.2 Doorbell Status Register (DSR)
              • Figure17-75. Doorbell Status Register (DSR)
              • Table17-77. DSR Field Descriptions
            • 17.3.3.3.3 Doorbell Queue/Dequeue Pointer Address Register (DQDPAR)
              • Figure17-76. Doorbell Queue Dequeue Pointer Address Registers (DQDPAR)
              • Table17-78. DQDPAR Field Descriptions 
            • 17.3.3.3.4 Doorbell Queue Enqueue Pointer Address Register (DQEPAR)
              • Figure17-77. Doorbell Queue Enqueue Pointer Address Register (DQEPAR)
              • Table17-79. DQEPAR Field Descriptions 
          • 17.3.3.4 RapidIO Port-Write Registers
            • 17.3.3.4.1 Port-Write Mode Register (PWMR)
              • Figure17-78. Port-Write Mode Register (PWMR)
              • Table17-80. PWMR Field Descriptions 
            • 17.3.3.4.2 Port-Write Status Register (PWSR)
              • Figure17-79. Port-Write Status Register (PWSR)
              • Table17-81. PWSR Field Descriptions 
            • 17.3.3.4.3 Port-Write Queue Base Address Register (PWQBAR)
              • Figure17-80. Port-Write Queue Base Address Register (PWQBAR)
              • Table17-82. PWQBAR Field Descriptions 
      • 17.4 Functional Description
        • 17.4.1 RapidIO Transaction, Packet, and Control Symbol Summary
          • Table17-83. RapidIO Transaction Summary
          • Figure17-81. Physical Maintenance Field (PMF) Definition
          • Table17-84. RapidIO Packet Format Summary (TT=0b00)
          • Table17-85. Control Symbol Formats
      • 17.5 RapidIO Functionality
        • 17.5.1 General Functionality Lists
          • Table17-86. General Device Functionality List
          • 17.5.1.1 8/16 LP-LVDS Layer Functionality Lists
            • Table17-87. General Device 8/16 LP-LVDS Physical Layer Basic Functionality List
            • Table17-88. General Device 8/16 LP-LVDS Physical Layer Link Maintenance List 
            • Table17-89. General Device 8/16 LP-LVDS Physical Layer Packet Transmission List
            • Table17-90. General Device 8/16 LP-LVDS Physical Layer Packet Reception List
            • Table17-91. General Device 8/16 LP-LVDS Physical Layer Recoverable Errors List
            • Table17-92. General Device 8/16 LP-LVDS Physical Layer Nonrecoverable Errors List
        • 17.5.2 Common Transport Layer Functionality Lists
          • Table17-93. General Device Common Transport Layer Basic Functionality List
          • Table17-94. General Device Common Transport Layer Packet Transmission List 
          • Table17-95. General Device Common Transport Layer Packet Reception List
          • Table17-96. General Device Common Transport Layer Detectable Errors List
        • 17.5.3 Logical Layer Functionality Lists
          • Table17-97. General Device Logical Layer Basic Functionality List
          • Table17-98. General Device Logical Layer Target Transaction Support List
          • 17.5.3.1 Logical Layer Source Transaction Support List
            • Table17-99. General Device Logical Layer Detectable Errors List
          • 17.5.3.2 Logical Layer Extended Functionality
      • 17.6 RapidIO Errors
        • Table17-100. Recoverable Errors Detected by RapidIO Controller
        • Table17-101. Notification Errors Detected by RapidIO Controller
        • Table17-102. Fatal Errors Detected by RapidIO Controller
      • 17.7 ATMU (Address Translation and Mapping Unit)
        • 17.7.1 Outbound ATMU Translation
          • 17.7.1.1 Outbound ATMU Bypass Mode
          • 17.7.1.2 Outbound Special Transactions and Requirements
        • 17.7.2 Inbound ATMU Translation
          • 17.7.2.1 Inbound ATMU LCSBA1CSR Window
          • 17.7.2.2 Inbound ATMU Bypass Mode
          • 17.7.2.3 Inbound Special Transactions and Requirements
          • 17.7.2.4 ATMU Boundary Crossing Errors
      • 17.8 RapidIO Message Unit
        • 17.8.1 Overview
        • 17.8.2 Message Unit Features
        • 17.8.3 Message Unit Modes of Operation
        • 17.8.4 RapidIO Messaging Description
          • 17.8.4.1 Data Message Controller
          • 17.8.4.2 Outbox Controller Operation
            • 17.8.4.2.1 Direct Mode Operation
            • 17.8.4.2.2 Chaining Mode Operation
              • Figure17-82. Outbound Message Queue Structure
            • 17.8.4.2.3 Switching Between Direct and Chaining Modes
            • 17.8.4.2.4 Descriptor Format
              • Table17-103. Outbound Message Unit Descriptor Summary
              • Figure17-83. Descriptor Dequeue Pointer and Descriptor
            • 17.8.4.2.5 Outbox Controller Interrupts
            • 17.8.4.2.6 Special Error Case Condition
          • 17.8.4.3 Inbox Controller Operation
            • Figure17-84. Inbound Mailbox Structure
            • 17.8.4.3.1 Retry Response Conditions
            • 17.8.4.3.2 Error Response Conditions
            • 17.8.4.3.3 Inbox Controller Interrupts
            • 17.8.4.3.4 Data Message Controller Limitations and Restrictions
          • 17.8.4.4 Doorbell Message Controller
            • Figure17-85. Inbound Doorbell Queue and Pointer Structure
            • 17.8.4.4.1 Inbound Doorbell Reception
            • 17.8.4.4.2 Doorbell Queue Entry Format
              • Table17-104. Target Information Definition
              • Table17-105. Source Information Definition
              • Figure17-86. Doorbell Entry Format
            • 17.8.4.4.3 Retry Response Conditions
            • 17.8.4.4.4 Error Response Conditions
            • 17.8.4.4.5 Doorbell Controller Interrupts
          • 17.8.4.5 Port-Write Controller Structure
            • Figure17-87. Inbound Port-Write Structure
      • 17.9 Initialization and Application Information
  • PartIV Global Functions and Debug
    • Chapter18 Global Utilities
      • 18.1 Overview
      • 18.2 Global Utilities Features
        • 18.2.1 Power Management and Block Disables
        • 18.2.2 Accessing Current POR Configuration Settings
        • 18.2.3 General-Purpose I/O
        • 18.2.4 Interrupt and Local Bus Signal Multiplexing
        • 18.2.5 Clock Control
      • 18.3 External Signal Descriptions
        • 18.3.1 Signals Overview
          • Table18-1. External Signal Summary
        • 18.3.2 Detailed Signal Descriptions
          • Table18-2. Detailed Signal Descriptions
      • 18.4 Memory Map/Register Definition
        • Table18-3. Global Utilities Block Register Summary
        • 18.4.1 Register Descriptions
          • 18.4.1.1 POR PLL Status Register (PORPLLSR)
            • Figure18-1. POR PLL Status Register (PORPLLSR)
            • Table18-4. PORPLLSR Field Descriptions 
          • 18.4.1.2 POR Boot Mode Status Register (PORBMSR)
            • Figure18-2. POR Boot Mode Status Register (PORBMSR)
            • Table18-5. PORBMSR Field Descriptions
          • 18.4.1.3 POR I/O Impedance Status and Control Register (PORIMPSCR)
            • Figure18-3. POR I/O Impedance Status and Control Register (PORIMPSCR)
            • Table18-6. PORIMPSCR Field Descriptions 
          • 18.4.1.4 POR Device Status Register (PORDEVSR)
            • Figure18-4. POR Device Status Register (PORDEVSR)
            • Table18-7. PORDEVSR Field Descriptions 
          • 18.4.1.5 POR Debug Mode Status Register (PORDBGMSR)
            • Figure18-5. POR Debug Mode Status Register (PORDBGMSR)
            • Table18-8. PORDBGMSR Field Descriptions 
          • 18.4.1.6 General-Purpose POR Configuration Register (GPPORCR)
            • Figure18-6. POR Configuration Register (GPPORCR)
            • Table18-9. GPPORCR Field Descriptions 
          • 18.4.1.7 General-Purpose I/O Control Register (GPIOCR)
            • Figure18-7. General-Purpose I/O Control Register (GPIOCR)
            • Table18-10. GPIOCR Field Descriptions 
          • 18.4.1.8 General-Purpose Output Data Register (GPOUTDR)
            • Figure18-8. General-Purpose Output Data Register (GPOUTDR)
            • Table18-11. GPOUTDR Field Descriptions 
          • 18.4.1.9 General-Purpose Input Data Register (GPINDR)
            • Figure18-9. General-Purpose Output Data Register (GPINDR)
            • Table18-12. GPINDR Field Descriptions 
          • 18.4.1.10 Alternate Function Signal Multiplex Control Register (PMUXCR)
            • Figure18-10. Alternate Function Pin Multiplex Control Register (PMUXCR)
            • Table18-13. PMUXCR Field Descriptions 
          • 18.4.1.11 Device Disable Register (DEVDISR)
            • Figure18-11. Device Disable Register (DEVDISR)
            • Table18-14. DEVDISR Field Descriptions 
          • 18.4.1.12 Power Management Control and Status Register (POWMGTCSR)
            • Figure18-12. Power Management Control and Status Register (POWMGTCSR)
            • Table18-15. POWMGTCSR Field Descriptions 
          • 18.4.1.13 Machine Check Summary Register (MCPSUMR)
            • Figure18-13. Machine Check Summary Register (MCPSUMR)
            • Table18-16. MCPSUMR Field Descriptions 
          • 18.4.1.14 Processor Version Register (PVR)
            • Figure18-14. Processor Version Register (PVR)
            • Table18-17. PVR Field Descriptions 
          • 18.4.1.15 System Version Register (SVR)
            • Figure18-15. System Version Register (SVR)
            • Table18-18. SVR Field Descriptions 
          • 18.4.1.16 Clock Out Control Register (CLKOCR)
            • Figure18-16. Clock Out Control Register (CLKOCR)
            • Table18-19. CLKOCR Field Descriptions 
          • 18.4.1.17 DDR DLL Control Register (DDRDLLCR)
            • Figure18-17. DDR DLL Control Register (DDRDLLCR)
            • Table18-20. DDRDLLCR Field Descriptions 
          • 18.4.1.18 Local Bus DLL Control Register (LBDLLCR)
            • Figure18-18. Local Bus DLL Control Register (LBDLLCR)
            • Table18-21. LBDLLCR Field Descriptions 
      • 18.5 Functional Description
        • 18.5.1 Power Management
          • 18.5.1.1 Relationship Between Core and Device Power Management States
            • Figure18-19. e500 Core Power Management State Diagram
            • Table18-22. MPC8540 Power Management Modes�Basic Description 
          • 18.5.1.2 CKSTP_IN Is Not Power Management
          • 18.5.1.3 Dynamic Power Management
          • 18.5.1.4 Shutting Down Unused Blocks
          • 18.5.1.5 Software-Controlled Power-Down States
            • 18.5.1.5.1 Doze Mode
            • 18.5.1.5.2 Nap Mode
            • 18.5.1.5.3 Sleep Mode
          • 18.5.1.6 Power Management Control Fields
          • 18.5.1.7 Power-Down Sequence Coordination
            • Table18-23. Power Management Entry Protocol and Initiating Functional Units
            • Figure18-20. MPC8540 Power Management Handshaking Signals
          • 18.5.1.8 Interrupts and Power Management
            • 18.5.1.8.1 Interrupts and Power Management Controlled by MSR[WE]
            • 18.5.1.8.2 Interrupts and Power Management Controlled by POWMGTCSR
          • 18.5.1.9 Snooping in Power-Down Modes
          • 18.5.1.10 Software Considerations for Power Management
          • 18.5.1.11 Requirements for Reaching and Recovering from Sleep State
        • 18.5.2 General-Purpose I/O Signals
        • 18.5.3 Interrupt and Local Bus Signal Multiplexing
    • Chapter19 Performance Monitor
      • 19.1 Introduction
        • 19.1.1 Overview
          • Figure19-1. Performance Monitor Block Diagram
        • 19.1.2 Features
      • 19.2 External Signal Descriptions
      • 19.3 Memory Map and Register Definition
        • 19.3.1 Register Summary
          • Table19-1. Control Register Memory Map
        • 19.3.2 Control Registers
          • 19.3.2.1 Performance Monitor Global Control Register (PMGC0)
            • Figure19-2. Performance Monitor Global Control Register (PMGC0)
            • Table19-2. PMGC0 Field Descriptions 
          • 19.3.2.2 Performance Monitor Local Control Registers (PMLCAn and PMLCBn)
            • Figure19-3. Performance Monitor Local Control Register A0 (PMLCA0)
            • Table19-3. PMLCA0 Field Descriptions
            • Figure19-4. Performance Monitor Local Control Registers A1�A8 (PMLCA1�PMLCA8)
            • Table19-4. PMLCA1�PMLC8 Field Descriptions
            • Figure19-5. Performance Monitor Local Control Register B0 (PMLCB0)
            • Table19-5. PMLCB0 Field Descriptions
            • Figure19-6. Performance Monitor Local Control Registers B1�B8 (PMLCB1�PMLCB8)
            • Table19-6. PMLCBn Field Descriptions 
        • 19.3.3 Counter Registers
          • 19.3.3.1 Performance Monitor Counters (PMC0�PMC8)
            • Figure19-7. Performance Monitor Counter Register 0 (PMC0)
            • Table19-7. PMC0 Field Descriptions
            • Figure19-8. Performance Monitor Counter Registers 1�8 (PMC1�PMC8)
            • Table19-8. PMCn Field Descriptions
      • 19.4 Functional Description
        • 19.4.1 Performance Monitor Interrupt
        • 19.4.2 Event Counting
        • 19.4.3 Threshold Events
          • Figure19-9. Duration Threshold Event Sequence Timing Diagram
        • 19.4.4 Chaining
        • 19.4.5 Triggering
        • 19.4.6 Burstiness Counting
          • Table19-9. Burst Definition
          • Figure19-10. Burst Size, Distance, Granularity, and Burstiness Counting
          • Figure19-11. Burstiness Counting Timing Diagram
        • 19.4.7 Performance Monitor Events
          • Table19-10. Performance Monitor Events
        • 19.4.8 Performance Monitor Examples
          • Table19-11. PMGC0 and PMLCAn Settings
          • Table19-12. Register Settings for Counting Examples MPC8540 
    • Chapter20 Debug Features and Watchpoint Facility
      • 20.1 Introduction
        • Figure20-1. Debug and Watchpoint Monitor Block Diagram
        • 20.1.1 Overview
        • 20.1.2 Features
        • 20.1.3 Modes of Operation
          • Table20-1. POR Configuration Settings and Debug Modes
          • 20.1.3.1 Local Bus (LBC) Debug Mode
          • 20.1.3.2 DDR SDRAM Interface Debug Modes
          • 20.1.3.3 PCI/PCI-X Interface Debug Modes
          • 20.1.3.4 Watchpoint Monitor Modes
          • 20.1.3.5 Trace Buffer Modes
      • 20.2 External Signal Descriptions
        • 20.2.1 Overview
          • Table20-2. Debug, Watchpoint and Test Signal Summary
        • 20.2.2 Detailed Signal Descriptions
          • 20.2.2.1 Debug Signals�Details
            • Table20-3. Debug Signals�Detailed Signal Descriptions
          • 20.2.2.2 Watchpoint Monitor Trigger Signals�Details
            • Table20-4. Watchpoint and Trigger Signals�Detailed Signal Descriptions
          • 20.2.2.3 Test Signals�Details
            • Table20-5. JTAG Test and Other Signals�Detailed Signal Descriptions
      • 20.3 Memory Map/Register Definition
        • Table20-6. Debug and Watchpoint Monitor Memory Map 
        • 20.3.1 Watchpoint Monitor Register Descriptions
          • 20.3.1.1 Watchpoint Monitor Control Registers 0�1 (WMCR0, WMCR1)
            • Figure20-2. Watchpoint Monitor Control Register 0 (WMCR0)
            • Table20-7. WMCR0 Field Descriptions 
            • Figure20-3. Watchpoint Monitor Control Register 1 (WMCR1)
            • Table20-8. WMCR1 Field Descriptions 
          • 20.3.1.2 Watchpoint Monitor Address Register (WMAR)
            • Figure20-4. Watchpoint Monitor Address Register (WMAR)
            • Table20-9. WMAR Field Descriptions 
          • 20.3.1.3 Watchpoint Monitor Address Mask Register (WMAMR)
            • Figure20-5. Watchpoint Monitor Address Mask Register (WMAMR)
            • Table20-10. WMAMR Field Descriptions 
          • 20.3.1.4 Watchpoint Monitor Transaction Mask Register (WMTMR)
            • Figure20-6. Watchpoint Monitor Transaction Mask Register (WMTMR)
            • Table20-11. WMTMR Field Descriptions 
            • Table20-12. Transaction Types by Interface 
          • 20.3.1.5 Watchpoint Monitor Status Register (WMSR)
            • Figure20-7. Watchpoint Monitor Status Register (WMSR)
            • Table20-13. WMSR Field Descriptions 
        • 20.3.2 Trace Buffer Register Descriptions
          • 20.3.2.1 Trace Buffer Control Registers (TBCR0, TBCR1)
            • Figure20-8. Trace Buffer Control Register 0 (TBCR0)
            • Table20-14. TBCR0 Field Descriptions 
            • Figure20-9. Trace Buffer Control Register 1 (TBCR1)
            • Table20-15. TBCR1 Field Descriptions 
          • 20.3.2.2 Trace Buffer Address Register (TBAR)
            • Figure20-10. Trace Buffer Address Register (TBAR)
            • Table20-16. TBAR Field Descriptions 
          • 20.3.2.3 Trace Buffer Address Mask Register (TBAMR)
            • Figure20-11. Trace Buffer Address Mask Register (TBAMR)
            • Table20-17. TBAMR Field Descriptions 
          • 20.3.2.4 Trace Buffer Transaction Mask Register (TBTMR)
            • Figure20-12. Trace Buffer Transaction Mask Register (TBTMR)
            • Table20-18. TBTMR Field Descriptions 
          • 20.3.2.5 Trace Buffer Status Register (TBSR)
            • Figure20-13. Trace Buffer Status Register (TBSR)
            • Table20-19. TBSR Field Descriptions 
          • 20.3.2.6 Trace Buffer Access Control Register (TBACR)
            • Figure20-14. Trace Buffer Access Control Register (TBACR)
            • Table20-20. TBACR Field Descriptions 
          • 20.3.2.7 Trace Buffer Access Data High Register (TBADHR)
            • Figure20-15. Trace Buffer Read High Register (TBADHR)
            • Table20-21. TBADHR Field Descriptions 
          • 20.3.2.8 Trace Buffer Access Data Register (TBADR)
            • Figure20-16. Trace Buffer Access Data Register (TBADR)
            • Table20-22. TBADR Field Descriptions 
        • 20.3.3 Context ID Registers
          • 20.3.3.1 Programmed Context ID Register (PCIDR)
            • Figure20-17. Programmed Context ID Register (PCIDR)
            • Table20-23. PCIDR Field Descriptions 
          • 20.3.3.2 Current Context ID Register (CCIDR)
            • Figure20-18. Current Context ID Register (CCIDR)
            • Table20-24. CCIDR Field Descriptions 
        • 20.3.4 Trigger Out Function
          • 20.3.4.1 Trigger Out Source Register (TOSR)
            • Figure20-19. Trigger Out Source Register (TOSR)
            • Table20-25. TOSR Field Descriptions 
      • 20.4 Functional Description
        • 20.4.1 Source and Target ID
          • Table20-26. Source and Target ID Values
        • 20.4.2 PCI/PCI-X Interface Debug
        • 20.4.3 DDR SDRAM Interface Debug
          • 20.4.3.1 Debug Information on Debug Pins
          • 20.4.3.2 Debug Information on ECC Pins
        • 20.4.4 Local Bus Interface Debug
        • 20.4.5 Watchpoint Monitor
          • 20.4.5.1 Watchpoint Monitor Performance Monitor Events
        • 20.4.6 Trace Buffer
          • 20.4.6.1 Traced Data Formats (as a Function of TBCR1[IFSEL])
            • Figure20-20. e500 Coherency Module Dispatch (CMD) Trace Buffer Entry
            • Table20-27. CMD Trace Buffer Entry Field Descriptions (TBCR1[IFSEL]=000)
            • Figure20-21. DDR Trace Buffer Entry
            • Table20-28. DDR Trace Buffer Entry Field Descriptions (TBCR1[IFSEL]=001)
            • Figure20-22. PCI Trace Buffer Entry
            • Table20-29. PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL]=010)
            • Figure20-23. RapidIO Trace Buffer Entry
            • Table20-30. RapidIO Trace Buffer Entry Field Descriptions (TBCR1[IFSEL]=011)
      • 20.5 Initialization
    • Chapter21 10/100 Fast Ethernet Controller
      • 21.1 Introduction
        • Figure21-1. 10/100 Fast Ethernet Controller in Relation to the OSI Protocol Stack
        • Figure21-2. Ethernet/IEEE 802.3 Frame Structure
        • Figure21-3. Ethernet/IEEE 802.3 Frame Structure With More Details
        • Figure21-4. FEC Block Diagram
        • 21.1.1 10/100 Fast Ethernet Controller Overview
      • 21.2 Features
      • 21.3 Modes of Operation
      • 21.4 External Signal Descriptions
        • 21.4.1 Detailed Signal Descriptions
          • Table21-1. FEC Signals�Detailed Signal Descriptions
      • 21.5 Memory Map/Register Definition
        • 21.5.1 Top-Level Module Memory Map
          • Table21-2. Module Memory Map Summary
        • 21.5.2 Detailed Memory Map
          • Table21-3. Module Memory Map 
        • 21.5.3 Memory-Mapped Register Descriptions
          • 21.5.3.1 FEC General Control and Status Registers
            • 21.5.3.1.1 Interrupt Event Register (IEVENT)
              • Figure21-5. IEVENT Register Definition
              • Table21-4. IEVENT Field Descriptions
            • 21.5.3.1.2 Interrupt Mask Register (IMASK)
              • Figure21-6. IMASK Register Definition
              • Table21-5. IMASK Field Descriptions
            • 21.5.3.1.3 Error Disabled Register (EDIS)
              • Figure21-7. EDIS Register Definition
              • Table21-6. EDIS Field Descriptions
            • 21.5.3.1.4 Minimum Frame Length Register (MINFLR)
              • Figure21-8. MINFLR Register Definition
              • Table21-7. MINFLR Field Descriptions
            • 21.5.3.1.5 Pause Time Value Register (PTV)
              • Figure21-9. PTV Register Definition
              • Table21-8. PTV Field Descriptions
            • 21.5.3.1.6 DMA Control Register (DMACTRL)
              • Figure21-10. DMACTRL Register Definition
              • Table21-9. DMACTRL Field Descriptions
          • 21.5.3.2 FEC FIFO Control and Status Registers
            • 21.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)
              • Figure21-11. FIFO_PAUSE_CTRL Register Definition
              • Table21-10. FIFO_PAUSE_CTRL Field Descriptions
            • 21.5.3.2.2 FIFO Transmit Threshold Register (FIFO_TX_THR)
              • Figure21-12. FIFO_TX_THR Register Definition
              • Table21-11. FIFO_TX_THR Field Descriptions
            • 21.5.3.2.3 FIFO Transmit Starve Register (FIFO_TX_STARVE)
              • Figure21-13. FIFO_TX_STARVE Register Definition
              • Table21-12. FIFO_TX_STARVE Field Descriptions
            • 21.5.3.2.4 FIFO Transmit Starve Shutoff Register (FIFO_TX_STARVE_SHUTOFF)
              • Figure21-14. FIFO_TX_STARVE_SHUTOFF Register Definition
              • Table21-13. FIFO_TX_STARVE_SHUTOFF Field Descriptions
          • 21.5.3.3 FEC Transmit Control and Status Registers
            • 21.5.3.3.1 Transmit Control Register (TCTRL)
              • Figure21-15. TCTRL Register Definition
              • Table21-14. TCTRL Field Descriptions
            • 21.5.3.3.2 Transmit Status Register (TSTAT)
              • Figure21-16. TSTAT Register Definition
              • Table21-15. TSTAT Field Descriptions
            • 21.5.3.3.3 TxBD Data Length Register (TBDLEN)
              • Figure21-17. TBDLEN Register Definition
              • Table21-16. TBDLEN Field Descriptions
            • 21.5.3.3.4 Current Transmit Buffer Descriptor Pointer Register (CTBPTR)
              • Figure21-18. CTBPTR Register Definition
              • Table21-17. CTBPTR Field Descriptions
            • 21.5.3.3.5 Transmit Buffer Descriptor Pointer Register (TBPTR)
              • Figure21-19. TBPTR Register Definition
              • Table21-18. TBPTR Field Descriptions
            • 21.5.3.3.6 Transmit Descriptor Base Address Register (TBASE)
              • Figure21-20. TBASE Register Definition
              • Table21-19. TBASE Field Descriptions
            • 21.5.3.3.7 Out-of-Sequence TxBD Register (OSTBD)
              • Figure21-21. OSTBD Register Definition
              • Table21-20. OSTBD Field Descriptions
            • 21.5.3.3.8 Out-of-Sequence Tx Data Buffer Pointer Register (OSTBDP)
              • Figure21-22. OSTBDP Register Definition
              • Table21-21. OSTBDP Field Descriptions
          • 21.5.3.4 FEC Receive Control and Status Registers
            • 21.5.3.4.1 Receive Control Register (RCTRL)
              • Figure21-23. RCTRL Register Definition
              • Table21-22. RCTRL Field Descriptions
            • 21.5.3.4.2 Receive Status Register (RSTAT)
              • Figure21-24. RSTAT Register Definition
              • Table21-23. RSTAT Field Descriptions
            • 21.5.3.4.3 RxBD Data Length Register (RBDLEN)
              • Figure21-25. RBDLEN Register Definition
              • Table21-24. RBDLEN Field Descriptions
            • 21.5.3.4.4 Current Receive Buffer Descriptor Pointer Register (CRBPTR)
              • Figure21-26. CRBPTR Register Definition
              • Table21-25. CRBPTR Field Descriptions
            • 21.5.3.4.5 Maximum Receive Buffer Length Register (MRBLR)
              • Figure21-27. MRBLR Register Definition
              • Table21-26. MRBLR Field Descriptions
            • 21.5.3.4.6 Receive Buffer Descriptor Pointer Register (RBPTR)
              • Figure21-28. Receive Buffer Descriptor Pointer Definition
              • Table21-27. RBPTR Field Descriptions
            • 21.5.3.4.7 Receive Descriptor Base Address Register (RBASE)
              • Figure21-29. RBASE Register Definition
              • Table21-28. RBASE Field Descriptions
          • 21.5.3.5 MAC Functionality
            • 21.5.3.5.1 Configuring the MAC
            • 21.5.3.5.2 Controlling CSMA/CD
            • 21.5.3.5.3 Handling Packet Collisions
            • 21.5.3.5.4 Controlling Packet Flow
          • 21.5.3.6 MAC Registers
            • 21.5.3.6.1 MAC Configuration Register 1 (MACCFG1)
              • Figure21-30. MACCFG1 Register Definition
              • Table21-29. MACCFG1 Field Descriptions
            • 21.5.3.6.2 MAC Configuration Register 2 (MACCFG2)
              • Figure21-31. MACCFG2 Register Definition
              • Table21-30. MACCFG2 Field Descriptions
            • 21.5.3.6.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
              • Figure21-32. IPGIFG Register Definition
              • Table21-31. IPGIFG Field Descriptions
            • 21.5.3.6.4 Half-Duplex Register (HAFDUP)
              • Figure21-33. Half-Duplex Register Definition
              • Table21-32. HAFDUP Field Descriptions
            • 21.5.3.6.5 Maximum Frame Length Register (MAXFRM)
              • Figure21-34. Maximum Frame Length Register Definition
              • Table21-33. MAXFRM Descriptions
            • 21.5.3.6.6 Interface Status Register (IFSTAT)
              • Figure21-35. Interface Status Register Definition
              • Table21-34. IFSTAT Field Descriptions
            • 21.5.3.6.7 Station Address Register Part 1 (MACSTNADDR1)
              • Figure21-36. Station Address Part 1 Register Definition
              • Table21-35. MACSTNADDR1 Field Descriptions
            • 21.5.3.6.8 Station Address Register Part 2 (MACSTNADDR2)
              • Figure21-37. Station Address Part 2 Register Definition
              • Table21-36. MACSTNADDR2 Field Descriptions
          • 21.5.3.7 Hash Function Registers
            • 21.5.3.7.1 Individual Address Registers 0�7 (IADDRn)
              • Figure21-38. IADDRn Register Definition
              • Table21-37. IADDRn Field Description
            • 21.5.3.7.2 Group Address Registers 0�7 (GADDRn)
              • Figure21-39. GADDRn Register Definition
              • Table21-38. GADDRn Field Description
          • 21.5.3.8 Attribute Registers
            • 21.5.3.8.1 Attribute Register (ATTR)
              • Figure21-40. ATTR Register Definition
              • Table21-39. ATTR Field Descriptions
            • 21.5.3.8.2 Attribute Extract Length and Extract Index Register (ATTRELI)
              • Figure21-41. ATTRELI Register Definition
              • Table21-40. ATTRELI Field Descriptions 
      • 21.6 Functional Description
        • 21.6.1 Connecting to the Physical Interface
          • 21.6.1.1 Media-Independent Interface (MII)
            • Figure21-42. FEC�MII Connection
            • Table21-41. MII Interface Signals 
        • 21.6.2 FEC Channel Operation
          • 21.6.2.1 Initialization Sequence
            • 21.6.2.1.1 Hardware Controlled Initialization
            • 21.6.2.1.2 User Initialization
              • Table21-42. Steps of Minimum Register Initialization
          • 21.6.2.2 Soft Reset and Reconfiguring Procedure
          • 21.6.2.3 FEC Frame Transmission
          • 21.6.2.4 FEC Frame Reception
          • 21.6.2.5 Frame Recognition
            • 21.6.2.5.1 Destination Address Recognition
              • Figure21-43. Ethernet Address Recognition Flowchart
            • 21.6.2.5.2 Hash Table Algorithm
            • 21.6.2.5.3 CRC Computation Examples
          • 21.6.2.6 Flow Control
            • Table21-43. Flow Control Frame Structure 
          • 21.6.2.7 Interrupt Handling
            • Table21-44. Non-Error Transmit Interrupts 
            • Table21-45. Non-Error Receive Interrupts
          • 21.6.2.8 Inter-Packet Gap Time
          • 21.6.2.9 Internal and External Loop Back
          • 21.6.2.10 Error-Handling Procedure
            • Table21-46. Transmission Errors 
            • Table21-47. Reception Errors 
        • 21.6.3 Buffer Descriptors
          • Figure21-44. Example of FEC Memory Structure for BD
          • Figure21-45. Buffer Descriptor Ring
          • 21.6.3.1 Transmit Data Buffer Descriptor (TxBD)
            • Figure21-46. Transmit Buffer Descriptor
            • Table21-48. Transmit Data Buffer Descriptor (TxBD) Field Descriptions
          • 21.6.3.2 Receive Buffer Descriptor (RxBD)
            • Figure21-47. Receive Buffer Descriptor
            • Table21-49. Receive Buffer Descriptor Field Descriptions 
        • 21.6.4 Data Extraction to the L2 Cache
      • 21.7 Application Information
        • 21.7.1 Interface Mode Configuration
          • 21.7.1.1 MII Interface Mode
            • Table21-50. MII Interface Mode Signal Configuration 
            • Table21-51. MII Mode Register Initialization Steps
  • AppendixA Revision History
    • A.1 Changes From Revision 0 to Revision 1
  • Glossary of Terms and Abbreviations
  • Index 1 Register Index (Memory-Mapped Registers)
  • Index 2 General Index