MPC9817

Rev 1, 11/2004

Freescale Semiconductor
Technical Data

Clock Generator for PowerQUICC

and PowerPC Microprocessors and

Microcontrollers

The MPC9817 is a PLL-based clock generator specifically designed for

Freescale Semiconductor Microprocessor and Microcontroller applications
including the PowerPC and PowerQUICC. This device generates the
microprocessor input clock and other microprocessor system and bus clocks at
any one of four output frequencies. These frequencies include the popular
33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock
outputs plus three reference outputs. The clock input reference is 25 MHz and
may be derived from an external source or by the addition of a 25-MHz crystal to
the on-chip crystal oscillator. The extended temperature range of the MPC9817
supports telecommunication and networking requirements.

Features
·

5 LVCMOS outputs for processor and other system circuitry

3 Buffered 25-MHz reference clock outputs

Crystal oscillator or external reference input

25-MHz input reference frequency

Selectable output frequencies include: 25, 33, 50, or 66 MHz

Low cycle-to-cycle and period jitter

Package: 20-lead SSOP

3.3-V supply

Supports computing, networking, and telecommunications applications

Ambient temperature range: 40°C to +85°C

Functional Description

The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS

output clocks. The output frequency of this bank is configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz
reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the
XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN
pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly
buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O
applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from
the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the
single-ended LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input
as well as other system components.

The MPC9817 is packaged in a 20-lead SSOP package.

MPC9817

MICROPROCESSOR

CLOCK GENERATOR

EN SUFFIX

20 SSOP PACKAGE

Pb-FREE PACKAGE

CASE 1461-01

SD SUFFIX

20 SSOP PACKAGE

CASE 1461-01

Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9817

Figure 1. MPC9817 Logic Diagram

Table 1. Pin Configurations

Pin

I/O

Type

Function

QA0, QA1, QA2, QA3, QA4

Output

LVCMOS

Clock Outputs

QREF0, QREF1, QREF2

Output

LVCMOS

Reference Output (25 MHz)

XTAL_IN

Input

LVCMOS

Crystal Oscillator Input Pin

XTAL_OUT

Output

LVCMOS

Crystal Oscillator Output Pin

FSEL0, FSEL1

Input

LVCMOS

Configures Bank A Clock Output Frequency (pull-up)

MR/OE

Input

LVCMOS

Enables All Outputs (pull-down)

3.3-V Supply

GND

Ground

Table 2. Function Table

Control

Default

FSEL0,FSEL1

25 MHz fed directly

from reference input,

PLL disabled

33 MHz

50 MHz

66 MHz

Ref

PLL

400 MHz

QA0

QA1

QA2

QA4

XTAL_IN

OSC

XTAL_OUT

FSEL0

QREF0

FSEL1

QA3

QREF1

QREF2

Data

Generator

MR/OE

33,50,66 MHz

25 MHz

Advanced Clock Drivers Devices
Freescale Semiconductor

MPC9817

Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View)

MPC9817 OPERATION

Crystal Oscillator

The MPC9817 features a fully integrated Pierce oscillator

to minimize system implementation costs. Other than the
addition of a 25-MHz crystal, no external components are
required.The crystal selection should be: 25 MHz, parallel
resonant type with a load specification of C

= 10 pF. Crystals

with a load specification of C

= 20 pF may be used, however,

the reference frequency may be higher than the specified
25 MHz. Externally supplied capacitors on both the XTAL_IN
and XTAL_OUT pins may be used to trim the frequency as
desired.

The crystal should be located as close to the MPC9817

XTAL_IN and XTAL_OUT pins as possible to avoid any board
level parasitic.

Power Supply Bypassing

The MPC9817 should have all V

pins bypassed with

0.01 capacitors and a minimum of one 1.0 capacitor for the
overall package. All capacitors should be located as close to
the SSOP pins as possible.

External Clock Source

An external reference source of 25 MHz may be applied to

the XTAL_IN pin. In this mode of operation, the XTAL_OUT
pin should be left floating.

XTAL_IN

XTAL_OUT

FSEL0

FSEL1

QREF2

GND

QREF1
QREF0

QA4
QA3
GND
QA2
QA1
V

QA0
MR/OE
GND

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

Table 3. Crystal Specifications

Parameter

Value

Crystal Cut

Fundamental AT Cut

Resonance

Parallel Resonance

Shunt Capacitance (C

)

57 pF

Load Capacitance (C

)

10 pF

Equivalent Series Resistance (ESR)

2060

Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9817

Table 4. Absolute Maximum Ratings

(1)

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.

Symbol

Characteristics

Min

Max

Unit

Condition

Supply Voltage

0.3

3.8

DC Input Current

±20

OUT

DC Output Current

±75

Storage Temperature

125

°C

Table 5. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Output Termination Voltage

÷ 2

ESD Protection (machine model)

200

HBM

ESD Protection (human body model)

2000

Latch-Up Immunity

200

Input Capacitance

Inputs

Thermal Resistance (junction-to-ambient)

80.8

°C/W

Ambient Temperature

°C

Table 6. DC Characteristics (V

= 3.3 V ± 5%, T

= 40° to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input High Voltage (XTAL_IN)

2.4

+ 0.3

Input threshold = V

Input High Voltage

2.0

+ 0.3

Input Low Voltage

0.8

LVCMOS

Input Current

(1)

1. Inputs have pull-down resistors affecting the input current.

150

= V

DDL

or GND

Output High Voltage

2.4

= 12 mA

Output Low Voltage

0.4

= 12 mA

OUT

Output Impedance

Maximum Quiescent Supply Current

8.0

15.0

pins

Advanced Clock Drivers Devices
Freescale Semiconductor

MPC9817

Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs)

Table 7. AC Characteristics

(1)

(2)

= 3.3 V ± 5%, T

= 40° to +85°C)

1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50

to V

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input and Output Timing Specification

ref

Input Reference Frequency

25 MHz Input

XTAL Input

25
25

MHz
MHz

VCO

VCO Frequency Range

400

MHz

MCX

Output Frequency (QAx)

FSEL0, FSEL1 = 00
FSEL0, FSEL1 = 01
FSEL0, FSEL1 = 10
FSEL0, FSEL1 = 11

Output Frequency (QREFx)

25
33
50
66
25

--
--
--
--
--

MHz
MHz
MHz
MHz
MHz

PLL locked

refPW

Reference Input Pulse Width

@ 25 MHz

Output Duty Cycle

47.5

52.5

out

Output Frequency Accuracy

Crystal

(3)

External Reference

3. Based upon recommended crystal specifications as outlined in operation section.

--
--

100

ppm
ppm

With recommended crystal
see Table 3

PLL Specifications

PLL Closed Loop Bandwidth

(4)

4. 3 dB point of PLL transfer characteristics.

500

kHz

LOCK

Maximum PLL Lock Time

Skew and Jitter Specifications

sk(O)

Output-to-Output Skew (within a bank)

100

sk(O)

Output-to-Output Skew (between bank A and bank Ref)

200

FSEL0, FSEL1 = 00

JIT(CC)

Cycle-to-Cycle Jitter

150

@ 25 MHz Input Reference
Q

output

JIT(PER)

Period Jitter

100

@ 25 MHz Input Reference
Q

output

, t

Output Rise/Fall Time

20% to 80%

Z = 50

= 50

Z = 50

DUT MPC9817

Pulse

Generator

Z = 50

= 50

Advanced Clock Drivers Devices
Freescale Semiconductor

MPC9817

PACKAGE DIMENSIONS

.337

.150

PIN 1 ID

.157

.344

.236

.118

.010

A-B

2X 10 TIPS

.003

A-B

.035

SECTION B-B

R.003 MIN

.0098
.0040

.016

0°

8°

0°

.010

GAUGE PLANE

MIN

.004 C

.055

SEATING
PLANE

.025

20X

18X

.061

.0125

(.010)

.012

.010

(.008)

PLATING

BASE METAL

SECTION A-A

.007

.008

.007

C A-B D

NOTES:

1.
2.

DIMENSIONS ARE IN INCHES.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
DATUM PLANE H LOCATED AT MOLD PARTING
LINE AND COINCIDENT WITH LEAD, WHERE
LEAD EXITS PLASTIC BODY AT BOTTOM OF
PARTING LINE.
DATUM A, B AND D TO BE DETRMINED WHERE
CENTERLINE BETWEEN LEADS EXITS PLASTIC
BODY AT DATUM PLANE H.
THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS, BUT DO INCLUDE
MOLD MISMATCH AND ARE MEASURED AT THE
MOLD PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED .006
INCHES FOR ENDS AND .008 INCHES FOR
SIDES.
THIS DIMENSION IS LENGTH OF TERMINAL FOR
SOLDERING A SUBSTRATE.
FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004
INCHES AT SEATING PLANE.
THIS DIMENSION IS DEFINED AS THE DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT OF THE PACKAGE BODY.

CASE 1461-02

ISSUE O

20 SSOP PACKAGE

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MPC9817
Rev. 1
11/2004

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