MPC9850
Rev 5, 4/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Clock Generator for PowerQUICC III
The MPC9850 is a PLL based clock generator specifically designed for
Freescale Microprocessor and Microcontroller applications including the
PowerQUICC III. This device generates a microprocessor input clock plus the
500 MHz Rapid I/O clock. The microprocessor clock is selectable in output
frequency to any of the commonly used microprocessor input and bus
frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight
low skew clock outputs organized into two output banks, each configurable to
support different clock frequencies. The extended temperature range of the
MPC9850 supports telecommunication and networking requirements.
Features
8 LVCMOS outputs for processor and other circuitry
2 differential LVDS outputs for Rapid I/O interface
Crystal oscillator or external reference input
25 or 33 MHz Input reference frequency
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,
50, 33 or 16 MHz
Buffered reference clock output
Rapid I/O (LVDS) Output = 500, 250 or 125 MHz
Low cycle-to-cycle and period jitter
100-lead PBGA package
100-lead Pb-free Package Available
3.3V supply with 3.3V or 2.5V output LVCMOS drive
Supports computing, networking, telecommunications applications
Ambient temperature range 40C to +85C
Functional Description
The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111,
100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use
in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency
is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III
communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be
used as the clock source for a Gigabit Ethernet PHY if desired.
The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal
oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are
required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input
frequency.
The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.
MPC9850
MICROPROCESSOR
CLOCK GENERATOR
SCALE 2 1
VF SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
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2
Freescale Semiconductor
MPC9850
Figure 1. MPC9850 Logic Diagram
Table 1. Pin Configurations
Pin
I/O
Type
Function
Supply
Active/State
CLK
Input
LVCMOS
PLL Reference Clock Input (pull-down)
V
DD
PCLK, PCLK
Input
LVPECL
PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and
pull-down)
V
DD
QA0, QA1, QA2, QA3 Output
LVCMOS
Bank A Outputs
V
DDOA
QB0, QB1, QB2, QB3 Output
LVCMOS
Bank B Outputs
V
DDOB
QC0, QC1, QC0,
QC1
Output
LVDS
Bank C Outputs
V
DDOC
REF_OUT
Output
LVCMOS
Reference Output (25 MHz or 33 MHz)
V
DD
XTAL_IN
Input
LVCMOS
Crystal Oscillator Input Pin
V
DD
XTAL_OUT
Output
LVCMOS
Crystal Oscillator Output Pin
V
DD
REF_CLK_SEL
Input
LVCMOS
Select between CLK and PCLK Input (pull-down)
V
DD
High
REF_SEL
Input
LVCMOS
Select between External Input and Crystal Oscillator Input (pull-down) V
DD
High
REF_33MHz
Input
LVCMOS
Selects 33 MHz Input (pull-down)
V
DD
High
MR
Input
LVCMOS
Master Reset (pull-up)
V
DD
Low
PLL_BYPASS
Input
LVCMOS
Select PLL or static test mode (pull-down)
V
DD
High
CLK_A[0:5]
(1)
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
Input
LVCMOS
Configures Bank A clock output frequency (pull-up)
V
DD
High
CLK_B[0:5]
(2)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
PowerPC bit ordering (bit 0 = msb, bit 1 = lsb)
Input
LVCMOS
Configures Bank B clock output frequency (pull-up)
V
DD
High
RIO_C [0:1]
Input
LVCMOS
Configures Bank C clock output frequency (pull-down)
V
DD
V
DD
3.3 V Supply
V
DDA
Analog Supply
V
DDOA
Supply for Output Bank A
V
DDOB
Supply for Output Bank B
V
DDOC
Supply for Output Bank C
GND
Ground
N
4, 8, 16, 40
QC0
PCLK
PCLK
CLK
REF_CLK_SEL
XTAL_IN
XTAL_OUT
REF_SEL
PLL_BYPASS
REF_33MHz
CLK_A[0:5]
CLK_B[0:5]
RIO_C[0:1]
MR
QC1
REF_OUT
QC1
QC0
QB3
QB2
QB1
QB0
QA3
QA2
QA1
QA0
N
PLL
2000 MHz
Ref
OSC
0
1
0
1
1
0
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MPC9850
Table 2. Function Table
Control
Default
0
1
REF_CLK_SEL
0
CLK
PCLK
REF_SEL
0
CLK or PCLK
XTAL
PLL_BYPASS
0
Normal
Bypass
REF_33MHz
0
Selects 25 MHz Reference
Selects 33 MHz Reference
MR
1
Reset
Normal
CLK_A, CLK_B, and RIO_C control output frequencies. See
Table 3
and
Table 4
for specific device configuration
Table 3. Output Configurations (Banks A & B)
CLK_x[0:5]
(1)
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
CLK_x[0]
(msb)
CLK_x[1]
CLK_x[2]
CLK_x[3]
CLK_x[4]
CLK_x[5]
(lsb)
N
Frequency
(MHz)
111111
1
1
1
1
1
1
126
15.87
111100
1
1
1
1
0
0
120
16.67
101000
1
0
1
0
0
0
80
25.00
011110
0
1
1
1
1
0
60
33.33
010100
0
1
0
1
0
0
40
50.00
001111
0
0
1
1
1
1
30
66.67
001100
0
0
1
1
0
0
24
83.33
001010
0
0
1
0
1
0
20
100.00
001001
0
0
1
0
0
1
18
111.11
001000
0
0
1
0
0
0
16
125.00
000111
0
0
0
1
1
1
15
133.33
000110
0
0
0
1
1
0
12
166.67
000101
0
0
0
1
0
1
10
200.00
000100
0
0
0
1
0
0
8
(2)
2. Minimum value for N
250
Table 4. Output Configurations (Bank C)
RIO_C[0:1]
Frequency (MHz)
00
50 (test output)
01
125
10
250
11
500
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Freescale Semiconductor
MPC9850
OPERATION INFORMATION
Output Frequency Configuration
The MPC9850 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems.
Table 3
lists the configuration
values that will generate those common frequencies. The
MPC9850 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(f
out
) of either Bank A or Bank B may be calculated by the
following equation.
f
out
= 2000 / N
where f
out
is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2
defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within V
DD
specifications. See
Table 11
for actual parameter values. The MPC9850 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
Figure 2. MR Operation
Power Supply Bypassing
The MPC9850 is a mixed analog/digital product. The
architecture of the MPC9850 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
DD
pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Figure 3. V
CC
Power Supply Bypass
MR
V
DD
t
reset_rel
t
reset_pulse
V
DD
MPC9850
0.1
F
22
F
0.1
F
15
V
DD
V
DDA
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Freescale Semiconductor
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MPC9850
Table 5. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
Condition
V
DD
Supply Voltage (core)
0.3
3.8
V
V
DDA
Supply Voltage (Analog Supply Voltage)
0.3
V
DD
V
V
DDOx
Supply Voltage (LVCMOS output for Bank A or B)
0.3
V
DD
V
V
IN
DC Input Voltage
0.3
V
DD
+0.3
V
V
OUT
DC Output Voltage
(2)
2. V
DDx
references power supply pin associated with specific output pin.
0.3
V
DDx
+0.3
V
I
IN
DC Input Current
20
mA
I
OUT
DC Output Current
50
mA
T
S
Storage Temperature
65
125
C
Table 6. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
V
TT
Output Termination Voltage
V
DD
2
V
HBM
ESD Protection (Human Body Model)
2000
V
CDM
ESD Protection (Charged Device Model)
500
V
LU
Latch-Up Immunity
100
mA
C
IN
Input Capacitance
4
pF
Inputs
C
PD
Power Dissipation Capacitance
10
pF
Per Output
JA
Thermal Resistance (junction-to-ambient)
54.5
C/W Air flow = 0
T
A
Ambient Temperature
40
85
C
Table 7. DC Characteristics (T
A
= 40C to 85C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Supply Current for V
DD
= 3.3 V
5%, V
DDOA
= 3.3 V
5 and V
DDOB
= 3.3 V
5%
I
DD
+ I
DDA
Maximum Quiescent Supply Current (Core)
200
mA
V
DD
+ V
DDA
pins
I
DDA
Maximum Quiescent Supply Current (Analog Supply)
15
mA
V
DDIN
pins
I
DDOA
,
I
DDOB
Maximum Bank A and B Supply Current
175
mA
V
DDOA
and
V
DDOB
pins
Supply Current for V
DD
= 3.3 V
5%, V
DDOA
= 2.5 V
5% and V
DDOB
= 2.5 V
5%
I
DD
+ I
DDA
Maximum Quiescent Supply Current (Core)
200
mA
V
DD
+ V
DDA
pins
I
DDA
Maximum Quiescent Supply Current (Analog Supply)
15
mA
V
DDIN
pins
I
DDOA
,
I
DDOB
Maximum Bank A and B Supply Current
100
mA
V
DDOA
and
V
DDOB
pins
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Freescale Semiconductor
MPC9850
Table 8. LVDS DC Characteristics (T
A
= 40C to 85C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVDS Clock Outputs (QC0, QC0 and QC1, QC1) for V
DD
= 3.3 V
5%
V
PP
Output Differential Voltage
(1)
(peak-to-peak)
(LVDS)
1. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
100
400
mV
V
OS
Output Offset Voltage
(LVDS)
1050
1600
mV
Table 9. LVPECL DC Characteristics (T
A
= 40C to 85C)
(1)
1. AC characteristics are design targets and pending characterization.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL Clock Inputs (CLK1, CLK1) for V
DD
= 3.3 V
0.5%
V
PP
Differential Voltage
(2)
(peak-to-peak)
(LVPECL)
2. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including t
PD
and device-to-device skew.
250
mV
V
CMR
Differential Input Crosspoint Voltage
(3)
(LVPECL)
3. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
(AC)
range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the device propagation delay,
device and part-to-part skew.
1.0
V
DD
0.6
V
Table 10. LVCMOS I/O DC Characteristics (T
A
= 40C to 85C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS for V
DD
= 3.3 V
5%
V
IH
Input High Voltage
2.0
V
DD
+ 0.3
V
LVCMOS
V
IL
Input Low Voltage
0.8
V
LVCMOS
I
IN
Input Current
(1)
1. Inputs have pull-down resistors affecting the input current.
200
A
V
IN
= V
DDL
or GND
LVCMOS for V
DD
= 3.3 V
5%, V
DDOA
= 3.3 V
5 and V
DDOB
= 3.3 V
5%
V
OH
Output High Voltage
2.4
V
I
OH
= 24 mA
V
OL
Output Low Voltage
0.5
V
I
OL
= 24 mA
Z
OUT
Output Impedance
14 17
LVCMOS for V
DD
= 3.3 V
5%, V
DDOA
= 2.5 V
5% and V
DDOB
= 2.5 V
5%
V
OH
Output High Voltage
1.9
V
I
OH
= 15 mA
V
OL
Output Low Voltage
0.4
V
I
OL
= 15 mA
Z
OUT
Output Impedance
18 22
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Freescale Semiconductor
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MPC9850
Figure 4. MPC9850 AC Test Reference (LVDS Outputs)
Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs)
Table 11. AC Characteristics (V
DD
= 3.3 V 5%, V
DDOA
= 3.3 V 5%,V
DDOB
= 3.3 V 5%, T
A
= 40C to +85C)
(1)
(2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to V
TT
.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
f
ref
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode
(3)
3. In bypass mode, the MPC9850 divides the input reference clock.
25
33
25
250
MHz
MHz
MHz
MHz
PLL bypass
f
VCO
VCO Frequency Range
(4)
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
ref
= (f
VCO
M) N.
2000
MHz
f
MCX
Output Frequency
Bank A output
Bank B output
Bank C output
15.87
15.87
50
200
200
500
MHz
MHz
MHz
PLL locked
f
refPW
Reference Input Pulse Width
2
ns
f
refCcc
Input Frequency Accuracy
100
ppm
t
r
, t
f
Output Rise/Fall Time
150
500
ps
20% to 80%
DC
Output Duty Cycle
43
47
50
50
57
53
%
Bank A and B
Bank C
PLL Specifications
t
LOCK
Maximum PLL Lock Time
10
ms
t
reset_ref
MR Hold Time on Power Up
10
ns
t
reset_pulse
MR Hold Time
10
ns
Skew and Jitter Specifications
t
sk(O)
Output-to-Output Skew (within a bank)
50
ps
t
sk(O)
Output-to-Output Skew (across banks A and B)
400
ps
V
DDOA
= 3.3 V
V
DDOB
= 3.3 V
t
JIT(CC)
Cycle-to-Cycle Jitter
200
150
ps
ps
Bank A and B
Bank C
t
JIT(PER)
Period Jitter
200
ps
Bank A and C
t
JIT(
)
I/O Phase Jitter
RMS (1
)
50
ps
Bank A and C
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
DUT MPC9850
V
TT
R
T
= 100
Z
O
= 50
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
DUT MPC9850
V
TT
Z
O
= 50
R
T
= 50
V
TT
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Freescale Semiconductor
MPC9850
Table 12. MPC9850 Pin Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
A
V
DDOA
V
DDOA
CLKA[1]
CLKA[3]
CLKA[5]
V
DD
QA1
QA2
V
DDOA
V
DDOA
B
V
DDOA
V
DDOA
CLKA[0]
CLKA[2]
CLKA[4]
QA0
V
DDOA
QA3
V
DDOA
V
DDOA
C
RSVD
RSVD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
REF_OUT
D
V
DDA
V
DDA
V
DD
GND
GND
GND
GND
V
DD
QC0
QC0
E
REF_SEL
CLK
V
DD
GND
GND
GND
GND
V
DD
V
DDOC
GND
F
PCLK
PCLK
V
DD
GND
GND
GND
GND
V
DD
QC1
QC1
G
REF_CLK_SEL
REF_33MHz
V
DD
GND
GND
GND
GND
V
DD
PLL_BYPASS
MR
H
XTAL_IN
XTAL_OUT
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
RIO_C[1]
RIO_C[0]
J
V
DDOB
V
DDOB
CLKB[0]
CLKB[2]
CLKB[4]
QB0
V
DDOB
QB3
V
DDOB
V
DDOB
K
V
DDOB
V
DDOB
CLKB[1]
CLKB[3]
CLKB[5]
V
DD
QB1
QB2
V
DDOB
V
DDOB
Table 13. MPC9850 Pin List
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
Signal
100 Pin
MAPBGA
V
DDOA
A1
RSVD
(1)
1. RSVD pins must be left open.
C1
REF_SEL
E1
REF_CLK_SEL
G1
V
DDOB
J1
V
DDOA
A2
RSVD
(1)
C2
CLK
E2
REF_33MHz
G2
V
DDOB
J2
CLKA[1]
A3
V
DD
C3
V
DD
E3
V
DD
G3
CLKB[0]
J3
CLKA[3]
A4
V
DD
C4
GND
E4
GND
G4
CLKB[2]
J4
CLKA[5]
A5
V
DD
C5
GND
E5
GND
G5
CLKB[4]
J5
V
DD
A6
V
DD
C6
GND
E6
GND
G6
QB0
J6
QA1
A7
V
DD
C7
GND
E7
GND
G7
V
DDOB
J7
QA2
A8
V
DD
C8
V
DD
E8
V
DD
G8
QB3
J8
V
DDOA
A9
V
DD
C9
V
DDOC
E9
PLL_BYPASS
G9
V
DDOB
J9
V
DDOA
A10
REF_OUT
C10
GND
E10
MR
G10
V
DDOB
J10
V
DDOA
B1
V
DDA
D1
PCLK
F1
XTAL_IN
H1
V
DDOB
K1
V
DDOA
B2
V
DDA
D2
PCLK
F2
XTAL_OUT
H2
V
DDOB
K2
CLKA[0]
B3
V
DD
D3
V
DD
F3
V
DD
H3
CLKB[1]
K3
CLKA[2]
B4
GND
D4
GND
F4
V
DD
H4
CLKB[3]
K4
CLKA[4]
B5
GND
D5
GND
F5
V
DD
H5
CLKB[5]
K5
QA0
B6
GND
D6
GND
F6
V
DD
H6
V
DD
K6
V
DDOA
B7
GND
D7
GND
F7
V
DD
H7
QB1
K7
QA3
B8
V
DD
D8
V
DD
F8
V
DD
H8
QB2
K8
V
DDOA
B9
QC0
D9
QC1
F9
RIO_C[1]
H9
V
DDOB
K9
V
DDOA
B10
QC0
D10
QC1
F10
RIO_C[0]
H10
V
DDOB
K10
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Freescale Semiconductor
9
MPC9850
PACKAGE DIMENSIONS
VA SUFFIX
VM SUFFIX (PB-FREE)
100 MAPBGA PACKAGE
CASE 1462-01
ISSUE O
A1 INDEX
AREA
B
C
0.2
11
TOP VIEW
11
4X
A1 INDEX
AREA
9X
10
9
8
7
4
3
2
1
A
B
C
D
E
F
G
H
J
K
3
BOTTOM VIEW
B
M
0.25
C
A
M
0.10
A
100X
0.55
0.45
6
5
1
0.5
0.5
9X
1
K
SIDE VIEW
A
0.35 A
0.12 A
100X
0.43
4
(1.18)
1.7 MAX
ROTATED 90 CLOCKWISE
DETAIL K
SEATING
PLANE
0.29
5
NOTES:
1.
2.
3.
4.
5.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
MAXIMUM SOLDER BALL DIAMETER MEASURED
PARALLEL TO DATUM A.
DATUM A, SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGING.
Advanced Clock Drivers Devices
10
Freescale Semiconductor
MPC9850
NOTES
Advanced Clock Drivers Devices
Freescale Semiconductor
11
MPC9850
NOTES
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4/2005
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