Document Outline

• Chapter 1 Introduction
  • 1.1 Audience
  • 1.2 Additional Reading
  • 1.3 Terminology
  • 1.4 Part Number Coding
• Chapter 2 Device Overview
  • 2.1 Introduction
    • 2.1.1 Features
    • 2.1.2 Implementation Details and Constraints
    • 2.1.3 Modes of Operation
    • 2.1.4 Block Diagram
    • 2.1.5 Memory Map
    • 2.1.6 Part ID Assignments
  • 2.2 Signal Descriptions
    • 2.2.1 System Pinout
    • 2.2.2 Pin Functions and Signal Properties
    • 2.2.3 Detailed Signal Descriptions
    • 2.2.4 Power Supply Pins
  • 2.3 System Clock Description
  • 2.4 Modes of Operation
    • 2.4.1 Overview
    • 2.4.2 Recommended Pullup/down Resistor Values
    • 2.4.3 Host Controller Interfaces
    • 2.4.4 External Output Clock
    • 2.4.5 MFR4200 Connection to FlexRay Network
    • 2.4.6 Power Mode
  • 2.5 Resets and Interrupts
    • 2.5.1 Overview
    • 2.5.2 Resets
    • 2.5.3 Interrupt Sources
• Chapter 3 MFR4200 FlexRay Communication Controller
  • 3.1 Introduction
    • 3.1.1 MFR4200 Features
    • 3.1.2 MFR4200 Implementation Parameters and Constraints
  • 3.2 Memory Map and Registers
    • 3.2.1 Introduction
    • 3.2.2 Register Map Summary
    • 3.2.3 Register Descriptions
  • 3.3 Message Buffer
    • 3.3.1 Message Buffer Layout
    • 3.3.2 Message Buffer Field Descriptions
    • 3.3.3 Message Buffer Slot Status Vector
    • 3.3.4 Message ID
    • 3.3.5 NMVector Fields
    • 3.3.6 Data[0:31] - Data Fields
  • 3.4 Message Buffer Control, Configuration, Status and Filtering Register Set
    • 3.4.1 Message Buffer Control, Configuration and Status Register
    • 3.4.2 Message Buffer Filter Registers
    • 3.4.3 Receive FIFO Filters
  • 3.5 Message Buffer Handling and Operations
    • 3.5.1 Introduction
    • 3.5.2 Buffer Map
    • 3.5.3 Active Message Buffers
    • 3.5.4 Buffer Configuration
    • 3.5.5 Buffer Reconfiguration in the Normal State of Operation
    • 3.5.6 Message Buffer Operations
  • 3.6 Receive FIFO Function
  • 3.7 Host Controller Interfaces
    • 3.7.1 MFR4200 Asynchronous Memory Interface
    • 3.7.2 MFR4200 HCS12 Interface
  • 3.8 External 4/10 MHz Output Clock
  • 3.9 Communication Controller States
    • 3.9.1 Hard Reset State
    • 3.9.2 Configuration State
    • 3.9.3 Diagnosis Stop State
    • 3.9.4 Normal Active State
    • 3.9.5 Normal Passive State
  • 3.10 Debug Port
    • 3.10.1 Debug Port Overview
    • 3.10.2 Debug Port Functions
    • 3.10.3 Debug Port Function Timing
• Chapter 4 Dual Output Voltage Regulator (VREG3V3V2)
  • 4.1 Introduction
    • 4.1.1 Features
    • 4.1.2 Modes of Operation
    • 4.1.3 Block Diagram
  • 4.2 External Signal Description
    • 4.2.1 VDDR, VSSR - Regulator Power Input
    • 4.2.2 VDDA, VSSA - Regulator Reference Supply
    • 4.2.3 VDD, VSS - Regulator Output1 (Core Logic)
    • 4.2.4 VDDOSC, VSSOSC - Regulator Output2 (OSC)
    • 4.2.5 VREGEN - Optional Regulator Enable
  • 4.3 Functional Description
    • 4.3.1 REG - Regulator Core
    • 4.3.2 Full-performance Mode
    • 4.3.3 POR - Power On Reset
    • 4.3.4 LVR - Low Voltage Reset
    • 4.3.5 CTRL - Regulator Control
  • 4.4 Resets
    • 4.4.1 Power On Reset
    • 4.4.2 Low Voltage Reset
• Chapter 5 Clocks and Reset Generator
  • 5.1 Introduction
    • 5.1.1 Features
  • 5.2 Functional Description
    • 5.2.1 MFR4200 Pins Relevant to the CRG
    • 5.2.2 Reset Generation and CLKOUT Control
• Chapter 6 Oscillator (OSCV2)
  • 6.1 Introduction
    • 6.1.1 Features
    • 6.1.2 Modes of Operation
  • 6.2 External Signal Description
    • 6.2.1 VDDOSC and VSSOSC - OSC Operating Voltage, OSC Ground
    • 6.2.2 EXTAL and XTAL - Clock/Crystal Source Pins
  • 6.3 Functional Description
• Appendix A Electrical Characteristics
  • A.1 General
    • A.1.1 Parameter Classification
    • A.1.2 Power Supply
    • A.1.3 Pins
    • A.1.4 Current Injection
    • A.1.5 Absolute Maximum Ratings
    • A.1.6 ESD Protection and Latch-up Immunity
    • A.1.7 Operating Conditions
    • A.1.8 Power Dissipation and Thermal Characteristics
    • A.1.9 I/O Characteristics
    • A.1.10 Supply Currents
  • A.2 Voltage Regulator (VREG)
    • A.2.1 Operating Conditions
    • A.2.2 Chip Power-up and Voltage Drops
    • A.2.3 Output Loads
  • A.3 Reset and Oscillator
    • A.3.1 Startup
    • A.3.2 Oscillator
  • A.4 AMI Interface Timing Diagram
  • A.5 HCS12 Interface Timing Diagram
• Appendix B Package Information
  • B.1 64-pin LQFP package
• Appendix C Printed Circuit Board Layout Recommendations
• Appendix C MFR4200 Protocol Implementation Document
  • C.1 Introduction
    • C.1.1 Purpose
    • C.1.2 Structure
    • C.1.3 References
  • C.2 Overall Protocol State Machine
  • C.3 Coding and Decoding
    • C.3.1 Overview
    • C.3.2 NRZ Coding
    • C.3.3 NRZ Decoding
    • C.3.4 Signal Integrity
  • C.4 Frame Format
  • C.5 Media Access Control
  • C.6 Frame and Symbol Processing
  • C.7 Wakeup, Startup, and Reintegration
    • C.7.1 Introduction
    • C.7.2 Cluster Wakeup
    • C.7.3 Communication Startup and Reintegration
  • C.8 Clock Synchronization
    • C.8.1 Introduction
    • C.8.2 Time Representation
    • C.8.3 Synchronization Process
    • C.8.4 Clock Startup
    • C.8.5 Time Measurement
    • C.8.6 Correction Term Calculation
    • C.8.7 Clock Correction
    • C.8.8 Sync Frame Configuration Rules
  • C.9 Controller Host Interface
  • C.10 Device Specific Power Modes
  • C.11 Bus Guardian Schedule Monitoring
  • C.12 System Parameters and Configuration Constraints
    • C.12.1 System Parameters
    • C.12.2 Configuration Constraints
• Appendix D Index of Registers