Future Technology Devices International Ltd.
Copyright Future Technology Devices International Ltd. 2005
FT245R USB FIFO I.C.
Incorporating FTDIChip-IDTM Security Dongle
The
FT245R is the latest device to be added to FTDI's range of USB FIFO interface Integrated Circuit Devices.
The FT245R is a USB to parallel FIFO interface, with the new FTDIChip-IDTM security dongle feature. In addition,
asynchronous and synchronous bit bang interface modes are available. USB to parallel designs using the FT245R
have been further simplified by fully integrating the external EEPROM, clock circuit and USB resistors onto the device.
The FT245R adds a new function compared with its predecessors, effectively making it a "2-in-1" chip for some
application areas. A unique number (the FTDIChip-IDTM) is burnt into the device during manufacture and is readable
over USB, thus forming the basis of a security dongle which can be used to protect customer application software
from being copied.
The FT245R is available in Pb-free (RoHS compliant) compact 28-Lead SSOP and QFN-32 packages.
TM
FT245R USB UART I.C. Datasheet Version 1.02
Future Technology Devices International Ltd. 2005
Page 2
Single chip USB to parallel FIFO bidirectional data
transfer interface.
Entire USB protocol handled on the chip - No
USB-specific firmware programming required.
Simple interface to MCU / PLD / FPGA logic with
simple 4-wire handshake interface.
Data transfer rate to 1 Megabyte / second - D2XX
Direct Drivers.
Data transfer rate to 300 kilobyte / second - VCP
Drivers.
FTDI's royalty-free VCP and D2XX drivers
eliminate the requirement for USB driver
development in most cases.
New USB FTDIChip-IDTM feature.
FIFO receive and transmit buffers for high data
throughput.
Adjustable receive buffer timeout.
Synchronous and asynchronous bit bang mode
interface options with RD# and WR# strobes allow
the data bus to be used as a general purpose I/O
port.
Integrated 1024 Bit internal EEPROM for storing
USB VID, PID, serial number and product
description strings.
Device supplied preprogrammed with unique USB
serial number.
Support for USB suspend / resume through
PWREN# pin and Wake Up pin function.
In-built support for event characters.
Support for bus powered, self powered, and high-
power bus powered USB configurations.
Integrated 3.3V level converter for USB I/O .
Integrated level converter on FIFO interface and
control pins for interfacing to 5V - 1.8V Logic.
True 5V / 3.3V / 2.8V / 1.8V CMOS drive output
and TTL input.
High I/O pin output drive option.
Integrated USB resistors.
Integrated power-on-reset circuit.
Fully integrated clock - no external crystal,
oscillator, or resonator required.
Fully integrated AVCC supply filtering - No separate
AVCC pin and no external R-C filter required.
USB bulk transfer mode.
3.3V to 5.25V Single Supply Operation.
Low operating and USB suspend current.
Low USB bandwidth consumption.
UHCI / OHCI / EHCI host controller compatible
USB 2.0 Full Speed compatible.
-40C to 85C extended operating temperature
range.
Available in compact Pb-free 28 Pin SSOP and
QFN-32 packages (both RoHS compliant).
1. Features
1.1 Hardware Features
Royalty-Free VIRTUAL COM PORT
(VCP) DRIVERS for...
Windows 98, 98SE, ME, 2000, Server 2003, XP.
Windows Vista / Longhorn*
Windows XP 64-bit.*
Windows XP Embedded.
Windows CE.NET 4.2 & 5.0
MAC OS 8 / 9, OS-X
Linux 2.4 and greater
Royalty-Free D2XX Direct Drivers
(USB Drivers + DLL S/W Interface)
Windows 98, 98SE, ME, 2000, Server 2003, XP.
Windows Vista / Longhorn*
Windows XP 64-bit.*
Windows XP Embedded.
Windows CE.NET 4.2 & 5.0
Linux 2.4 and greater
1.2 Driver Support
The drivers listed above are all available to download for free from the FTDI website. Various 3rd Party Drivers are
also available for various other operating systems - see the
FTDI website
for details.
* Currently Under Development. Contact FTDI for availability.
Upgrading Legacy Peripherals to USB
Cellular and Cordless Phone USB data transfer
cables and interfaces
Interfacing MCU / PLD / FPGA based designs to
USB
USB Audio and Low Bandwidth Video data transfer
PDA to USB data transfer
USB Smart Card Readers
USB Instrumentation
USB Industrial Control
USB MP3 Player Interface
USB FLASH Card Reader / Writers
Set Top Box PC - USB interface
USB Digital Camera Interface
USB Hardware Modems
USB Wireless Modems
USB Bar Code Readers
USB Software / Hardware Encryption Dongles
1.3 Typical Applications
FT245R USB UART I.C. Datasheet Version 1.02
Future Technology Devices International Ltd. 2005
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2. Enhancements
2.1 Device Enhancements and Key Features
This section summarises the enhancements and the key features of the FT245R device. For further details, consult
the
device pin-out
description and
functional description
sections.
Integrated Clock Circuit - Previous generations of FTDI's USB to parallel FIFO interface devices required an external
crystal or ceramic resonator. The clock circuit has now been integrated onto the device meaning that no crystal or
ceramic resonator is required. However, if required, an external 12MHz crystal can be used as the clock source.
Integrated EEPROM - Previous generations of FTDI's USB to parallel FIFO interface devices required an external
EEPROM if the device were to use USB Vendor ID (VID), Product ID (PID), serial number and product description
strings other than the default values in the device itself. This external EEPROM has now been integrated onto the
FT245R chip meaning that all designs have the option to change the product description strings. A user area of the
internal EEPROM is available for storing additional data. The internal EEPROM is programmable in circuit, over USB
without any additional voltage requirement.
Preprogrammed EEPROM - The FT245R is supplied with its internal EEPROM preprogrammed with a serial number
which is unique to each individual device. This, in most cases, will remove the need to program the device EEPROM.
Integrated USB Resistors - Previous generations of FTDI's USB to parallel FIFO interface devices required two
external series resistors on the USBDP and USBDM lines, and a 1.5 k pull up resistor on USBDP. These three
resistors have now been integrated onto the device.
Integrated AVCC Filtering - Previous generations of FTDI's USB to parallel FIFO interface devices had a separate
AVCC pin - the supply to the internal PLL. This pin required an external R-C filter. The separate AVCC pin is now
connected internally to VCC, and the filter has now been integrated onto the chip.
Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC filter will substantially
reduce the bill of materials cost for USB interface designs using the FT245R compared to its FT245BM predecessor.
Enhanced Asynchronous Bit Bang Mode with RD# and WR# Strobes - The FT245R supports FTDI's BM chip bit
bang mode. In bit bang mode, the eight parallel FIFO data bus lines can be switched from the regular interface mode
to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the
interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT245R device this
mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be
used to allow external logic to be clocked by accesses to the bit bang I/O bus. This option will be described more fully
in a separate application note
Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the
interface pins are only read when the device is written to. Thus making it easier for the controlling program to measure
the response to an output stimulus as the data returned is synchronous to the output data. The feature was previously
seen in FTDI's FT2232C device. This option will be described more fully in a separate application note.
Lower Supply Voltage - Previous generations of the chip required 5V supply on the VCC pin. The FT245R will work
with a Vcc supply in the range 3.3V - 5V. Bus powered designs would still take their supply from the 5V on the USB
bus, but for self powered designs where only 3.3V is available, and there is no 5V supply, there is no longer any need
for an additional external regulator.
Integrated Level Converter on FIFO Interface and Control Signals - VCCIO pin supply can be from 1.8V to 5V.
Connecting the VCCIO pin to 1.8V, 2.8V, or 3.3V allows the device to directly interface to 1.8V, 2.8V or 3.3V and other
logic families without the need for external level converter I.C.s
5V / 3.3V / 2.8V / 1.8V Logic Interface - The FT245R provides true CMOS Drive Outputs and TTL level Inputs.
Integrated Power-On-Reset (POR) Circuit- The device incorporates an internal POR function. A RESET# pin is
available in order to allow external logic to reset the FT245R where required. However, for many applications the
RESET# pin can be left unconnected, or pulled up to VCCIO.
FT245R USB UART I.C. Datasheet Version 1.02
Future Technology Devices International Ltd. 2005
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Wake Up Function - If USB is in suspend mode, and remote wake up has been enabled in the internal EEPROM (it is
enabled by default), the RXF# pin becomes an input. Strobing this pin low will cause the FT245R to request a resume
from suspend on the USB bus. Normally this can be used to wake up the host PC from suspend
Lower Operating and Suspend Current - The device operating supply current has been further reduced to 15mA,
and the suspend current has been reduced to around 70A. This allows a greater margin for peripherals to meet the
USB suspend current limit of 500A.
Low USB Bandwidth Consumption - The operation of the USB interface to the FT245R has been designed to use
as little as possible of the total USB bandwidth available from the USB host controller.
High Output Drive Option - The parallel FIFO interface and the four FIFO handshake pins can be made to drive
out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a
greater signal drive strength to be interfaced to the FT245R. This option is configured in the internal EEPROM.
Power Management Control for USB Bus Powered, High Current Designs- The PWREN# signal can be used to
directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required.
An option in the internal EEPROM makes the device gently pull down on its FIFO interface lines when the power
is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is
removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored.
FTDIChip-IDTM - Each FT245R is assigned a unique number which is burnt into the device at manufacture. This ID
number cannot be reprogrammed by product manufacturers or end-users. This allows the possibility of using FT245R
based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the
FTDIChip-IDTM number when encrypted with other information. This encrypted number can be stored in the user area
of the FT245R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-IDTM to verify
that a license is valid. Web based applications can be used to maintain product licensing this way. An application note
describing this feature is available separately from the
FTDI website
.
Improved EMI Performance - The reduced operating current and improved on-chip VCC decoupling significantly
improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related specifications.
Programmable FIFO TX Buffer Timeout - The FIFO TX buffer timeout is used to flush remaining data from the
receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments from 1ms to 255ms,
thus allowing the device to be optimised for protocols that require fast response times from short data packets.
Extended Operating Temperature Range - The FT232R operates over an extended temperature range of -40 to
+85 C thus allowing the device to be used in automotive and industrial applications.
New Package Options - The FT245R is available in two packages - a compact 28 pin SSOP ( FT245RL) and an
ultra-compact 5mm x 5mm pinless QFN-32 package (
FT245RQ). Both packages are lead ( Pb ) free, and use a
`green' compound. Both packages are fully compliant with European Union directive 2002/95/EC.
FT245R USB UART I.C. Datasheet Version 1.02
Future Technology Devices International Ltd. 2005
Page 5
3. Block Diagram
3.1 Block Diagram (Simplified)
Figure 1 - FT245R Block Diagram
3.2 Functional Block Descriptions
3.3V LDO Regulator - The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver
cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It
also provides 3.3V power to the 1.5k internal pull up resistor on USBDP. The main function of this block is to power
the USB Transceiver and the Reset Generator Cells, rather than to power external logic. However, external circuitry
requiring 3.3V nominal at a current of around 50mA could also draw its power from the 3V3OUT pin if required.
USB Transceiver - The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal
USB series resistors on the USB data lines, and a 1.5k pull up resistor on USBDP.
USB DPLL - The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and
data signals to the SIE block.
Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4
Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and FIFO
controller blocks
Clock Multiplier - The Clock Multiplier takes the 12MHz input from the Oscillator Cell and generates the 48MHz clock
reference used for the USB DPLL block.
Serial Interface Engine (SIE) - The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to
Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / un-stuffing
and CRC5 / CRC16 generation / checking on the USB data stream.
Clock
Multiplier
Serial Interface
Engine
( SIE )
USB
Protocol Engine
3.3 Volt
LDO
Regulator
USB
Transceiver
with
Integrated
Series
Resistors
and 1.5K
Pull-up
USB DPLL
Internal
12MHz
Oscillator
48MHz
OCSI
(optional)
OSCO
(optional)
USBDP
USBDM
3V3OUT
VCC
D0
D1
D2
D3
D4
D5
D6
D7
RD#
RXF#
TXE#
RESET#
TEST
GND
RESET
GENERATOR
3V3OUT
WR
FIFO TX Buffer
FIFO RX Buffer
Internal
EEPROM
To USB Transceiver Cell
PWREN#
To USB
Transceiver
Cell
VCCIO
FIFO Controller
with
Programmable
High Drive
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