FT8U245AM
Future Technology Devices Intl. FT8U245AM Preliminary Information Rev 0.9 Subject to Change
USB FIFO - Fast Parallel Data Transfer IC
FEATURES
Single Chip Fast Data Transfer Solution
Send / Receive Data over USB at up to 1 M
Bytes / sec
384 byte FIFO Transmit buffer / 128 byte FIFO
receive buffer for high data throughput
Simple interface to CPU or MCU bus
No in-depth knowledge of USB required as all
USB Protocol is handled automatically within
the I.C.
FTDI's Virtual COM port drivers eliminate the
need for USB driver development in most
cases.
Compact 32 pin ( 7mm x 7mm ) MQFP package
Integrated 6MHz - 48MHz Clock Multiplier aids
FCC and CE compliance
Integrated 3.3v Regulator No External
Regulator Required
4.4v .. 5.25v Single Supply Operation
UHCI / OHCI Compliant
USB 1.1 Specification Compliant
USB VID, PID, Serial Number and Product
Description Strings in external E2PROM.
Virtual COM Port Drivers for
Windows 98 and Windows 98 SE
Windows 2000
Windows Millennium **
Apple iMAC **
Linux **
Application Areas
USB ISDN and ADSL Modems
High Speed USB
PDA Communications
USB I/F for Digital Cameras
USB I/F for MP3 players
High Speed USB Instrumentation
USB
USB data transfer cables
USB
USB null-modem cables
GENERAL DESCRIPTION
The FT8U245AM provides an easy cost-effective method of transferring data to / from a peripheral and a
host P.C. at up to 8 Million bits ( 1 Megabyte ) per second. It's simple FIFO-like design makes it easy to interface
to any CPU ( MCU ) either by mapping the device into the Memory / IO map of the CPU, using DMA or controlling
the device via IO ports.
To send data from the peripheral to the host P.C. simply write the byte wide data into the device when the
transmitter empty status bit is not active. If the ( 384 byte ) transmit buffer fills up, the device de-asserts
transmit empty in order to stop further data being written to the device until some of the FIFO data has been
transferred over USB.
When the host P.C. sends data to the peripheral over USB, the device will assert the receiver full status
bit to let the peripheral know that data is available. The peripheral then reads the data until the receiver full
status bit goes inactive, indicating no more data is available to read.
By using FTDI's virtual COM Port drivers, the peripheral looks like a standard COM Port to the application
software. Commands to set the baud rate are ignored the device always transfers data at it's fastest rate
regardless of the application's baud rate setting.
Future Technology Devices Intl. FT8U245AM Preliminary Information Rev 0.9 Subject to Change
Figure 1 FT8U245AM Block Diagram ( Simplified )
Figure 2 FT8U245AM I.C. Pinout
x8 Clock
Multiplier
Serial Interface
Engine
( SIE )
USB
Protocol Engine
FIFO Transmit
Buffer
384 Bytes
FIFO Receive
Buffer
128 Bytes
3.3 Volt
LDO
Regulator
USB
Transceiver
USB DPLL
6MHZ
Oscillator
48MHz
12MHz
XTIN
XTOUT
USBDP
USBDM
3V3OUT
VCC
RCCLK
RESET#
TEST
GND
FIFO
Controller
D0
D1
D2
D3
D4
D5
D6
D7
EEPROM
Interface
RD#
WR
EEREQ#
EEGNT#
EECS
EESK
EEDATA
RXF#
TXE#
EESK
EEDATA
VCC
RESET#
TEST
3V3OUT
USBDP
USBDM
GND
EEGNT#
EEREQ#
RXF#
TXE#
WR
RD#
VCC
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
XTOUT
XTIN
AGND
AVCC
RCCLK
EECS
1
8
9
16
17
24
25
32
FT245AM
XXYY
FTDI
Future Technology Devices Intl. FT8U245AM Preliminary Information Rev 0.9 Subject to Change
FT8U245AM - FUNCTIONAL BLOCK DESCRIPTION
3.3V LDO Regulator
The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell
output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator
output pin.
USB Transceiver
The USB Transceiver Cell provides the USB 1.1 full-speed physical interface to the USB cable. The
output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection.
USB DPLL
The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and
data signals to the SIE block.
6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz reference clock input to the X8 Clock multiplier from an
external 6MHz crystal or ceramic resonator.
X8 Clock Multiplier
The X8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference
clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz
reference clock for the USB DPPL and the Baud Rate Generator blocks.
Serial Interface Engine ( SIE )
The Serial Interface Engine ( SIE ) block performs the Parallel to Serial and Serial to Parallel conversion
of the USB data. In accordance to the USB 1.1 specification, it performs bit stuffing / un-stuffing and
CRC5 / CRC16 generation / checking on the USB data stream.
USB Protocol Engine
The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the
low level USB protocol ( Chapter 9 ) requests generated by the USB host controller and the commands
for controlling the functional parameters of the UART.
Fifo Receive Buffer ( 128 bytes )
Data sent from the USB Host to the FIFO via the USB data out endpoint is stored in the FIFO Receive
Buffer and is removed from the buffer by reading the FIFO contents using RD#.
Future Technology Devices Intl. FT8U245AM Preliminary Information Rev 0.9 Subject to Change
FIFO Transmit Buffer ( 384 bytes )
Data written into the FIFO using WR# is stored in the FIFO Transmit Buffer. The Host removes Data
from the FIFO Transmit Data by sending a USB request for data from the device data in endpoint.
FIFO Controller
The FIFO Controller handles the transfer of data between the external FIFO interface pins and the FIFO
Transmit and Receive buffers.
EEPROM Interface
The FT8U245AM uses an external 93C46 EEPROM to customise the USB VID, PID, Serial Number and
Strings of the FT8U245AM for OEM applications. The FT8U245 Virtual Com Port Drivers rely on a unique
device serial number for to bind a unique virtual COM port to each individual device.
Future Technology Devices Intl. FT8U245AM Preliminary Information Rev 0.9 Subject to Change
Table 1 - FT8U245AM - PINOUT DESCRIPTION
Pin #
Signal
Type
Description
7
USBDP
I/O
USB Data Signal Plus Requires 1.5k pull-up to 3V3OUT
8
USBDM
I/O
USB Data Signal Minus
6
3V3OUT
OUT
3.3 volt Output from integrated regulator
27
XTIN
IN
Input to 6MHz Crystal Oscillator Cell
28
XTOUT
OUT
Output from 6MHz Crystal Oscillator Cell
31
RCCLK
I/O
RC timer used to guarantee clock stability on exiting sleep
mode. Clamped low during reset or sleep condition.
4
RESET#
IN
Resets entire device using external RC network
32
EECS
I/O
Optional EEPROM Chip Select
1
EESK
I/O
Optional EEPROM Clock
2
EEDATA
I/O
Optional EEPROM Data I/O
5
TEST
IN
Puts device in i.c. test mode must be tied to GND
25
D0
I/O
Bi-directional Data Bus Bit # 0
24
D1
I/O
Bi-directional Data Bus Bit # 1
23
D2
I/O
Bi-directional Data Bus Bit # 2
22
D3
I/O
Bi-directional Data Bus Bit # 3
21
D4
I/O
Bi-directional Data Bus Bit # 4
20
D5
I/O
Bi-directional Data Bus Bit # 5
19
D6
I/O
Bi-directional Data Bus Bit # 6
18
D7
I/O
Bi-directional Data Bus Bit # 7
16
RD#
IN
Enables Current FIFO Data Byte on D0..D7.when low.
Fetches the next FIFO Data Byte ( if available ) from the
Receive FIFO Buffer when RD# goes from low to high.
15
WR
IN
Writes the Data Byte on the D0..D7 into the Transmit FIFO
Buffer when WR goes from high to low.
14
TXE#
OUT
When high, do not write data into the FIFO. When low, data can
be written into the FIFO by strobing WR high then low.
12
RXF#
OUT
When high, do not read data from the FIFO. When low, there is
data available in the FIFO which can be read by strobing RD#
low then high again.
11
EEREQ#
IN
Requests the EEPROM contents to be accessed via the Data
Bus.
10
EEGNT#
OUT
When low, allows the EEPROM contents to be accessed via the
Data Bus.
3,13,26
VCC
PWR
Device - +4.4 volt to +5.25 volt Power Supply Pins
9.17
GND
PWR
Device Ground Supply Pins
30
AVCC
PWR
Device - Analog Power Supply for the internal x8 clock multiplier
29
AGND
PWR
Device - Analog Ground Supply for the internal x8 clock
multiplier
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