DS06-10801-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
AccelArray
TM
CA91 Series
DESCRIPTION
AccelArray
TM
* is a new structured ASIC family, offering short development time, and low development cost with
pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.
By using 0.11
m CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM
and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins)
packages are available.
* : AccelArray
TM
is a trademark of Fujitsu Limited.
FEATURES
High-speed, large scale ASIC produced in short development time:
TAT = One third compared with Standard Cell ASICs (target value)
Uses an architecture that simplifies physical design tasks.
Pre-designed common masters with IR-drop free.
Pre-designed test circuit insertion to reduce test synthesis tasks.
Uses a dedicated timing-driven layout tool to reduce development time.
Signal Integrity Free (pre-designed main clock trees without design verifications)
Max built-in gate number : 6,000,000 gates or more
Technology : 0.11
m Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
Internal cells support high-speed operation
Power supply voltage : +1.2 V 0.1 V/2.5 V
0.2 V (Dual power supply. Needs 1.5 V power supply during using
HTSL.) .
Operation junction temperature :
-
40
C to
+
125
C (standard)
Max operating frequency: 333 MHz (internal circuit)
Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
Embedded macro : PLL, SRAM
8-channel clock supply system incorporating a PLL
Supports Memory-BIST/Boundary-SCAN
Package : FC-BGA (729 pins to 1681 pins)
ARM core is supported.
Note : It contains under planning.
CA91 Series
2
MACRO LIBRARY
1.
Unit cell
Flip Flop, with clear/preset (support for Mux-D Scan, with Lock up latch)
Clock Buffer
Other combination circuits (approximately 50 different types)
2.
APLL
Input frequency
: 25 MHz to 800 MHz
Output frequency : 400 MHz to 800 MHz
User frequency
: 25 MHz to 800 MHz
Phase shift
: 0/90/180/270 deg.
3.
SRAM
1R1W-SRAM : 32 words
40 bits
2RW-SRAM : 512 words
40 bits
Bit Select 1 : 1, 2 : 1, 4 : 1, 8 : 1
1 RW operation accesses specified port bit-width
4.
I/O
HSTL *
1
(250 MHz)
2.5 V LVCMOS
(200 MHz (input buffer), 75 MHz to 100 MHz (output buffer))
PCML
(250 MHz)
LVDS
(311 MHz)
SSTL2
(250 MHz)
PCI-66 *
2
(66 MHz)
PCI-X *
2
(133 MHz)
3.3 V tolerant
(200 MHz (input buffer), 75 MHz to 100 MHz (output buffer))
*1 : Needs 1.5 V power supply
*2 : As the I/F is 3.3V tolerant, it does not satisfy the PCI standard in some cases.
Dedicated for Giga Frame
SPI-4P2
(622 Mbps to 800 Mbps)
XAUI
(3.125 Gbps)
Fibre Channel
(1.0 Gbps, 2.0 Gbps)
Serial Rapid IO
(1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
PCI Express
(2.5 Gbps)
5.
Memory interface
DDR-SDRAM
(400 Mbps)
QDR-SDRAM
(400 Mbps)
Peer to Peer SDR (200 Mbps)
Peer to Peer DDR (200 Mbps)
SDR-SDRAM
(167 Mbps)
CA91 Series
3
ABSOLUTE MAXIMUM RATINGS
(VSS
=
0 V)
*1 : Different limit values apply for LVDS, etc.
*2 : Maximum supply current in normal operation. Supply current depends on the frame or the package.
*3 : Maximum output current in normal operation
*4 : Required when using HSTL I/O.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter
Symbol
Application
Rating
Unit
Min
Max
Power supply
voltage
VDD
VDDI (Core)
-
0.5
1.8
V
VDDE
(for 2.5 V CMOS I/Os, 3.3 V Tolerant I/Os)
-
0.5
3.6
V
VDDE (for 1.5 V I/Os*
4
)
-
0.5
3.6
V
Input voltage *
1
VI
2.5 V CMOS
-
0.5
VDDE
+
0.5
(
3.6)
V
3.3 V Tolerant
-
0.5
VDDE
+
3.6
(
4.0)
V
Output voltage
VO
2.5 V CMOS
-
0.5
VDDE
+
0.5
(
3.6)
V
3.3 V Tolerant (H/L-State)
-
0.5
VDDE
+
0.5
(
4.0)
V
3.3 V Tolerant (Z-State)
-
0.5
4.0
V
Storage
temperature
Tst
-
55
+
125
C
Operation
junction
temperature
Tj
-
40
+
125
C
Power supply
pin current *
2
ID
Each VDDE pin
180
mA
Each VDDI pin
200
mA
Each VSS pin
200
mA
Output current *
3
IO
2.5 V CMOS
10
mA
3.3 V Tolerant
7.5
mA
CA91 Series
4
RECOMMENDED OPERATING CONDITIONS
Dual power supply (VDDI
=
+
1.2 V
0.1 V, VDDE
=
+
2.5 V
0.2 V, (
+
1.5 V
0.1 V))
(VSS
=
0 V)
* : Applicable to HSTL I/O.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Value
Unit
Min
Typ
Max
Power supply
voltage
Power supply voltage
for core
VDDI
1.1
1.2
1.3
V
Power supply voltage
for 2.5 V I/Os
VDDE
2.3
2.5
2.7
V
Power supply voltage
for 1.5 V I/Os *
VDDE
1.4
1.5
1.6
V
"H" level input
voltage
2.5 V CMOS
VIH
1.7
VDDE
+
0.3
V
3.3 V Tolerant
1.7
3.6
V
"L" level input
voltage
2.5 V CMOS
VIL
-
0.3
0.7
V
3.3 V Tolerant
-
0.3
0.7
V
Operation junction temperature
Tj
-
40
+
125
C
CA91 Series
5
ELECTRICAL CHARACTERISTICS
1.
DC CHARACTERISTICS
(VDDI
=
1.2 V
0.1 V, VDDE
=
2.5 V
0.2 V, VSS
=
0 V, Tj
=
-
40
C to
+
125
C)
* : The input leak current may exceed the above value if an input buffer with pull-up or pull-down resistor is used.
Note : Refer to the application note for details of HSTL I/O.
2.
AC CHARACTERISTICS
*1 : Delay time = propagation delay time, enable time, and disable time.
*2 : typ can be estimated from the cell specification.
*3 : Measurement condition
Note : Obtains the tpd max corresponding to the maximum junction temperature Tj.
I/O PIN CAPACITANCE
(Tj
=
+
25
C, VDDE
=
VI
=
0 V, f
=
1 MHz)
Note
: The capacity depends on the package, pin positions, and similar.
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
"H" level output voltage
VOH
IOH
=
-
100
A
VDDE
-
0.2
VDDE
V
"L" level output voltage
VOL
IOL
=
100
A
0
0.2
V
Input leak current *
IL
-
10
+
10
A
Pull-up/Pull-down
resistor
RP
2.5 V CMOS pin,
VIL = 0 V at pull-up,
VIH = VDDE at pull-down
10
25
55
k
3.3 V Tolerant pin,
VIH = 3.0 V to 3.6 V at pull-down
12
33
85
k
Parameter
Symbol
Value
Unit
Min
Typ
Max
Delay time
tpd *
1
typ *
2
tmin *
3
typ *
2
ttyp *
3
typ *
2
tmax *
3
ns
Measurement condition
tmin
ttyp
tmax
VDD
=
1.2 V
0.1 V, VSS
=
0 V, Tj
=
-
40
C to
+
125
C
0.73
1.00
1.43
Parameter
Symbol
Value
Unit
Input pin
CIN
Max 16
pF
Output pin
COUT
Max 16
pF
I/O pin
CI/O
Max 16
pF
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