CE66 Series Embedded Array

0.35µm CMOS Technology

Features

Description

Embedded

Hard

Macro

Fixed

Layout

Soft Macro

Fixed

Layout

Soft Macro

Clock Tree

Clk

5V I/O
5V I/O
5V I/O
5V I/O
5V I/O
3V I/O
3V I/O
3V I/O
PCML
3V I/O
3V I/O
5V I/O
5V I/O
5V I/O
5V I/O
5V I/O

· 0.28µm L

eff

(0.34µm drawn)

· Propagation delay of 98 ps

· Mixed-signal macros: A/D and D/A converters

· High-density diffused RAMs and ROMs

· Separate core and I/O supply voltages

· I/Os: 5V, 3.3V, 5V tolerant

· Core power supply voltage: 3.3V, 2.5V~2.0V

· Junction temperature: -40ºC~125ºC

· Special I/Os: PCI, I

C, USB

· Analog and digital PLLs

· Packaging options: QFP, HQFP, LQFP, TQFP, PBGA,FBGA

· Support for major third party EDA tools

Fujitsu's CE66 is a series of high-performance, CMOS

embedded arrays featuring mixed-signal macros, diffused

high-speed RAMs, ROMs, and a variety of other embedded

functions. The CE66 series combines the density and

performance of standard cells with the time-to-market

advantage of gate arrays. In addition, the I/Os, operating

at 5V, 3.3V, and 5V tolerant conditions, are designed to

provide cost-effective solutions for both core-limited and

pad-limited designs. The CE66 series features a very low

power consumption of 0.29µW/gate/MHz at 3.3V. Potential

applications for the CE66 series include the consumer

market, communications, and networking designs.

P-Series with 100µm Inline Pad Pitch

Frame

Total Gates

Total Pads

Signals

CE66P1

188K

144

126

CE66P2

233K

160

138

CE66P3

283K

176

132

CE66P4

337K

192

152

CE66P5

396K

208

178

CE66P6

427K

216

178

CE66P7

460K

224

178

CE66P8

528K

240

206

CE66P9

602K

256

228

CE66PA

680K

272

228

CE66PB

761K

288

228

CE66PC

847K

304

264

CE66PD

940K

320

264

CE66PE

1037K

336

264

CE66PF

1138K

352

312

S-Series with 70µm Inline Pad Pitch

Frame

Total Gates

Total Pads

Signals

CE66S1

91K

144

126

CE66S2

113K

160

138

CE66S3

137K

176

152

CE66S4

164K

192

160

CE66S5

207K

216

178

CE66S6

256K

240

193

CE66S7

311K

264

228

CE66S8

391K

296

248

CE66S9

481K

328

248

CE66SA

580K

360

312

Mixed-Signal Macros
D/A Converters

· 8-bit: 220 MHz (video)

· 8-bit: 50 MHz (video)

· 8-bit: 1.5 MHz (general purpose)

· 10-bit: 30 MHz (general purpose)

· 10-bit: 1.5 MHz (general purpose)

A/D Converters

· 6-bit: 300 MHz (disk)

· 8-bit: 50 MHz (video)

· 10-bit: 20 MHz (general purpose)

· 10-bit: 1 MHz (general purpose)
Multiplier Compiler
· Multiplicand (m): 4 < m < 32

· Multiplier (n): 4 < n < 32 (even numbers only)
Memory Macros
· SRAM Compiler: single and dual port (1 R/W, 1R),

up to 72K bits per block, partial write option

· ROM Compiler: up to 512K bits per block

· Delay line: up to 32K bits
Phase-Locked Loops
· Analog: 50-200 MHz

· Digital: 180-360 MHz (Preliminary)
I/Os
· 3.3V, 5V, and 5V tolerant

· Slew-rate controlled

· CMOS, TTL, LVTTL, T-LVTTL, SDRAM I/F,

PCI, I

C, USB

SOC IP Cores
ARC 32-bit RISC

832/833/835 SPARClite Hard Macros

Oak DSP Hard Macro

10/100 MAC

64/256 QAM

MPEG2 Decoder/Demultiplexer

8VSB TV Demodulator

AC-3 Dolby Voice Decoder

JPEG Encoder and Decoder

PCI33/66 MHz, 32/64-bit cores

USB Host Controller/Device

IDE (ATA3) Host Controller

Smart Card I/F

IRDA I/R Interface

More IPs are being added

ASIC Design Kit and EDA Support

Verilog Logic Simulators from

Verilog-XL, NC-Verilog,

Cadence, Synopsys, and Mentor

VCS, Model-sim (Verilog)

VHDL/VITAL Logic

VSS, Model-sim (VHDL), V-System,

Simulators from Synopsys,

Leapfrog

Cadence, and Mentor
Synthesis, DFT, and STA tools

Design Compiler, Test Compiler,

from Synopsys

PrimeTime, MOTIVE, and

Sunrise TestGen

Other EDA tools

Chrysalis Design Verifyer

PACKAGE AVAILABILITY

No. of Pins

Frame Size

TQFP
100