DS04-21361-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F07SL
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DESCRIPTION
The Fujitsu MB15F07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with two 1100 MHz
prescalers. The two 1100 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65 enabling pulse
swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15F07SL uses the latest BiCMOS process. As a result,
the supply current is typically 5 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5
mA or 6 mA. The charge pump current is selectable by serial data.
MB15F07SL is ideally suited for wireless mobile communications, such as GSM and PDC.
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FEATURES
High frequency operation: PLL 1, 2: 1100 MHz max
Low power supply voltage: V
CC
= 2.4 to 3.6 V
Ultra Low power supply current: I
CC
= 5.0 mA typ. (V
CC
= 2.7 V, Ta = +25
C, in PLL1, 2 locking state)
I
CC
= 5.5 mA typ. (V
CC
= 3.0 V, Ta = +25
C, in PLL1, 2 locking state)
Direct power saving function: Power supply current in power saving mode
Typ. 0.1
A (V
CC
= 3.0 V, Ta = +25
C), Max. 10
A (V
CC
= 3.0 V)
Dual modulus prescaler: 1100 MHz prescaler (64/65, 128/129)
Serial input 14-bit programmable reference divider: R = 3 to 16,383
Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
Software selectable charge pump current
On-chip phase control for phase comparator
Operating temperature: Ta = 40 to +85
C
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PACKAGES
16-pin plastic SSOP
(FPT-16P-M05)
16-pad plastic BCC
(LCC-16P-M04)
3
MB15F07SL
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PIN DESCRIPTIONS
Pin no.
Pin
name
I/O
Descriptions
SSOP-16 BCC-16
1
16
GND
2
Ground for PLL 2 section.
2
1
OSC
IN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GND
1
Ground for the PLL 1 section.
4
3
fin
1
I
Prescaler input pin for the PLL 1.
Connection to an external VCO should be via AC coupling.
5
4
V
CC1
Power supply voltage input pin for the PLL 1 section.
6
5
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in a serial data.
LDS bit = "H" ; outputs fout signal
LDS bit = "L" ; outputs LD signal
7
6
PS
1
I
Power saving mode control for the PLL 1 section. This pin must be set
at "L" during Power-ON. (Open is prohibited.)
PS
1
= "H" ; Normal mode
PS
1
= "L" ; Power saving mode
8
7
Do
1
O
Charge pump output for the PLL 1 section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
Do
2
O
Charge pump output for the PLL 2 section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PS
2
I
Power saving mode control for the PLL 2 section. This pin must be set
at "L" during Power-ON. (Open is prohibited.)
PS
2
= "H" ; Normal mode
PS
2
= "L" ; Power saving mode
11
10
Xfin
2
I
Prescaler complementary input for the PLL 2 section.
This pin should be grounded via a capacitor.
12
11
V
CC2
Power supply voltage input pin for the PLL 2 section, the shift register and
the oscillator input buffer. When power is OFF, latched data of PLL 2 is lost.
13
12
fin
2
I
Prescaler input pin for the PLL 2.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set "H", data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (PLL 1-ref counter, PLL 1-
prog. counter, PLL 2-ref. counter, PLL 2-prog. counter) according to the
control bit in the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
5
MB15F07SL
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ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Remark
Min.
Max.
Power supply voltage
V
CC
0.5
+4.0
V
Input voltage
V
I
0.5
V
CC
+0.5
V
Output voltage
V
O
GND
V
CC
V
Storage temperature
Tstg
55
+125
C
Parameter
Symbol
Value
Unit
Remark
Min.
Typ.
Max.
Power supply voltage
V
CC
2.4
3.0
3.6
V
Input voltage
V
I
GND
V
CC
V
Operating temperature
Ta
40
+85
C
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