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Электронный компонент: MB86342B

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DS04-26903-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
CMOS
Dolby Digital (AC-3) Decoder LSI
MB86342B
s
DESCRIPTION
Dolby Digital (AC-3) is a perceptual digital audio coding technique of unprecedented efficiency, quality and
versatility.
Fujitsu has developed Dolby Digital (AC-3) 5.1-ch full decodable LSI.
This LSI is certificated as " Dolby Digital (AC-3) Decoder LSI " by Dolby Laboratories Licensing Corporation.
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FEATURES
Dolby Digital (AC-3) 5.1ch Full Decode
All bit-rate and All sampling frequency
Down Mix
Dialog Normalization
Dynamic-range Compression
Noise sequencer (Test tone)
Each channel can be independently set
Output Bass Management (config-1, 2, 3)
Dolby Pro Logic Decode
Dolby Digital (AC-3) + Dolby Pro Logic Decode
16/18/20bit Audio Data Input/Output
(Continued)
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PACKAGE
Note: Dolby, AC-3, Pro Logic and double-D are trademarks of Dolby Laboratories Licensing Corporation.
(FPT-100P-M06)
100-pin Plastic QFP
2
MB86342B
(Continued)
Operat with only audio system clock (384fs) by built-in PLL
Correct with ADC,DAC,DIR and DIT with type audio I/F three lines
Control by Host I/F
3.0V to 3.6V operation
QFP-100 pin package
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PIN ASSIGNMENT
D08
D07
V
DD
V
SS
D06
D05
D04
D03
D02
V
SS
D01
D00
ICCLK
ICBRK
ICD1
ICD0
ICS2
ICS1
ICS0
V
SS
A14
A15
WE
CS
MOD
BST
HDOUT
HDIN
HCS
HCLK
V
SS
GP0
GP1
GP2
GP3
GP4
V
SS
V
DD
GP5
GP6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
D09
V
SS
V
DD
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
A00
A01
V
SS
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
V
SS
V
DD
A12
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
XRST
EXTIN
V
DD
V
SS
MCLK1
MCLK2
KFSIO
SCKO
PM
PSTOP
EXLOCK
MS
FS1
FS2
V
SS
SYNC
LRCKI1
BCKI1
SDI1
LRCKI2
BCKI2
SDI2
LRCKO
BCKO
SDO1
SDO2
SDO3
V
DD
V
SS
GP7
(Top view)
(FPT-100P- M06)
3
MB86342B
s
PIN DESCRIPTION
Pin No.
Pin name
I/O
Function
5
MCLK1
I
Clock input
6
MCLK2
I/O
Clock input/output
1
XRST
I
Reset signal input
8
SCKO
O
System clock output
12
MS
I
Master/Slave select input
L: Master (X'tal) H:Slave (external clock)
16
SYNC
I
Synchronous/Asynchronous select input
2
EXTIN
I
System clock input (384fs)
13, 14
FS1, FS2
I
Sampling frequency switching signal input
7
KFSIO
I/O
Audio input/output clock (384fs)
9
PM
I
Test pin (usually clipped to GND)
10
PSTOP
I
PLL and crystal oscillator control signal
11
EXLOCK
I
Lock signal input of EXTIN
41
HCLK
I
Clock input for serial input-data of host interface
43
HDIN
I
Serial data input of host interface
44
HDOUT
O
Serial data output of host interface
42
HCS
I
Chip-select signal input of host interface
45
BST
I
Usually clipped to GND
30 to 32, 35 to 39
GP0 to GP7
I/O
Input/output of 8-bit general port data
17
LRCKI1
I/O
Sampling clock input/output for audio interface serial data
18
BCKI1
I/O
Bit clock input/output for audio interface serial data
20
LRCKI2
I
Sampling clock input for audio interface serial data
21
BCKI2
I
Bit clock input for audio interface serial data
19, 22
SD1, SD2
I
Serial data input of audio interface
23
LRCKO
O
Sampling clock output for audio interface serial data
24
BCKO
O
Bit clock output for audio interface serial data
25 to 27
SDO1 to SDO3
O
Serial data output of audio interface
46
MOD
I
Bus-mode control signal input
47
CS
O
Chip-select signal output for external SRAM interface
48
WE
O
Write enable signal output for external SRAM interface
49 to 52, 55 to 64, 66, 67 A00 to A15
O
Address data output of external SRAM interface
68 to 77,80 to 82
85 to 89, 91, 92
D00 to D19
I/O
Data input/output of external SRAM interface
93
ICCLK
O
Clock output for emulator
94
ICBRK
I
External break control signal input for emulator
95, 96
ICD0, ICD1
I/O
Input/output signal for data/address of emulator
97 to 99
ICS0 to ICS2
O
Status signal output for emulator
4
MB86342B
s
BLOCK DIAGRAM
MCORE
MEM
MCLK1
XRST
MS
KFSIO
PSTOP
SYNC
LRCKI2,LRCKI1
SDI2,SDI1
BCKO
HCLK
HDOUT
BST
MOD
WE
D19 to 00
ICBRK
ICS2 to 0
GP7 to 0
MCLK2
SCKO
EXTLN
PM
FS2,FS1
EXLOCK
BCKI2,BCKI1
LRCKO
SDO3 to 0
HDIN
HCS
CS
A15 to 00
ICCLK
ICD1,ICD0
B-bus
A-bus
P-bus
CLKGM
ADIF
HISF
GP
EXMIF
EMUIF
LOG
5
MB86342B
s
FUNCTION OF EACH BLOCK
MCORE : MUCAP Core
MUCAP Core is a 20-bit fixed point DSP core. This core operates MOVE, BRANCH,
INTERRUPT, ADDRESSING and ARITHMETIC operations.
CLKGM : Clock Generation Module
This module generates internal and external clock. two type of clocks are generated external
clocks and clock from external crystal oscillator.
ADIF
: Audio Interface Module
This module is an interface of input/output serial audio data to external.
2-channels of input port, and 3-channel of output port.
2-audio data input registers and 6-output registers ( 20-bit ).
HSTIF
: Host Interface Module
This module transfers asynchronous serial data to host CPU, which has input data register and
output data register(20-bit).
GP
: General Port Module
This module has a 8-bit direction register and 8-bit data register. Each port is independent as
a 1pin input/output general port(total 8pins).
EXMIF
: External Memory Interface Module
This module reads and writes data to external memory(SRAM), which has 3-byte data read/
write mode and 1word(20bit) data read/write mode.
This module uses in-service-register in order to read and write 3-byte data.
EMUIF
: Emulator Interface Module
This module is used for in circuit emulation.
LOG
: LOG Module
This module has registers to refer to table data for the operation of logarithmic functions.
MEM
: Memory Module
This module restores data and programs.