DS04-22002-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP Communication Control
IEEE 1394 Bus Controller
(for DVC)
MB86615
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DESCRIPTION
The MB86615 is 1394 serial bus controller compatible with the IEEE 1394 "FireWire" standard (IEEE Standard
1394-1995). One built-in port plus a differential transceiver and comparator are provided to enable formation of
networks in a 1394 cable environment. The MB86615 supports s100 data transfer speeds.
By integrating the physical layer and link layer on one chip, The MB86615 is designed to reduce mounting area
as well as power consumption.
The MB86615 has an exclusive data port for isochronous transfer, provides automatic packetizing for sending
and separation of header and data units at receiving, and is optimized for continuity of transfer processing.
The MB86615 supports DVC AV/C protocols, and includes the necessary built-in automatic operations and
CSR's for providing the necessary operations for DVC data transfer.
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FEATURES
Compatible with IEEE 1394 high-performance serial bus standards
Physical layer and link layer integrated on one chip
1 cable ports
Supports s100 transfer speed (98.304 Mbit/sec)
3.3V single power supply operation
Built-in PLL (for crystal oscillator) for internal clock signal generation
Power saving modes
1) Forced sleep mode at instruction from MPU
2) Automatic sleep mode for non-connected ports
Header and data units automatically separated at receiving and automatic packetizing for sending
Supports cycle master functions
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PACKAGES
100-pin plastic LQFP
(FPT-100P-M05)
120-pin plastic FBGA
(BGA-120P-M01)
2
MB86615
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Built-in CSR's to provide isochronous resource manager functions
32-bit CRC generation and check functions
General purpose port for asynchronous transfer and control (16-bit MPU/DMA common bus)
Exclusive built-in ports for isochronous transfer (8-bit bus)
Built-in CRS's and automatic processes to support DVC
1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending.
2) Automatic generation and match detection of time stamp by FP signal.
3) DBC area automatic increment function
4) No-data packet sending and receiving
5) On-chip PCR (input/output 1 channel each)
6) Each CSR with automatic C&S lock processing and read processing
Compatible with 4-core cable
Packages: LQFP-100, FBGA-120
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