MB86695

FireStreamTM50

ATM 52 Mbps SAR Device

Page 1 of 7

Product Flyer

April 2000

Version 1.0

FML/NPD/FS50/FL/2359

FireStreamTM5

ATM 52 Mbps SAR Device

MB86695

The FireStream50 is a low cost ATM protocol controller
which autonomously terminates ATM Adaptation Layer
standard Type 5 (AAL5). ATM cells are received through a
UTOPIA

v2.01

compliant

interface.

Simultaneous

segmentation and reassembly can be achieved at an
average rate in excess of 52Mbps.

The device contains embedded memory to support 32
virtual circuits (VCs).

All ATM Forum traffic classes (ABR, VBR, CBR, UBR) are
supported with traffic management to ATM Forum TM4.0
specification for all 32 VCs.

The FireStream50 is ideally suited to many ATM
applications including ATM switches, home gateways,
integrated access devices, set-top boxes, routers and
adaptor cards.

Features

Broadband ISDN Adaptation Layer standard Type 5 (AAL5)

Simultaneous segmentation and reassembly on up to 32VCs

ABR, VBR, CBR and UBR traffic classes with traffic management compliant to TM4.0

Autonomous Resource Management (RM) cell handling

33MHz 32-bit PCI (v2.1) interface supporting the 3.3V signalling environment, and tolerant to 5V

Write-only interface for PDU handling with copy of SAR registers maintained in host memory

Configuration through PCI slave port, PCI configuration optionally through serial EEPROM

Support for scatter/gather mode

Transparent ATM cell and cell payload modes (AAL0) with support for Operations and
Maintenance (OAM) cells

8 bit, up to 52MHz UTOPIA v2.01 level1/2 compliant cell stream interface with master/slave
modes and optional HEC checking on receive

Embedded memory, no external memory requirement

16 bit Peripheral interface

JTAG compliant to IEEE1149.1

Fabricated in CMOS technology with CMOS/TTL compatible 5V tolerant I/O

-40

C to +85

C Industrial temperature range

PLASTIC PACKAGE

SQFP208

April 2000 Version 1.0

FML/NPD/FS50/FL/2359

MB86695 FireStreamTM50 ATM 52 Mbps SAR Device

Page 2 of 7

Figure 1 FireStream50 block diagram

General

A top level logic diagram of the FireStream50 is shown in Figure 1. The FireStream50
simultaneously supports autonomous segmentation and reassembly of user data packets on up to
32 virtual circuits (VCs). User data packets are transferred to and from shared data structure memory
using a high speed 32-bit PCI bus and transferred to and from the network using an 8-bit UTOPIA
interface.

High

Speed

DMA

Controller

ATM

Cell

Input

ATM

Cell

Output

Cell Input

Buffer

(3Cells)

Receive

Buffer

(24 Cells)

Reassembly and

Convergence

Sub-layer

Controller

Cell Output

Buffer

(3 Cells)

Transmit

Buffer

(4 Cells)

Segmentation

and

Convergence

Sub-layer

Controller

Local

Memory

Controller

JTAG

Traffic

Management

Controller

Internal

Registers

JTAG Interface

Peripheral Interface

Host Interf

ace (PCI)

UT
OPIA Interf

ace

Serial EEPROM Interface

Internal

RAM

April 2000 Version 1.0

FML/NPD/FS50/FL/2359

MB86695 FireStreamTM50 ATM 52 Mbps SAR Device

Page 3 of 7

Adaptation Layer Support

The FireStream50 autonomously terminates the protocols involved in segmenting and reassem-
bling data streams conforming to ATM Adaptation Layer (AAL) Type 5 to I.363. Streaming and Mes-
sage Modes as defined for AAL5 are supported. In Message Mode, the Convergence Sublayer
payload (Service Data Unit) is considered to be the user data transmitted from or received into a
single entity - a single entity being regarded as one user data buffer or linked chain of user data buff-
ers. In Streaming Mode, the Convergence Sublayer payload is considered to be the user data trans-
mitted from or received into multiple entities separated in time. This allows a partial segmentation or
reassembly. The device recognises OAM and RM cells and separates them from the data stream.
The FireStream50 device supports two transparent modes (AAL0) with optional CRC-10 genera-
tion and checking. In transparent payload mode the 48 byte ATM cell payload is received or trans-
mitted transparently into or from SAR Memory. In transparent cell mode the complete ATM cell,
excluding the HEC, is received or transmitted transparently into or from SAR Memory.

Traffic Shaping

The FireStream50 supports autonomous traffic shaping functions for ABR, VBR, UBR and CBR
traffic. Traffic parameters are stored on a per-circuit basis in internal memory. A calendar algorithm
is used for traffic scheduling and has four priority levels which are independent of traffic type. ABR
support includes autonomous handling of RM cells. Transmitted FRM cells are dropped into the data
stream at the correct rate. Received BRM cells modify the associated VC's traffic parameters.
Received FRM cells are stored locally and automatically rescheduled for transmission.

Embedded Memory

Control structures are initialised by the host and then copied by the FireStream50 into internal
memory. These include circuit information such as VP/VC values and descriptor information such as
data pointers and buffer lengths. The FireStream50 then works on the local copy of these structures
and hence does not consume any further system bandwidth. The internal memory also contains
static and dynamic traffic parameters and pointers for the traffic scheduling algorithm.

Cell Stream Interface

The FireStream50 interfaces via a standard UTOPIA level 1 or level 2 interface. This 8-bit interface
which operates at up to 52MHz can be configured as an ATM or a PHY (master or slave) device
depending on the application. The HEC is inserted on transmit and checked on receive. A 52-byte
cell option is provided where the HEC is omitted.

PCI Master Interface

The FireStream50 has a high performance 32-bit PCI master interface, conforming to v2.1 of the PCI
specification. The programming interface has a "write-only" mode which minimizes PCI bus
occupancy by removing the need for the Host to make slave read accesses.

PCI Slave Interface

A simple PCI slave control/status port is used to configure the device. Its function includes the
Initialisation of the queue structures and the monitoring of cell and packet loss. An interrupt
mechanism is implemented to indicate queue updates and exception conditions.

April 2000 Version 1.0

FML/NPD/FS50/FL/2359

MB86695 FireStreamTM50 ATM 52 Mbps SAR Device

Page 4 of 7

Circuit Initialisation

Circuits are initialised for both transmit and receive by placing an entry on a high or low priority
Transmit Pending Queue or onto an on-chip queue. This entry points to configuration information. A
Status Queue is used to inform the user that the operation has been completed.

Transmit Operation

Transmit operation is initiated using a simple queue structure. A buffer containing part or all of a
packet's data is scheduled by placing a Transmit Descriptor pointer on the high or low priority
Transmit Pending Queue. The FireStream50 links queued descriptors for the same VC into a list.
Data is then segmented under the control of the traffic scheduler into cells. The data pointer is
contained in the Transmit Descriptor. When a buffer is exhausted it is returned to the host by putting
the Transmit Descriptor pointer on a Release Queue.

Receive Operation

On receiving ATM cells the FireStream50 takes a buffer from one of eight simple Buffer Free Pools.
Each pool forms a linked list and buffers are allocated to the device by linking Receive Descriptors
onto the list. Each pool may use a different buffer size. Receive Circuits can be allocated to one of
these pools. Alternatively the device may be configured so that Receive Circuits use an initial buffer
from one pool followed by subsequent buffers from another pool to reassemble a packet. This
maximizes memory efficiency. Receive Circuits can have a low-priority discard mode where free
buffers will not be allocated while the number of free entries is below a programmable threshold. This
improves robustness of the system under heavy receive traffic loading by preventing the free pools
under running. When buffers are completed they are returned to the host by putting the Receive
Descriptor identifier on one of four Buffer Ready Queues.

JTAG

A JTAG port Boundary Scan port provides support for PCB production test.

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