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Электронный компонент: MB90F562

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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90560
Series
HARDWARE MANUAL
CM44-10107-1E
i
PREFACE
s
Objectives and Intended Reader
Thank you for purchasing Fujitsu semiconductor products.
The MB90560 series was developed as a group of general-purpose models in the FMC-16 LX
series, which is a family of original 16-bit single-chip microcontrollers that can be used for
application specific ICs (ASICs).
This manual is intended for engineers who design products using the MB90560 series of
microcontrollers. The manual describes the functions and operation of the MB90560 series.
s
Trademarks
FMC is a registered trademark of Fujitsu Limited and stands for FUJITSU Flexible
Microcontroller.
ii
1998 FUJITSU LIMITED Printed in Japan
1. The contents of this document are subject to change without notice. Customers are advised to consult
with FUJITSU sales representatives before ordering.
2. The information and circuit diagrams in this document are presented as examples of semiconductor
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU
is unable to assume responsibility for infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
3. The contents of this document may not be reproduced or copied without the permission of FUJITSU
LIMITED.
4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment,
personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls,
sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to
consult with FUJITSU sales representatives before such use. The company will not be responsible for
damages arising from such use without prior approval.
5. Any semiconductor devices have an inherent chance of failure.You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such
as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
6. If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export of those products from Japan.
MB90560 series
iii
CONTENTS
CHAPTER 1
OVERVIEW ....................................................................................................1
1.1
Features .................................................................................................................................................2
1.2
Product Lineup .......................................................................................................................................4
1.3
Block Diagram ........................................................................................................................................5
1.4
Pin Assignments .....................................................................................................................................6
1.5
Package Dimensions ............................................................................................................................10
1.6
Pin Functions ........................................................................................................................................14
1.7
I/O Circuit Types ...................................................................................................................................18
1.8
Notes on Handling Devices ..................................................................................................................20
CHAPTER 2
CPU ..............................................................................................................23
2.1
CPU ......................................................................................................................................................24
2.2
Memory Space ......................................................................................................................................26
2.3
Memory Maps .......................................................................................................................................28
2.4
Addressing ............................................................................................................................................29
2.4.1
Linear addressing ...........................................................................................................................30
2.4.2
Bank addressing ..............................................................................................................................32
2.5
Memory Location of Multibyte Data ......................................................................................................34
2.6
Registers ...............................................................................................................................................36
2.7
Dedicated Registers .............................................................................................................................38
2.7.1
Accumulator (A) ...............................................................................................................................40
2.7.2
Stack Pointers (USP, SSP) .............................................................................................................44
2.7.3
Processor Status (PS) .....................................................................................................................46
2.7.4
Condition code register (PS: CCR) ..................................................................................................48
2.7.5
Register bank pointer (PS: RP) .......................................................................................................50
2.7.6
Interrupt level mask register (PS: ILM) ............................................................................................51
2.7.7
Program Counter (PC) .....................................................................................................................52
2.7.8
Direct Page Register (DPR) ............................................................................................................53
2.7.9
Bank Registers (PCB, DTB, USB, SSB, ADB) ................................................................................54
2.8
General-Purpose Registers ..................................................................................................................56
2.9
Prefix Codes .........................................................................................................................................58
2.9.1
Bank select prefix (PCB, DTB, ADB, SPB) ......................................................................................60
2.9.2
Common register bank prefix (CMR) ...............................................................................................62
2.9.3
Flag change suppression prefix (NCC) ...........................................................................................63
2.9.4
Restrictions on Prefix Codes ...........................................................................................................64
CHAPTER 3
RESETS .......................................................................................................67
3.1
Resets ..................................................................................................................................................68
3.2
Reset Causes and Oscillation Stabilization Wait Intervals ...................................................................70
3.3
External Reset Pin ................................................................................................................................72
3.4
Reset Operation ....................................................................................................................................74
3.5
Reset Cause Bits ..................................................................................................................................76
3.6
Status of Pins in a Reset ......................................................................................................................78