DS07-13705-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90595/595G Series
MB90598/F598/F598G/V595/V595G
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DESCRIPTION
The MB90595/595G series with FULL-CAN*
1
interface and FLASH ROM is especially designed for automotive
and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and
Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full
CAN approach.
The instruction set of F
2
MC-16LX CPU core inherits an AT architecture of the F
2
MC*
2
family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions,
and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word data.
The MB90595/595G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)) and stepping motor controller.
*1: Controller Area Network (CAN) - License of Robert Bosch GmbH
*2: F
2
MC stands for FUJITSU Flexible Microcontroller.
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FEATURES
Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
V
CC
of 5.0 V)
(Continued)
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PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90595/595G Series
2
(Continued)
Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
Program patch function (for two address pointers)
Enhanced execution speed: 4-byte instruction queue
Enhanced interrupt function: 8 levels, 34 factors
Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
2
OS): Up to 10 channels
Embedded ROM size and types
Mask ROM: 128 Kbytes
Flash ROM: 128 Kbytes
Embedded RAM size: 4 Kbytes (MB90V595/595G : 6 Kbytes)
Flash ROM
Supports automatic programming, Embedded Algorithm
TM
*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector
Erase can be performed on each block
Block protection with external programming voltage
Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
Process: 0.5
m CMOS technology
I/O port
General-purpose I/O ports: 78 ports
Push-pull output and Schmitt trigger input.
Programmable on each bit as I/O or signal for peripherals.
Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit
6 channels
16-bit re-load timer: 2 channels
16-bit I/O timer
Input capture: 4 channels
Output compare: 4 channels
Extended I/O serial interface: 1 channel
UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
MB90595/595G Series
3
UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended transmission) can be selectively
used.
Stepping motor controller (4 channels)
External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI
2
OS) and generating an external interrupt which
is triggered by an external input.
Delayed interrupt generation module: Generates an interrupt request for switching tasks.
8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
FULL-CAN interface: 1 channel
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
18-bit Time-base counter
External bus interface: Maximum address space 16 Mbytes
*: Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
MB90595/595G Series
4
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PRODUCT LINEUP
(Continued)
Features
MB90598
MB90F598/F598G
MB90V595/V595G
Classification
Mask ROM product
Flash ROM product
Evaluation product
ROM size
128 Kbytes
128 Kbytes
Boot block
Hard-wired reset vector
None
RAM size
4 Kbytes
4 Kbytes
6 Kbytes
Emulator-specific power
supply *
1
None
CPU functions
The number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5
s
(at machine clock frequency of 16 MHz, minimum value)
UART0
Clock synchronized transmission (500 K/1 M/2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
UART1(SCI)
Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps)
Clock asynchronized transmission (1202/2404/4808/9615/31250 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
8/10-bit A/D converter
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program
up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
(6 channels)
Number of channels: 6 (8/16-bit
6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
( fsys
=
system clock frequency )
128
s ( fosc = 4MHz : oscillation clock frequency)
16-bit Reload timer
Number of channels: 2
Operation clock frequency: fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Output compares
Number of channels: 4
Pin input factor: A match signal of compare register
Input captures
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
MB90595/595G Series
5
(Continued)
*1: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*2: Varies with conditions such as the operating frequency. (See section "
s
Electrical Characteristics.")
Features
MB90598
MB90F598/F598G
MB90V595/V595G
CAN Interface
Number of channels: 1
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID's
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:
MB90xxx:TSEG2
RSJW
+
2TQ
MB90xxxG:TSEG2
RSJW
Stepping motor controller
(4 channels)
Four high current outputs for each channel
Synchronized two 8-bit PWM's for each channel
External interrupt circuit
Number of inputs: 8
Started by a rising edge, a falling edge, an "H" level input, or an "L" level input.
Serial IO
Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock
frequency of 16 MHz)
LSB first/MSB first
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm
TM
and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics Inc.
Low-power consumption
(stand-by) mode
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
Process
CMOS
Power supply voltage for
operation*
2
+
5 V
10 %
Package
QFP-100
PGA-256
PDF 
ZIP