DS07-16302-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit RISC Microcontroller

CMOS

FR Family MB91106

MB91106

DESCRIPTION

The MB91106 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To carry out hi-speed performance of CPU instructions,
instruction/data ROM of 64 Kbytes and RAM of 2 Kbytes are embedded in the MB91106.

The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation
systems, high-performance FAXs and printer controllers.

*: FR Family stands for FUJITSU RISC controller.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture, 5-stage pipeline
· Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
· General purpose registers: 32 bits

· 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
· Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
· Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

· Register interlock functions, efficient assembly language coding
· Branch instructions with delay slots: Reduced overhead time in branch executions

(Continued)

PACKAGE

100-pin Plastic LQFP

(FPT-100P-M05)

100-pin Plastic QFP

(FPT-100P-M06)

MB91106 Series

(Continued)

· Internal multiplier/supported at instruction level

Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles

· Interrupt (push PC and PS): 6 cycles, 16 priority levels

External bus interface

· Clock doublure: Maximum internal bus 50 MHz, maximum external bus 25 MHz operation
· 25-bit address bus (32 Mbytes memory space)
· 8/16-bit data bus
· Basic external bus cycle: 2 clock cycles
· Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
· Interface supported for various memory technologies

DRAM interface (area 4 and 5)

· Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
· Unused data/address pins can be configured us input/output ports
· Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

· 2 banks independent control (area 4 and 5)
· Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
· Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
· Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
· DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode

· Supports 8/9/10/12-bit column address width
· 2CAS/1WE, 2WE/1CAS selective

DMA controller (DMAC)

· 8 channels
· Transfer incident/external pins/internal resource interrupt requests
· Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
· Transfer data length: 8 bits/16 bits/32 bits selective
· NMI/interrupt request enables temporary stop operation

UART

· 3 independent channels
· Full-duplex double buffer
· Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
· Asynchronous (start-stop system), CLK-synchronized communication selective
· Multi-processor mode
· Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
· Use external clock can be used as a transfer clock
· Error detection: Parity, frame, overrun

MB91106 Series

(Continued)

10-bit A/D converter (successive approximation conversion type)

· 10-bit resolution, 4 channels
· Successive approximation type: Conversion time of 5.6

s at 25 MHz

· Internal sample and hold circuit
· Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
· Start: Software/external trigger/internal timer selective

16-bit reload timer

· 3 channels
· Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective

Other interval timers

· 16-bit timer: 3 channels (U-TIMER)
· PWM timer: 4 channels
· Watchdog timer: 1 channel

Bit search module

First bit transition "1" or "0" from MSB can be detected in 1 cycle

Interrupt controller

· External interrupt input: Non-maskable interrupt (NMI), normal interrupt

4 (INT0 to INT3)

· Internal interrupt incident: UART, DMA controller (DMAC), 10-bit A/D converter, 16-bit reload-timer, PWM timer,

U-TIMER and delayed interrupt module

· Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)

Others

· Reset cause: Power-on reset/software reset/external reset
· Low-power consumption mode: Sleep mode/stop mode
· Clock control

Gear function: Operating clocks for CPU and peripherals are independently selective

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
(However, operating frequency for peripherals is less than 25 MHz.)

· Packages: LQFP-100 and QFP-100
· CMOS technology (0.35

· Power supply voltage: 3.3 V

0.3 V

PRODUCT LINEUP

MB91V106

Classification

Mass production products

(mask ROM products)

Piggyback/evaluation product

(for evaluation and development)

IROM size

63 Kbytes

IRAM size

64 Kbytes

CROM size

64 Kbytes

CRAM size

64 Kbytes

RAM size

2 Kbytes

5 Kbytes

I $

Other

Under trial manufacture

Under development

MB91106

Part number

Parameter

MB91106 Series

PIN ASSIGNMENT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
V

CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0/PA0
NMI
V

RST
V

MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD/P83
WR0/P84
WR1/P85
D16/P20

AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/EOP0/P70
A23/P67
A22/P66
V

A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15/P57
A14/P56
A13/P55
A12/P54
A11/P53
A10/P52
A09/P51
A08/P50

RAS1/PB4/EOP2

/PB3

CS0H/PB2

CS0L/PB1

RAS0/PB0

INT0/PE0

INT1/PE1

INT2/SC1/PE2

INT3/SC2/PE3

DREQ0/PE4

DREQ1/PE5

/
P

OCP

0/PF7/A

2/OC

/
PF6

SI2/OCP

1/PF5

SO1/TRG3/PF4

SI1/TRG2/PF3

0/O

/
PF2

SO0/TRG1/PF1

SI0/TRG0/PF0

D17/P21

D18/P22

D19/P23

D20/P24

D21/P25

D22/P26

D23/P27

D24/P30

D25/P31

D26/P32

D27/P33

D28/P34

D29/P35

D30/P36

D31/P37

A00/P40

A01/P41

A02/P42

A03/P43

A04/P44

A05/P45

A06/P46

A07/P47

(Top view)

(FPT-100P-M05)

MB91106 Series

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

(Top view)

(FPT-100P-M06)

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

CS0H/PB2
DW0/PB3
RAS1/PB4/EOP2
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
V

CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0/PA0
NMI
V

RST
V

MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD/P83
WR0/P84
WR1/P85
D16/P20
D17/P21
D18/P22

SO0/TRG1/PF1
SI0/TRG0/PF0
AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/EOP0/P70
A23/P67
A22/P66
V

A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15/P57
A14/P56
A13/P55
A12/P54
A11/P53
A10/P52
A09/P51
A08/P50
A07/P47
A06/P46
A05/P45

CS0L/PB1

RAS0/PB0

INT0/PE0

INT1/PE1

INT2/SC1/PE2

INT3/SC2/PE3

DREQ0/PE4

DREQ1/PE5

/
P

OCP

0/PF7/A

2/OC

/
PF6

SI2/OCP

1/PF5

SO1/TRG3/PF4

SI1/TRG2/PF3

0/O

/
PF2

D19/P23

D20/P24

D21/P25

D22/P26

D23/P27

D24/P30

D25/P31

D26/P32

D27/P33

D28/P34

D29/P35

D30/P36

D31/P37

A00/P40

A01/P41

A02/P42

A03/P43

A04/P44

MB91106 Series

PIN DESCRIPTION

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

25 to 32

28 to 35 D16 to D23

Bit 16 to bit 23 of external data bus

P20 to P27

Can be configured as general purpose I/O port when external
data bus width is set to 8-bit or in single chip mode.

33 to 39,

36 to 42,

D24 to D30,
D31

Bit 24 to bit 31 of external data bus

P30 to P36,
P37

Can be configured as general purpose I/O ports when not used
as address bus.

42,

44 to 50,

51 to 58

45,

47 to 53,

54 to 61

A00,
A01 to A07,
A08 to A15

Bit 00 to bit 15 of external address bus

P40,
P41 to P47,
P50 to P57

Can be configured as general purpose I/O ports when not used
as address bus.

59 to 64,

66,

62 to 67,

69,

A16 to A21,
A22,
A23

Bit 16 to bit 23 of external address bus

P60 to P67,
P69,
P70

Can be configured as general purpose I/O ports when not used
as address bus.

A24

Bit 24 of external address bus

EOP0

Can be configured as DMAC EOP output (ch. 0) when DMAC
EOP output is enabled.

P70

Can be configured as general purpose I/O port when A24 and
EOP0 are not used.

RDY

External ready input
Inputs "0" when bus cycle is being executed and not completed.

P80

Can be configured as general purpose I/O port when RDY is
not used.

BGRNT

External bus release acknowledge output
Outputs "L" level when external bus is released.

P81

Can be configured as general purpose I/O port when BGRNT is
not used.

BRQ

External bus release request input
Inputs "1" when release of external bus is required.

P82

Can be configured as general purpose I/O port when BRQ is
not used.

Read strobe output pin for external bus

P83

Can be configured as general purpose I/O port when RD is not
used.

MB91106 Series

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

P84

Can be configured as general purpose I/O port when WR0 is
not used.

WR0

Write strobe output pin for external bus
Relation between control signals and effective byte locations is
as follows:

Note: WR1 is Hi-Z during resetting.

Attach an external pull-up resister when using at 16-bit
bus width.

WR1

P85

Can be configured as general purpose I/O port when WR1 is
not used.

CS0

Chip select 0 output ("L" active)

PA0

Can be configured as general purpose I/O port when CS0 is
not used.

CS1

Chip select 1 output ("L" active)

PA1

Can be configured as general purpose I/O port when CS1 is
not used.

CS2

Chip select 2 output ("L" active)

PA2

Can be configured as a port when CS2 is not used.

CS3

Chip select 3 output ("L" active)

PA3

Can be configured as a port when CS3 and EOP1 are not
used.

EOP1

EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is
enabled.

CS4

Chip select 4 output ("L" active)

PA4

Can be configured as general purpose I/O port when CS4 is
not used.

CS5

Chip select 5 output ("L" active)

PA5

Can be configured as general purpose I/O port when CS5 is
not used.

CLK

System clock output
Outputs clock signal of external bus operating frequency.

PA6

Can be configured as general purpose I/O port when CLK is
not used.

16-bit

bus width

8-bit

bus width

Single chip

mode

D31 to D24

WR0

(I/O port

enabled)

D23 to D16

WR1

(I/O port

enabled)

(I/O port

enabled)

MB91106 Series

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

RAS0

RAS output for DRAM bank 0

PB0

Can be configured as general purpose I/O port when RAS0 is
not used.

100

CS0L

CASL output for DRAM bank 0

PB1

Can be configured as general purpose I/O port when CS0L is
not used.

CS0H

CASH output for DRAM bank 0

PB2

Can be configured as general purpose I/O port when CS0H is
not used.

DW0

WE output for DRAM bank 0 ("L" active)

PB3

Can be configured as general purpose I/O port when DW0 is
not used.

100

RAS1

RAS output for DRAM bank 1

PB4

Can be configured as general purpose I/O port when RAS1
and EOP2 are not used.

EOP2

DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.

CS1L

CASL output for DRAM bank 1

PB5

Can be configured as general purpose I/O port when CS1L
and DREQ are not used.

DREQ2

External transfer request input pin for DMA
This pin is used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output
for other functions from this pin unless such output is made
intentionally.

CS1H

CASH output for DRAM bank 1

PB6

Can be configured as general purpose I/O port when CS1H
and DACK2 are not used.

DACK2

External transfer request accept output pin for DMAC (ch. 2)
This function is available when transfer request output for
DMAC is enabled.

DW1

WE output for DRAM bank 1 ("L" active)

PB7

Can be configured as general purpose I/O port when DW1 is
not used.

16 to 18

19 to 21

MD0 to MD2

Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with V

or V

for use.

Clock (oscillator) input

Clock (oscillator) output

RST

External reset input

NMI

NMI (non-maskable interrupt pin) input ("L" active)

MB91106 Series

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

95,

98,

INT0,
INT1

External interrupt request input pins
These pins are used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other
functions from these pins unless such output is made
intentionally.

PE0,
PE1

Can be configured as general purpose I/O ports when INT0
and INT1 are not used.

INT2

External interrupt request input pin
This pin is used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.

SC1

Clock I/O pin for UART1
Clock output is available when clock output of UART1 is
enabled.

PE2

Can be configured as general purpose I/O port when INT2 and
SC1 are not used.
This function is available when UART1 clock output is disabled.

INT3

SC2

UART2 clock I/O pin
Clock output is available when UART2 clock output is enabled.

PE3

Can be configured as general purpose I/O port when INT3 and
SC2 are not used.
This function is available when UART2 clock output is disabled.

87,

90,

DREQ0,
DREQ1

External transfer request input pins for DMA
These pins are used for input when external trigger is selected
to cause DMAC operation, and it is necessary to disable output
for other functions from these pins unless such output is made
intentionally.

PE4,
PE5

Can be configured as general purpose I/O ports when DREQ0
and DREQ1 are not used.

DACK0

External transfer request acknowledge output pin for DMAC
(ch. 0)
This function is available when transfer request output for
DMAC is enabled.

PE6

Can be configured as general purpose I/O port when DACK0 is
not used.
This function is available when transfer request acknowledge
output for DMAC or DACK0 output is disabled.

MB91106 Series

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

DACK1

External transfer request acknowledge output pin for DMAC
(ch. 1)
This function is available when transfer request output for
DMAC is enabled.

PE7

Can be configured as general purpose I/O port when DACK1 is
not used.
This function is available when transfer request output for
DMAC or DACK1 output is disabled.

SI0

UART0 data input pin
This pin is used for input during UART0 is in input operation,
and it is necessary to disable output for other functions from
this pin unless such output is made intentionally.

TRG0

PWM timer external trigger input pin (ch.0)
This pin is used for input during PWM timer external trigger is
in input operation, and it is necessary to disable output for
other functions from this pin unless such output is made
intentionally.

PF0

Can be configured as general purpose I/O port when SI0 and
TRG0 are not used.

SO0

UART0 data output pin
This function is available when UART0 data output is enabled.

TRG1

PWM timer external trigger input pin
This function is available when serial data output of PF1,
UART0 are disabled.

PF1

Can be configured as general purpose I/O port when SO0 and
TRG1 are not used.
This function is available when serial data output of UART0 is
disabled.

SC0

UART0 clock I/O pin
Clock output is available when UART0 clock output is enabled.

OCPA3

PWM timer output pin
This function is available when PWM timer output is enabled.

PF2

Can be configured as general purpose I/O port when SC0 and
OCPA3 are not used.
This function is available when UART0 clock output is disabled.

SI1

UART1 data input pin
This pin is used for input during UART1 is in input operation,
and it is necessary to disable output for other functions from
this pin unless such output is made intentionally.

TRG2

PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is
in input operation, and it is necessary to disable output for
other functions from this pin unless such output is made
intentionally.

PF3

Can be configured as general purpose I/O port when SI1 and
TRG2 are not used.

MB91106 Series

*1: FPT-100P-M05

(Continued)

*2: FPT-100P-M06

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

SO1

UART1 data output pin
This function is available when UART1 data output is enabled.

TRG3

PWM timer external trigger input pin
This function is available when PF4, UART1 data outputs are
disabled.

PF4

Can be configured as general purpose I/O port when SO1 and
TRG3 are not used.
This function is available when UART1 data output is disabled.

SI2

UART2 data input pin
This pin is used for input during UART2 is in input operation,
and it is necessary to disable output for other functions from
this pin unless such output is made intentionally.

OCPA1

PWM timer output pin
This function is available when PWM timer output is enabled.

PF5

Can be configured as general purpose I/O port when SI2 and
OCPA2 are not used.

SO2

UART2 data output pin
This function is available when UART2 data output is enabled.

OCPA2

PWM timer output pin
This function is available when PWM timer output is enabled.

PF6

Can be configured as general purpose I/O port when SO2 and
OCPA2 are not used.
This function is available when UART2 data output is disabled.

OCPA0

PWM timer output pin
This function is available when PWM timer output is enabled.

PF7

Can be configured as a port when OCPA0 and ATG are not
used.
This function is available when PWM timer output is disabled.

ATG

External trigger input pin for A/D converter
This pin is used for input when external trigger is selected to
cause A/D converter operation, and it is necessary to disable
output for other functions from this pin unless such output is
made intentionally.

72 to 75

75 to 78

AN0 to AN3

Analog input pins of A/D converter
This function is available when AIC register is set to specify
analog input mode.

Power supply pin (V

) for A/D converter

AVRH

Reference voltage input (high) for A/D converter
Make sure to turn on and off this pin with potential of AVRH or
more applied to V

AVRL

Power supply pin (V

) for A/D converter and reference voltage

input pin (low)

MB91106 Series

(Continued)

*1: FPT-100P-M05
*2: FPT-100P-M06

Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between

output of I/O port and resource I/O, priority is always given to the output of resource I/O.

Pin no.

Pin name

Circuit

type

Function

LQFP*

QFP*

13,
43,

16,
46,

Power supply pin (V

) for digital circuit

Always power supply pin (V

) must be connected to the power

supply

15,
40,
65,

18,
43,
68,

Earth level (V

) for digital circuit

MB91106 Series

DRAM CONTROL PIN

Pin name

Data bus 16-bit mode

Data bus 8-bit mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

Area 4 RAS

Correspondence of "L"
"H" to lower address 1
bit (A0) in data bus 16-
bit mode
"L": "0"
"H": "1"
CASL: CAS which A0

corresponds to
"0" area

CASH: CAS which A0

corresponds to
"1" area

WEL: WE which A0

corresponds to
"0" area

WEH: WE which A0

corresponds to
"1" area

Area 5 RAS

Area 4 CASL

Area 4 CAS

Area 4 CASH

Area 4 WEL

Area 4 CAS

Area 5 CASL

Area 5 CAS

Area 5 CASH

Area 5 WEL

Area 5 CAS

Area 4 WE

Area 4 WEH

Area 4 WE

DW1

Area 5 WE

Area 5 WEH

Area 5 WE

RAS0

RAS1

CS0L

CS0H

CS1L

CS1H

DW0

MB91106 Series

I/O CIRCUIT TYPE

(Continued)

Type

Circuit

Remarks

· Oscillation feedback resistance 1 M

approx.
With standby control

· CMOS level hysteresis input

Without standby control
With pull-up resistance

· CMOS level I/O

With standby control

· Analog input

Clock input

Standby control signal

Digital input

N-channel
type transister

P-channel
type transister

Diffused resistor

P-ch

Standby control signal

N-ch

P-ch

Digital output

Digital input

Digital output

P-ch

Analog input

N-ch

Digital output

MB91106 Series

HANDLING DEVICES

Preventing Latchup

In CMOS ICs, applying voltage higher than V

or lower than V

to input/output pin or applying voltage over

rating across V

and V

may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.

Take care that the analog power supply (AV

AVR) and the analog input do not exceed the digital power supply

) when the analog power supply turned on or off.

Treatment of Unused Pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

External Reset Input

It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.

Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops
at "H" output in stop mode).

And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.

· Using an external clock

Using an external clock (normal)

Note: Can not be used stop mode (oscillation stop mode).

Using an external clock (can be used at 12.5 MHz and less than.)

(5 V power supply only)

MB91106

Open

MB91106 Series

Power Supply Pins

When there are several V

and V

pins, each of them is equipotentially connected to its counterpart inside

of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all V

and V

pins to the power supply or GND.

It is preferred to connect V

and V

of MB91106 to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1

F between V

and V

at a position as close as possible to MB91106.

Crystal Oscillator Circuit

Noises around X0 and X1 pins may cause malfunctions of MB91106. In designing the PC board, layout X0,
X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.

It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.

Turning-on Sequence of A/D Converter Power Supply and Analog Input

Make sure to turn on the digital power supply (V

) before turning on the A/D converter (AV

, AVRH) and

applying voltage to analog input (AN0 to AN3).

Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been
switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies
may be turned on simultaneously.) Make sure that AVRH never exceeds AV

when turning on/off power

supplies.

Treatment of N.C. Pins

Make sure to leave N.C. pins open.

Fluctuation of Power Supply Voltage

Warranty range for normal operation against fluctuation of power supply voltage V

is as given in rating.

However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is
recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by
controlling power supply as a reference of stabilizing, V

ripple fluctuation (P-P value) at the commercial

frequency (50 Hz to 60 Hz) should be less than 10% of the standard V

value and the transient regulation

should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.

10. Mode Setting Pins (MD0 to MD2)

Connect mode setting pins (MD0 to MD2) directly to V

or V

Arrange each mode setting pin and V

or V

patterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

11. Turning on the Power Supply

When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power
supply voltage goes to V

level, at least after ensuring the time for 5 machine cycle, then set to "H" level.

MB91106 Series

12. Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5
MHz. Take care that the pin condition may be output condition at initial unstable condition.

13. Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.

14. Initialization

Some internal resistors initialized only via power on reset are embedded in the device. To initialize these
resistors, run power on reset by returning on the power supply or to set RST pin to "H" level.

MB91106 Series

BLOCK DIAGRAM

Note: Pins are display for functions (Actually some pins are multiplexer).

When using REALOS, time control should be done by using external interrupt or inner timer.

FR CPU

RAM (2 Kbytes)

Bit search module

DMA controller (DMAC)

(8 ch.)

Bus converter (32 bits

16bits)

Clock control unit
(Watchdog timer)

Interrupt control unit

10-bit A/D converter

(4 ch.)

16-bit reload timer (3 ch.)

Port E,

Port F

D-b

s (32 bits)

I-b

s (16 bits)

Instruction ROM

63 Kbytes, 32bits

Bus converter

(Harvard

Princeton)

Bus controller

DRAM interface

Instruction ROM

and

data ROM

64 Kbytes

Port 2 to port B

UART (3 ch.)

(Baud rate timer)

PWM timer (4 ch.)

Other pins

MD0 to MD2, V

, V

DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2

X0
X1
RST

INT0 to INT3
NMI

AN0 to AN3
AV

AVRH
AVRL
ATG

PE0 to PE7
PF0 to PF7

8
8

R-b

s (16 bits)

C-b

s (32 bits)

D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
CS0 to CS5
BRQ
BGRNT

RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1

P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70
PA80 to P85
PA0 to PA6
PB0 to PB7

SI0 to SI2
SO0 to SO2
SC0 to SC2

OCPA0 to OCPA3
TRG0 to TRG3

3
3
3

4
4

MB91106 Series

CPU CORE

Memory Space

The FR family has a logical address space of 4 Gbytes (2

bytes) and the CPU linearly accesses the memory

space.

· Memory space

* : Direct addressing area

The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an
address can be specified in a direct operand of a code.

Direct areas consists of the following areas dependent on accessible data sizes.

Byte data access: 000

to 0FF

Half word data access: 000

to 1FF

Word data access: 000

to 3FF

Notes:

Access to the external area can be execute in the single chip mode.
To access to the external area, select internal ROM external bus mode via mode resistor.
Never execute data access to the instruction ROM area.

In the instruction/data ROM, images in block of 64 Kbytes can be seen.
Make an instruction/data in the area 000F0000

to 000FFFFF

See "

I/O MAP"

Direct

addressing

area*

Single chip mode

Memory Space

Internal ROM/

external bus mode

External ROM/

external bus mode

Address

0000 0000

0000 0400

0000 0800

0000 1000

0000 1800

0001 0000

0008 0000

0008 FC00

000F 0000

0010 0000

FFFF FFFF

I/0 Area

Access inhibited

Embedded RAM

(2 Kbytes)

Access inhibited

Instruction ROM

(63 Kbytes)

Access inhibited

Instruction ROM/data ROM

(64 Kbytes)

Access inhibited

I/0 Area

Access inhibited

Embedded RAM

(2 Kbytes)

Access inhibited

External area

Instruction ROM

(63 Kbytes)

Access inhibited

Instruction ROM/data ROM

(64 Kbytes)

External area

I/0 Area

Access inhibited

Embedded RAM

(2 Kbytes)

Access inhibited

External area

MB91106 Series

Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.

· Dedicated registers

Program counter (PC):

32-bit length, indicates the location of the instruction to be executed.

Program status (PS):

32-bit length, register for storing register pointer or condition codes

Table base register (TBR):

Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)
processing.

Return pointer (RP):

Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP): Indicates system stack space.
User's stack pointer (USP): Indicates user's stack space.
Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division

· Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).

TBR

SSP

USP

MDH

MDL

Initial value

Program counter

Program status

Table base register

Return pointer

System stack pointer

User's stack pointer

Multiplication/division result register

XXXX XXXX

Indeterminate

000F

FC00

XXXX XXXX

Indeterminate

0000

XXXX XXXX

Indeterminate

XXXX XXXX

Indeterminate

XXXX XXXX

Indeterminate

32 bits

ILM4 ILM3 ILM2 ILM1

ILM0

ILM

SCR

CCR

MB91106 Series

· Condition code register (CCR)

S-flag:

Specifies a stack pointer used as R15.

I-flag:

Controls user interrupt request enable/disable.

N-flag:

Indicates sign bit when division result is assumed to be in the 2's complement format.

Z-flag:

Indicates whether or not the result of division was "0".

V-flag:

Assumes the operand used in calculation in the 2's complement format and indicates whether
or not overflow has occurred.

C-flag:

Indicates if a carry or borrow from the MSB has occurred.

· System condition code register (SCR)

T-flag:

Specifies whether or not to enable step trace trap.

· Interrupt level mask register (ILM)

ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

High

:
:

Low

MB91106 Series

GENERAL-PURPOSE REGISTERS

R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer (field for indicating address).

Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.

R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000

(SSP value).

· Register bank structure

R12

R13

R14

R15

AC (accumulator)

FP (frame pointer)

SP (stack pointer)

32 bits

:
:

Initial value

XXXX XXXX

:
:
:
:
:
:
:
:
:
:
:

XXXX XXXX

0 0 0 0 0 0 0 0

MB91106 Series

SETTING MODE

Pin

· Mode setting pins and modes

* : MB91106 support single-chip mode.

Registers

· Mode setting registers (MODR) and modes

· Bus mode setting bits and functions

Mode setting

pins

Mode name

Reset vector

access area

External data

bus width

Bus mode

MD2 MD1 MD0

External vector mode 0

External

8 bits

External ROM/external bus
mode

External vector mode 1

External

16 bits

Inhibited

Internal vector mode

Internal

(Mode register)

Single-chip mode*

Not use

Functions

Note

Single-chip mode

Internal ROM/external bus mode

External ROM/external bus mode

Inhibited

Address

0000 07FF

Bus mode setting bit

W : Write only
X : Indeterminate
* : Always write "0" except for M1 and M0.

Initial value

XXXX XXXX

Access

MB91106 Series

I/O MAP

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000000

PDR3

Port 3 data register

R/W

Port 3

X X X X X X X X

000001

PDR2

Port 2 data register

R/W

Port 2

X X X X X X X X

000002

(Vacancy)

000003

000004

PDR7

Port 7 data register

R/W

Port 7

000005

PDR6

Port 6 data register

R/W

Port 6

X X X X X X X X

000006

PDR5

Port 5 data register

R/W

Port 5

X X X X X X X X

000007

PDR4

Port 4 data register

R/W

Port 4

X X X X X X X X

000008

PDRB

Port B data register

R/W

Port B

X X X X X X X X

000009

PDRA

Port A data register

R/W

Port A

X X X X X X X

00000A

(Vacancy)

00000B

PDR8

Port 8 data register

R/W

Port 8

X X X X X X

00000C

000011

(Vacancy)

000012

PDRE

Port E data register

R/W

Port E

X X X X X X X X

000013

PDRF

Port F data register

R/W

Port F

X X X X X X X X

000014

00001B

(Vacancy)

00001C

SSR0

Serial status register 0

R/W

UART0

0 0 0 0 1 0 0

00001D

SIDR0/SODR0

Serial input data register 0/serial
output data register 0

R/W

X X X X X X X X

00001E

SCR0

Serial control register 0

R/W

0 0 0 0 0 1 0 0

00001F

SMR0

Serial mode register 0

R/W

0 0 0 0 0

000020

SSR1

Serial status register 1

R/W

UART1

0 0 0 0 1 0 0

000021

SIDR1/SODR1

Serial input data register 1/serial
output data register 1

R/W

X X X X X X X X

000022

SCR1

Serial control register 1

R/W

0 0 0 0 0 1 0 0

000023

SMR1

Serial mode register 1

R/W

0 0 0 0 0

000024

SSR2

Serial status register 2

R/W

UART2

0 0 0 0 1 0 0

000025

SIDR2/SODR2

Serial input data register 2/serial
output data register 2

R/W

X X X X X X X X

000026

SCR2

Serial control register 2

R/W

0 0 0 0 0 1 0 0

000027

SMR2

Serial mode register 2

R/W

0 0 0 0 0

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000028

TMRLR0

16-bit reload register 0

16-bit reload

timer 0

X X X X X X X X

000029

X X X X X X X X

00002A

TMR0

16-bit timer register 0

X X X X X X X X

00002B

X X X X X X X X

00002C

(Vacancy)

00002D

00002E

TMCSR0

16-bit reload timer control status
register 0

R/W

16-bit reload

timer 0

0 0 0 0

00002F

0 0 0 0 0 0 0 0

000030

TMRLR1

16-bit reload register 1

16-bit reload

timer 1

X X X X X X X X

000031

X X X X X X X X

000032

TMR1

16-bit timer register 1

X X X X X X X X

000033

X X X X X X X X

000034

(Vacancy)

000035

000036

TMCSR1

16-bit reload timer control status
register 1

R/W

16-bit reload

timer 1

0 0 0 0

000037

0 0 0 0 0 0 0 0

000038

ADCR

A/D converter data register

10-bit A/D

converter

0 0 0 0 0 0 X X

000039

X X X X X X X X

00003A

ADCS

A/D converter control status register

R/W

0 0 0 0 0 0 0 0

00003B

0 0 0 0 0 0 0 0

00003C

TMRLR2

16-bit reload register 2

16-bit reload

timer 2

X X X X X X X X

00003D

X X X X X X X X

00003E

TMR2

16-bit timer register 2

X X X X X X X X

00003F

X X X X X X X X

000040

(Vacancy)

000041

000042

TMCSR2

16-bit reload timer control status
register 2

R/W

16-bit reload

timer 2

0 0 0 0

000043

0 0 0 0 0 0 0 0

000044

000077

(Vacancy)

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000078

UTIM0/UTIMR0

U-TIMER register ch. 0 /U-TIMER
reload register ch. 0

R/W

U-TIMER 0

0 0 0 0 0 0 0 0

000079

0 0 0 0 0 0 0 0

00007A

(Vacancy)

00007B

UTIMC0

U-TIMER control register ch. 0

R/W

U-TIMER 0

0 0 0 0 0 1

00007C

UTIM1/UTIMR1

U-TIMER register ch. 1/reload
register ch. 1

R/W

U-TIMER 1

0 0 0 0 0 0 0 0

00007D

0 0 0 0 0 0 0 0

00007E

(Vacancy)

00007F

UTIMC1

U-TIMER control register ch. 1

R/W

U-TIMER 1

0 0 0 0 0 1

000080

UTIM2/UTIMR2

U-TIMER register ch. 2/U-TIMER
reload register ch. 2

R/W

U-TIMER 2

0 0 0 0 0 0 0 0

000081

0 0 0 0 0 0 0 0

000082

(Vacancy)

000083

UTIMC2

U-TIMER control register ch. 2

R/W

U-TIMER 2

0 0 0 0 0 1

000084

000093

(Vacancy)

000094

EIRR

External interrupt cause register

R/W

External

interrupt/

NMI

0 0 0 0 0 0 0 0

000095

ENIR

Interrupt enable register

R/W

0 0 0 0 0 0 0 0

000096

000098

(Vacancy)

000099

ELVR

External interrupt request level
setting register

R/W

External

interrupt/

NMI

0 0 0 0 0 0 0 0

00009A

0000D1

(Vacancy)

0000D2

DDRE

Port E data direction register

Port E

0 0 0 0 0 0 0 0

0000D3

DDRF

Port F data direction register

Port F

0 0 0 0 0 0 0 0

0000D4

0000DB

(Vacancy)

0000DC

GCN1

General control register 1

R/W

PWM

timer 1

0 0 1 1 0 0 1 0

0000DD

0 0 0 1 0 0 0 0

0000DE

(Vacancy)

0000DF

GCN2

General control register 2

R/W

PWM

timer 2

0 0 0 0 0 0 0 0

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

0000E0

PTMR0

PWM timer register 0

PWM

timer 0

1 1 1 1 1 1 1 1

0000E1

1 1 1 1 1 1 1 1

0000E2

PCSR0

PWM cycle setting register 0

X X X X X X X X

0000E3

X X X X X X X X

0000E4

PDUT0

PWM duty setting register 0

X X X X X X X X

0000E5

X X X X X X X X

0000E6

PCNH0

Control status register H 0

R/W

0 0 0 0 0 0 0

0000E7

PCNL0

Control status register L 0

R/W

0 0 0 0 0 0 0 0

0000E8

PTMR1

PWM timer register 1

PWM

timer 1

1 1 1 1 1 1 1 1

0000E9

1 1 1 1 1 1 1 1

0000EA

PCSR1

PWM cycle setting register 1

X X X X X X X X

0000EB

X X X X X X X X

0000EC

PDUT1

PWM duty setting register 1

X X X X X X X X

0000ED

X X X X X X X X

0000EE

PCNH1

Control status register H 1

R/W

0 0 0 0 0 0 0

0000EF

PCNL1

Control status register L 1

R/W

0 0 0 0 0 0 0 0

0000F0

PTMR2

PWM timer register 2

PWM

timer 2

1 1 1 1 1 1 1 1

0000F1

1 1 1 1 1 1 1 1

0000F2

PCSR2

PWM cycle setting register 2

X X X X X X X X

0000F3

X X X X X X X X

0000F4

PDUT2

PWM duty setting register 2

X X X X X X X X

0000F5

X X X X X X X X

0000F6

PCNH2

Control status register H 2

R/W

0 0 0 0 0 0 0

0000F7

PCNL2

Control status register L 2

R/W

0 0 0 0 0 0 0 0

0000F8

PTMR3

PWM timer register 3

PWM

timer 3

1 1 1 1 1 1 1 1

0000F9

1 1 1 1 1 1 1 1

0000FA

PCSR3

PWM cycle setting register 3

X X X X X X X X

0000FB

X X X X X X X X

0000FC

PDUT3

PWM duty setting register 3

X X X X X X X X

0000FD

X X X X X X X X

0000FE

PCNH3

Control status register H 3

R/W

0 0 0 0 0 0 0

0000FF

PCNL3

Control status register L 3

R/W

0 0 0 0 0 0 0 0

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000100

0001FF

(Vacancy)

000200

DPDP

DMAC parameter descriptor pointer

R/W

DMA

controller

(DMAC)

X X X X X X X X

000201

X X X X X X X X

000202

X X X X X X X X

000203

X 0 0 0 0 0 0 0

000204

DACSR

DMAC control status register

R/W

0 0 0 0 0 0 0 0

000205

0 0 0 0 0 0 0 0

000206

0 0 0 0 0 0 0 0

000207

0 0 0 0 0 0 0 0

000208

DATCR

DMAC pin control register

R/W

X X X X X X X X

000209

X X 0 0 0 0 0 0

00020A

X X 0 0 0 0 0 0

00020B

X X 0 0 0 0 0 0

00020C

0003EF

(Vacancy)

0003F0

BSD0

Bit search module 0-detection data
register

Bit search

module

X X X X X X X X

0003F1

X X X X X X X X

0003F2

X X X X X X X X

0003F3

X X X X X X X X

0003F4

BSD1

Bit search module 1-detection data
register

R/W

X X X X X X X X

0003F5

X X X X X X X X

0003F6

X X X X X X X X

0003F7

X X X X X X X X

0003F8

BSDC

Bit search module transition-
detection data register

X X X X X X X X

0003F9

X X X X X X X X

0003FA

X X X X X X X X

0003FB

X X X X X X X X

0003FC

BSRR

Bit search module detection result
register

X X X X X X X X

0003FD

X X X X X X X X

0003FE

X X X X X X X X

0003FF

X X X X X X X X

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000400

ICR00

Interrupt control register 0

R/W

Interrupt

controller

1 1 1 1 1

000401

ICR01

Interrupt control register 1

R/W

1 1 1 1 1

000402

ICR02

Interrupt control register 2

R/W

1 1 1 1 1

000403

ICR03

Interrupt control register 3

R/W

1 1 1 1 1

000404

ICR04

Interrupt control register 4

R/W

1 1 1 1 1

000405

ICR05

Interrupt control register 5

R/W

1 1 1 1 1

000406

ICR06

Interrupt control register 6

R/W

1 1 1 1 1

000407

ICR07

Interrupt control register 7

R/W

1 1 1 1 1

000408

ICR08

Interrupt control register 8

R/W

1 1 1 1 1

000409

ICR09

Interrupt control register 9

R/W

1 1 1 1 1

00040A

ICR10

Interrupt control register 10

R/W

1 1 1 1 1

00040B

ICR11

Interrupt control register 11

R/W

1 1 1 1 1

00040C

ICR12

Interrupt control register 12

R/W

1 1 1 1 1

00040D

ICR13

Interrupt control register 13

R/W

1 1 1 1 1

00040E

ICR14

Interrupt control register 14

R/W

1 1 1 1 1

00040F

ICR15

Interrupt control register 15

R/W

1 1 1 1 1

000410

ICR16

Interrupt control register 16

R/W

1 1 1 1 1

000411

ICR17

Interrupt control register 17

R/W

1 1 1 1 1

000412

ICR18

Interrupt control register 18

R/W

1 1 1 1 1

000413

ICR19

Interrupt control register 19

R/W

1 1 1 1 1

000414

ICR20

Interrupt control register 20

R/W

1 1 1 1 1

000415

ICR21

Interrupt control register 21

R/W

1 1 1 1 1

000416

ICR22

Interrupt control register 22

R/W

1 1 1 1 1

000417

ICR23

Interrupt control register 23

R/W

1 1 1 1 1

000418

ICR24

Interrupt control register 24

R/W

1 1 1 1 1

000419

ICR25

Interrupt control register 25

R/W

1 1 1 1 1

00041A

ICR26

Interrupt control register 26

R/W

1 1 1 1 1

00041B

ICR27

Interrupt control register 27

R/W

1 1 1 1 1

00041C

ICR28

Interrupt control register 28

R/W

1 1 1 1 1

00041D

ICR29

Interrupt control register 29

R/W

1 1 1 1 1

00041E

ICR30

Interrupt control register 30

R/W

1 1 1 1 1

00041F

ICR31

Interrupt control register 31

R/W

1 1 1 1 1

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000420

00042E

(Vacancy)

00042F

ICR47

Interrupt control register 47

R/W

Interrupt

controller

1 1 1 1 1

000430

DICR

Delayed interrupt control register

R/W

000431

HRCL

Hold request cancel request level
setting register

R/W

1 1 1 1 1

000432

00047F

(Vacancy)

000480

RSRR/WTCR

Reset cause register/
watchdog cycle control register

R/W

Clock

control

1X X X X 0 0

000481

STCR

Standby control register

R/W

0 0 0 1 1 1

000482

PDRR

DMA controller request squelch
register

R/W

0 0 0 0

000483

CTBR

Timebase timer clear register

X X X X X X X X

000484

GCR

Gear control register

R/W

1 1 0 0 1 1 1

000485

WPR

Watchdog reset occurrence postpone
register

X X X X X X X X

000486

(Vacancy)

000487

000488

PCTR

PLL control register

R/W

PLL control

0 0 0

000489

0005FF

(Vacancy)

000600

DDR3

Port 3 data direction register

Port 3

0 0 0 0 0 0 0 0

000601

DDR2

Port 2 data direction register

Port 2

0 0 0 0 0 0 0 0

000602

000603

(Vacancy)

000604

DDR7

Port 7 data direction register

Port 7

000605

DDR6

Port 6 data direction register

Port 6

0 0 0 0 0 0 0 0

000606

DDR5

Port 5 data direction register

Port 5

0 0 0 0 0 0 0 0

000607

DDR4

Port 4 data direction register

Port 4

0 0 0 0 0 0 0 0

000608

DDRB

Port B data direction register

Port B

0 0 0 0 0 0 0 0

000609

DDRA

Port A data direction register

Port A

0 0 0 0 0 0 0

00060A

(Vacancy)

00060B

DDR8

Port 8 data direction register

Port 8

0 0 0 0 0 0

MB91106 Series

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

00060C

ASR1

Area select register 1

External bus

interface

0 0 0 0 0 0 0 0

00060D

0 0 0 0 0 0 0 1

00060E

AMR1

Area mask register 1

0 0 0 0 0 0 0 0

00060F

0 0 0 0 0 0 0 0

000610

ASR2

Area select register 2

0 0 0 0 0 0 0 0

000611

0 0 0 0 0 0 1 0

000612

AMR2

Area mask register 2

0 0 0 0 0 0 0 0

000613

0 0 0 0 0 0 0 0

000614

ASR3

Area select register 3

0 0 0 0 0 0 0 0

000615

0 0 0 0 0 0 1 1

000616

AMR3

Area mask register 3

0 0 0 0 0 0 0 0

000617

0 0 0 0 0 0 0 0

000618

ASR4

Area select register 4

0 0 0 0 0 0 0 0

000619

0 0 0 0 0 1 0 0

00061A

AMR4

Area mask register 4

0 0 0 0 0 0 0 0

00061B

0 0 0 0 0 0 0 0

00061C

ASR5

Area select register 5

0 0 0 0 0 0 0 0

00061D

0 0 0 0 0 1 0 1

00061E

AMR5

Area mask register 5

0 0 0 0 0 0 0 0

00061F

0 0 0 0 0 0 0 0

000620

AMD0

Area mode register 0

R/W

0 0 1 1 1

000621

AMD1

Area mode register 1

R/W

0 0 0 0 0 0

000622

AMD32

Area mode register 32

R/W

0 0 0 0 0 0 0 0

000623

AMD4

Area mode register 4

R/W

0 0 0 0 0 0

000624

AMD5

Area mode register 5

R/W

0 0 0 0 0 0

000625

DSCR

DRAM signal control register

0 0 0 0 0 0 0 0

000626

RFCR

Refresh control register

R/W

X X X X X X

000627

0 0 0 0 0

000628

EPCR0

External pin control register 0

1 1 0 0

000629

1 1 1 1 1 1 1

00062A

EPCR1

External pin control register 1

00062B

1 1 1 1 1 1 1 1

00062C

DMCR4

DRAM control register 4

R/W

0 0 0 0 0 0 0 0

00062D

0 0 0 0 0 0 0

00062E

DMCR5

DRAM control register 5

R/W

0 0 0 0 0 0 0 0

00062F

0 0 0 0 0 0 0

MB91106 Series

(Continued)

About Programming

R/W: Readable and writable
R: Read only
W: Write only

Explanation of initial values

0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
: This bit is not used. The initial value of this bit is undefined.

RMW system instructions (RMW: Read Modify Write)

Notes:

Never execute a RMW system instruction to the resistor has a write only bit.

The area "vacancy" on the I/O map is reserved area. Access to this area are deal with to an internal area.
No access signals to the external area would be generated.

Address

Register name

(abbreviated)

Register name

Read/write

Resources

name

Initial value

000630

0007FD

(Vacancy)

0007FE

LER

Little endian register

External bus

interface

0 0 0

0007FF

MODR

Mode register

X X X X X X X X

AND
ANDH
ANDB
BANDL
BANDH

Rj, @ Ri
Rj, @ Ri
Rj, @ Ri
#

4, @ Ri

OR
ORH
ORB
BORL
BORH

Rj, @ Ri
Rj, @ Ri
Rj, @ Ri
#

4, @ Ri

EOR
EORH
EORB
BEORL
BEORH

Rj, @ Ri
Rj, @ Ri
Rj, @ Ri
#

4, @ Ri

MB91106 Series

INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

Reset

3FC

000FFFFC

Reserved for system

3F8

000FFFF8

Reserved for system

3F4

000FFFF4

Reserved for system

3F0

000FFFF0

Reserved for system

3EC

000FFFEC

Reserved for system

3E8

000FFFE8

Reserved for system

3E4

000FFFE4

Reserved for system

3E0

000FFFE0

Reserved for system

3DC

000FFFDC

Reserved for system

3D8

000FFFD8

Reserved for system

3D4

000FFFD4

Reserved for system

3D0

000FFFD0

Reserved for system

3CC

000FFFCC

Reserved for system

3C8

000FFFC8

Exception for undefined instruction

3C4

000FFFC4

NMI request

fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

UART0 receive complete

ICR04

3AC

000FFFAC

UART1 receive complete

ICR05

3A8

000FFFA8

UART2 receive complete

ICR06

3A4

000FFFA4

UART0 transmit complete

ICR07

3A0

000FFFA0

UART1 transmit complete

ICR08

39C

000FFF9C

UART2 transmit complete

ICR09

398

000FFF98

DMAC0 (complete, error)

ICR10

394

000FFF94

DMAC1 (complete, error)

ICR11

390

000FFF90

DMAC2 (complete, error)

ICR12

38C

000FFF8C

DMAC3 (complete, error)

ICR13

388

000FFF88

DMAC4 (complete, error)

ICR14

384

000FFF84

DMAC5 (complete, error)

ICR15

380

000FFF80

MB91106 Series

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

DMAC6 (complete, error)

ICR16

37C

000FFF7C

DMAC7 (complete, error)

ICR17

378

000FFF78

A/D converter (successive
approximation conversion type)

ICR18

374

000FFF74

16-bit reload timer 0

ICR19

370

000FFF70

16-bit reload timer 1

ICR20

36C

000FFF6C

16-bit reload timer 2

ICR21

368

000FFF68

PWM 0

ICR22

364

000FFF64

PWM 1

ICR23

360

000FFF60

PWM 2

ICR24

35C

000FFF5C

PWM 3

ICR25

358

000FFF58

U-TIMER 0

ICR26

354

000FFF54

U-TIMER 1

ICR27

350

000FFF50

U-TIMER 2

ICR28

34C

000FFF4C

Reserved for system

ICR29

348

000FFF48

Reserved for system

ICR30

344

000FFF44

Reserved for system

ICR31

340

000FFF40

Reserved for system

33C

000FFF3C

Reserved for system

338

000FFF38

Reserved for system

334

000FFF34

Reserved for system

330

000FFF30

Reserved for system

32C

000FFF2C

Reserved for system

328

000FFF28

Reserved for system

324

000FFF24

Reserved for system

320

000FFF20

Reserved for system

31C

000FFF1C

Reserved for system

318

000FFF18

Reserved for system

314

000FFF14

Reserved for system

310

000FFF10

Reserved for system

30C

000FFF0C

Reserved for system

308

000FFF08

Reserved for system

304

000FFF04

Delayed interrupt cause bit

ICR47

300

000FFF00

MB91106 Series

PERIPHERAL RESOURCES

I/O Ports

There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register
(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on
the register corresponds to an external pin. In port registers input/output register of the port configures input/
output function of the port, while corresponding bit (pin) configures input/output function in data direction
registers. Bit "0" specifies input and "1" specifies output.

· For input (DDR = "0") setting;

PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.

· For output (DDR = "1") setting;

PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.

(1) Register configuration

· Port data register

bit 7

bit 0

000001

000000

000007

000006

000005

000004

00000B

000009

000008

000012

000013

X X X X X X X X

- - - - - - - X

- - X X X X X X

- X X X X X X X

X X X X X X X X

Address

Initial value

: Access
: Readable and writable
: Indeterminate

(R/W)

( )

R/W

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDRA

PDRB

PDRE

PDRF

MB91106 Series

(2) Block diagram

( )
W

· Data direction register

: Access
: Write only
: Unused

bit 7

bit 0

000601

000600

000607

000606

000605

000604

00060B

000609

000608

0000D2

0000D3

0 0 0 0 0 0 0 0

- - - - - - - 0

- - 0 0 0 0 0 0

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

Address

Initial value

(W)

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDRA

DDRB

DDRE

DDRF

PDR read

PDR

(Port data register)

DDR

(Data direction register)

Data b

Resource input

Resource output

Resource output enable

MB91106 Series

DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to
enhanced performance of the system.

· 8 channels
· Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
· Transfer all through the area
· Max. 65536 of transfer cycles
· Interrupt function right after the transfer
· Selectable for address transfer increase/decrease by the software
· External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

(1) Registers configuration

· DMAC internal registers

bit 31

bit 0

Address
00000200

X X X X X X X X

X 0 0 0 0 0 0 0

Initial value

: Access
: Readable and writable
: Indeterminate

DPDP

( )

R/W

DACSR

DATCR

(R/W)

· DMAC parameter descriptor pointer

· DMAC control status register

· DMAC pin control register

bit 31

bit 0

bit 31

bit 0

Address

00000208

0 0 0 0 0 0 0 0

Initial value

X X X X X X X X

X X 0 0 0 0 0 0

Initial value

Address
00000204

MB91106 Series

UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK
synchronous communication, and it has the following features.

The MB91106 consists of 3 channels of UART.

· Full double double buffer
· Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
· Supporting multi-processor mode
· Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section "4. U-TIMER").

· Any baud rate can be set by external clock.
· Error checking function (parity, framing and overrun)
· Transfer signal: NRZ code
· Enable DMA transfer/start by interrupt.

(1) Register configuration

· Serial control register 0 to 2

Initial value

0 0 0 0 0 1 0 0

bit 15

bit 0

bit 8 bit 7

SCR0 to SCR2

SMR

(R/W)

Address

· Serial model register 0 to 2

Initial value

0 0 - - 0 - 0 0

bit 15

bit 0

bit 8 bit 7

(SCR)

SMR0 to SMR2

(R/W)

SMR0 : 00001F

SMR1 : 000023

SMR2 : 000027

· Serial status register 0 to 2

Initial value

0 0 0 0 1 - 0 0

bit 15

bit 0

bit 8 bit 7

SSR0 to SSR2

SID

(R/W)

SSR0 : 00001C

SSR1 : 000020

SSR2 : 000024

· Serial input data register 0 to 2

Initial value

X X X X X X X X

bit 15

bit 0

bit 8 bit 7

(SSR)

SIDR0 to SIDR2

(R)

: Access
: Readable and writable
: Unused
: Indeterminate

( )

R/W

SCR0 : 00001E

SCR1 : 000022

SCR2 : 000026

Address

SIDR0 : 00001D

SIDR1 : 000021

SIDR2 : 000025

Address

· Serial output data register 0 to 2

Initial value

X X X X X X X X

bit 15

bit 0

bit 8 bit 7

(SSR)

SODR0 to SODR2

(W)

SODR0 : 00001D

SODR1 : 000021

SODR2 : 000025

Address

MB91106 Series

(2) Block diagram

Control signals

From U-TIMER

From external clock

SI
(receive data)

Clock select

circuit

Receive clock

Transmit clock

Receive interrupt
(to CPU)

SC (clock)

Transmit interrupt
(to CPU)

Receive control circuit

Start bit detect

circuit

Receive bit counter

Receive parity

counter

Transmit control circuit

Transmit start

circuit

Transmit bit counter

Transmit parity

counter

SO (transmit data)

Receive status

judge circuit

Receive error
generate signal
for DMA
(to DMAC)

Receive shifter

Serial input data register

SIDR

Receive
complete

Transmit shifter

Serial output data register

SIDR

Transmit
start

R-bus

Serial register

(SMR)

MD1
MD0

CS0

SCKE
SOE

Serial control

(SCR)

PEN
P
SBL
CL
A/D
REC
RXE
TXE

Serial status

(SSR)

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

Control signals

MB91106 Series

U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91106 has 3 channel U-TIMER embedded on the chip. When used as an interval timer, two cupple of
U-TIMER (ch0, ch1) can be cascaded and an interva of up to 2

can be counted.

(1) Register configuration

(2) Block diagram

· U-TIMER register ch.0 to ch.2

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

bit 15

bit 0

UTIM0 to UTIM2

(R)

UTIM0 : 00000078

UTIM1 : 0000007C

UTIM2 : 00000080

Address

· U-TIMER reload register ch.0 to ch.2

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

bit 15

bit 0

UTIMR0 to UTIMR2

(W)

UTIMR0 : 00000078

UTIMR1 : 0000007C

UTIMR2 : 00000080

Address

· U-TIMER control register ch.0 to ch.2

bit 15

bit 0

UTIMC0 to UTIMC2

: Access
: Readable and writable
: Unused

( )

R/W

UTIMC0 : 0000007B

UTIMC1 : 0000007F

UTIMC2 : 00000083

Address

(Vacancy)

bit 8 bit 7

Initial value

0 - - 0 0 0 0 1

(R/W)

bit 15

bit 0

Reload register (U-TIMER)

bit 15

bit 0

U-TIMER register (UTIM)

Load

(Peripheral clock)

MUX

(ch.0 only)

Underflow

U-TIMER

Clock

Underflow

U-TIMER control register

(UTIMC)

f.f.

To UART

MB91106 Series

PWM Timer

The PWM timer can output high accurate PWM waves efficiently.

MB91106 has inner 4-channel PWM timers, and has the following features.

· Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-

bit compare resister with a buffer for duty setting, and a pin controller.

· The count clock of a 16-bit down counter can be selected from the following four inner clocks.

Inner clock

/4,

/16,

/64

· The counter value can be initialized "FFFF

" by the resetting or the counter borrow.

· PWM output (each channel)

MB91106 Series

(1) Register configuration

bit 15

bit 0

bit 8 bit 7

(Vacancy)

GCN2

: Access
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate

( )

R/W

· Control status register H0 to 3

Initial value

0 0 0 0 0 0 0 -

bit 15

bit 0

bit 8 bit 7

PCNH0 to PCNH3

(PCNL)

(R/W)

Address

PCNH0 : 0000E6

PCNH1 : 0000EE

PCNH2 : 0000F6

PCNH3 : 0000FE

· Control status register L0 to 3

Initial value

0 0 0 0 0 0 0 0

bit 15

bit 0

(PCNH)

PCNL0 to PCNL3

(R/W)

Address

PCNL0 : 0000E7

PCNL1 : 0000EF

PCNL2 : 0000F7

PCNL3 : 0000FF

· PWM cycle setting register 0 to 3

Initial value

X X X X X X X X

bit 15

bit 0

PCSR0 to PCSR3

(W)

Address

PCSR0 : 0000E2

PCSR1 : 0000EA

PCSR2 : 0000F2

PCSR3 : 0000FA

· PWM duty setting register 0 to 3

bit 15

bit 0

PDUT0 to PDUT3

Address

PDUT0 : 0000E4

PDUT1 : 0000EC

PDUT2 : 0000F4

PDUT3 : 0000FC

Initial value

X X X X X X X X
X X X X X X X X

(W)

· PWM timer register 0 to 3

bit 15

bit 0

PTMR0 to PTMR3

Address

PTMR0 : 0000E0

PTMR1 : 0000E8

PTMR2 : 0000F0

PTMR3 : 0000F8

Initial value

1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1

(R)

· General control register 1, 2

bit 15

bit 0

GCN1

Address

GCN1 : 0000DC

Initial value

0 0 1 1 0 0 1 0
0 0 0 1 0 0 0 0

(R/W)

Address

GCN1 : 0000DF

Initial value

0 0 0 0 0 0 0 0

(R/W)

MB91106 Series

(2) Block diagram

· Block diagram (general construction)

· Block diagram (for one channel)

16-bit reload timer

ch.0

16-bit reload timer

ch.1

General control

External TRG0 to TRG3

General control

(cause selection)

TRG input

PWM timer ch.0

TRG input

PWM timer ch.1

TRG input

PWM timer ch.2

TRG input

PWM timer ch.3

PWM0

PWM1

PWM2

PWM3

Prescaler

1 / 1
1 / 4

1 / 16
1 / 64

PWM cycle

setting register

(PCSR)

PWM duty

setting register

(PDUT)

Load

16-bit down counter

Start

Borrow

cmp

Peripheral clock

TRG input

Enable

Edge detect

Soft trigger

PPG mask

Reverse bit

PWM output

IRQ

Interr

upt

selection

MB91106 Series

16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating
internal count clock and control registers.

Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).

The DMA transfer can be started by the interruption.

The MB91106 consists of 3 channels of the 16-bit reload timer.

(1) Register configuration

· 16-bit reload timer control status register 0 to 2

Initial value

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

bit 15

bit 0

TMCSR0 to TMCSR2

(R/W)

TMCSR0 : 00002E

TMCSR1 : 000036

TMCSR2 : 000042

Address

· 16-bit timer register 0 to 2

bit 15

bit 0

TMR0 to TMR2

TMR0 : 00002A

TMR1 : 000032

TMR2 : 00003E

Address

· 16-bit reload register 0 to 2

bit 15

bit 0

TMRLR0 to TMRLR2

TMRLR0 : 000028

TMRLR1 : 000030

TMRLR2 : 00003C

Address

Initial value

X X X X X X X X
X X X X X X X X

(R)

Initial value

X X X X X X X X
X X X X X X X X

(W)

: Access
: Readable and writable
: Read Only
: Write Only
: Unused
: Indeterminate

( )

R/W

MB91106 Series

Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.

(1) Register configuration

(2) Block diagram

: Access
: Readable and writable
: Read only
: Write only
: Indeterminate

( )

R/W

· Bit search module 0, 1-detection data register

bit 31

bit 0

BSD0, BSD1

BSD0 : 000003F0

BSD1 : 000003F4

Address

Initial value

X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X

(R/W)

· Bit search module transition-detection data register

bit 31

bit 0

BSDC

000003F8

Address

Initial value

X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X

(W)

· Bit search module detection result register

bit 31

bit 0

BSRR

Address

Initial value

X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X

(R)

000003FC

D-b

Input latch

Address
decoder

Single-detection data recovery

Search result register (BSRR)

Bit search circuit

Detection

mode

MB91106 Series

10-bit A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.

· Minimum converting time: 5.6

s/ch. (system clock: 25 MHz)

· Inner sample and hold circuit
· Resolution: 10 bits
· Analog input can be selected from 4 channels by program.

Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronising at

the beginning of conversion can be peformed.

· DMA transfer operation is available by interruption.
· Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer

(rising edge).

(1) Register configuration

: Access
: Readable and writable
: Read only
: Unused
: Indeterminate

( )

R/W

· A/D converter control status register

bit 15

bit 0

ADCS

Address

0000003A

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

(R/W)

· A/D converter data register

bit 15

bit 0

ADCR

Address

00000038

Initial value

0 0 0 0 0 0 X X
X X X X X X X X

(R)

MB91106 Series

Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

· Hardware Configuration

Interrupt controller is configured by ICR resistor, interrupt priority decision circuit, interrupt level, vector
generation and HLDREQ cancel request, and has the following functions.

· Main Functions

NMI request/Interrupt request detection
Priority (judgement) decision (via level and vector)
Transfer of judged interrupt level to CPU
Transfer of judged interrupt vector to CPU
Return instruction from the stop mode via NMI/interrupt
Generation of HOLD request cancel request to the bus timer

MB91106 Series

(1) Register configuration

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

bit 7

bit 0

00000400

00000401

00000402

00000403

00000404

00000405

00000406

00000407

00000408

00000409

0000040A

0000040B

0000040C

0000040D

0000040E

0000040F

00000410

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

Address

Initial value

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR47

bit 7

bit 0

00000411

00000412

00000413

00000414

00000415

00000416

00000417

00000418

00000419

0000041A

0000041B

0000041C

0000041D

0000041E

0000041F

0000042F

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

- - - 11111

(R/W)

Address

Initial value

: Access
: Redable and writable
: Unused

( )

R/W

· Hold request cancel request level setting register

bit 7

bit 0

HRCL

Address

00000431

Initial value

- - - 1 1 1 1 1

(R/W)

· Interrupt control register 0 to 31, 47

MB91106 Series

(2) Block diagram

*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed Interrupt

Module" for detail).

*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3: HLDCAN is a bus release request signal for bus masters other than CPU.

*4: LEVEL5 to LEVEL0 are interrupt level outputs.

*5: VCT5 to VCT0 are interrupt vector outputs.

R-bus

NMI processing

Priority judgment

LEVEL4 to

LEVEL0*

VCT5 to

VCT0*

HLDCAN*

ICR47

ICR00

Vector judgment

RI00

RI47

·
·

(DLYIRQ)

NMI

HLDREQ

cancel

request

Level,

vector

generation

Level judgment

DLYI*

INT0*

MB91106 Series

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0
to INT3 pins.

Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin).

(1) Register configuration

(2) Block diagram

: Access
: Redable and writable

( )

R/W

· Interrupt enable register

bit 15

bit 0

(EIRR)

Address

00000095

Initial value

0 0 0 0 0 0 0 0

(R/W)

ENIR

· External interrupt cause register

bit 15

bit 0

EIRR

Address

00000094

(ENIR)

· External interrupt request level setting register

bit 15

bit 0

ELVR

Address

00000099

bit 7

bit 8

Initial value

0 0 0 0 0 0 0 0

(R/W)

Initial value

0 0 0 0 0 0 0 0

(R/W)

Interrupt enable register (ENIR)

R-b

Interrupt
request

External interrupt cause register (EIRR)

External interrupt request level setting register (ELVR)

Gate

Cause F/F

Edge detection circuit

INT0 to INT3
NMI

MB91106 Series

12. Clock Generation (Low-power consumption mechanism)

The clock control block is a module which undertakes the following functions.

· CPU clock generation (including gear function)
· Peripheral clock generation (including gear function)
· Reset generation and cause hold
· Standby function
· DMA request prohibit
· PLL (multiplier circuit) embedded

(1) Register configuration

· Reset cause register/watchdog cycle control register

bit 15

bit 0

RSRR

Address

00000480

Initial value

1 X X X X - 0 0

(R/W)

(STCR)

· Standby control register

bit 15

bit 0

(RSRR/WTCR)

Address

00000481

(STCR)

bit 9 bit 8

bit 7

Initial value

0 0 0 1 1 1 - -

(R/W)

· DMA controller request squelch register

bit 15

bit 0

PDRR

Address

00000482

(CTBR)

bit 8

Initial value

- - - - 0 0 0 0

(R/W)

bit 10

WTCR

· Timebase timer clear register

bit 15

bit 0

(PDRR)

Address

00000483

CTBR

bit 7

· Gear control register

bit 15

bit 0

GCR

Address

00000484

(WPR)

bit 8

Initial value

X X X X X X X X

(W)

Initial value

1 1 0 0 1 1 - 1

(R/W)

· Watchdog reset occurrence postpone register

bit 15

bit 0

(GCR)

Address

00000485

WPR

bit 7

Initial value

X X X X X X X X

(W)

· PLL control register

bit 15

bit 0

PCTR

Address

00000488

(Vacancy)

bit 8

Initial value

0 0 - - 0 - - -

(R/W)

: Access
: Readable and writable
: Read Only
: Write Only
: Unused
: Indeterminate

( )

R/W

MB91106 Series

(2) Block diagram

[Gear control block]

CPU clock

Gear control register (GCR)

Internal bus clock

External bus clock
Peripheral
DMA clock
Internal
peripheral clock

CPU gear

Internal clock

generation

circuit

Peripheral

gear

PLL control register

(PCTR)

PLL

1/2

Selection

circuit

R-b

Oscillator

circuit

X0
X1

STOP state

SLEEP state

CPU hold request

Internal reset

Status

transition

control circuit

Reset

generation

F/F

Standby control

[DMA prohibit circuit]

[Stop/sleep control block]

DMA request prohibit

Reset cause register (RSRR)

[Reset cause circuit]

[Watchdog control block]

Watchdog reset generation

postpone register (WPR)

Timebase timer clear

Watchdog reset

postpone register F/F

Timebase time

Count clock

Internal

interrupt request
Internal reset

CPU hold enable

DMA

request

Power on sel

RST pin

MB91106 Series

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.

· 25-bit (32 Mbytes) address output
· 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes

6 area setting is available by the address pin and the chip select pin.

· 8/16-bit bus width setting are available for every chip select area.
· Programmable automatic memory wait (max. for 7 cycles) can be inserted.
· DRAM interface support

Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM
Hyper DRAM

2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable wave form

· Unused address/data pin can be used for I/O port.
· Little endian mode supported
· Clock doublure: Internal bus 50 MHz, external bus 25 MHz (at source oscillation 12.5 MHz)

MB91106 Series

(1) Register configuration

: Access
: Redable and writable
: Write only
: Unused
: Indeterminate

( )

R/W

· Area select register 1 to 5

bit 15

bit 0

ASR1

Address

0000060C

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1

ASR2

00000610

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 2

ASR3

00000614

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 3

ASR4

00000618

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 4

ASR5

0000061C

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 5

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

(W)

bit 15

bit 0

AMR1 to AMR5

Address

AMR1 : 0000060E

AMR2 : 00000612

AMR3 : 00000616

AMR4 : 0000061A

AMR5 : 0000061E

· Area mask register 1 to 5

bit 15

bit 0

bit 8 bit 7

AMD0

AMD1

bit 15

bit 0

bit 8 bit 7

(AMD5)

DSCR

· Area mode register 0, 1, 32, 4, 5

Initial value

- - - 0 0 1 1 1

0 - - 0 0 0 0 0

(R/W)

AMD0 : 00000620

AMD1 : 00000621

Address

AMD32

AMD4

AMD32 : 00000622

AMD4 : 00000623

0 0 0 0 0 0 0 0
0 - - 0 0 0 0 0

AMD5

(DSCR)

AMD5 : 00000624

· DRAM signle control register

Address

00000625

Initial value

0 0 0 0 0 0 0 0

(W)

bit 15

bit 0

RFCR

· Refresh control register

Address

00000626

Initial value

- - X X X X X X

0 0 - - - 0 0 0

(R/W)

bit 15

bit 0

EPCR0

· External pin control register 0, 1

Address

EPCR0 : 00000628

Initial value

- - - - 1 1 0 0
- 1 1 1 1 1 1 1

(W)

bit 15

bit 0

DMCR4, DMCR5

Address

DMCR4 : 0000062C

DMCR5 : 0000062E

EPCR1

- - - - - - - 1

1 1 1 1 1 1 1 1

EPCR1 : 0000062A

· DRAM control register 4, 5

bit 15

bit 0

bit 8 bit 7

LER

(MODR)

Address

000007FE

· Litter endian register

bit 15

bit 0

bit 8 bit 7

(LER)

MODR

Address

000007FF

· Mode register

Initial value

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 -

(R/W)

Initial value

- - - - - 0 0 0

(W)

Initial value

X X X X X X X X

(W)

0 - - 0 0 0 0 0

(R/W)

(W)

MB91106 Series

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

= AV

= 0.0 V)

*1: V

must not be less than V

0.3 V.

*2: Make sure that the voltage does not exceed V

+ 0.3 V, such as when turning on the device.

*3: Maximum output current is a peak current value measured at a corresponding pin.
*4: Average output current is an average current for a 100 ms period at a corresponding pin.
*5: Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

0.3

+ 4.0

Analog supply voltage

0.3

+ 4.0

Analog reference voltage

AVRH

0.3

+ 4.0

Analog pin input voltage

0.3

+ 0.3

Input voltage

0.3

+ 0.3

Output voltage

0.3

+ 0.3

"L" level maximum output current

"L" level average output current

OLAV

"L" level maximum total output current

100

"L" level average total output current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level maximum total output current

"H" level average total output current

OHAV

Power consumption

500

Operating temperature

+70

Storage temperature

Tstg

+150

MB91106 Series

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

(V)

Fc
(MHz)

CPP

(MHz)

CPP

(MHz)

CPP

12.5

3.6

3.0

0.625

External clock

Self-oscillation

PLL system (12.5MHz(Fixed) 4 multiplication)

Divide-by-2 system

Normal operation warranty range (T

= 0

C to +70

Net masked area are f

CPP

Supply v

ltage

Max. inter

al cloc

k frequency setting

Notes:

When using PLL, the external clock must be used need 12.5 MHz.

PLL oscillation stabilizing period > 100

The setting of internal clock must be within above ranges.

Peripheral

Internal clock

CPU

· Normal operation warranty rage

· External/Internal clock setting rage

12.5

MB91106 Series

DC Characteristics

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input
voltage

Input pin except
for hysteresis
input

0.7

+ 0.3

IHS

NMI, RST,
P40 to P47,
P50 to P57,
P60 to P67,
P70, P81,
P83 to P85,
PA0 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7

0.8

+ 0.3

Hysteresis
input

"L" level input
voltage

Input other than
following
symbols

0.3

0.25

ILS

NMI, RST,
P40 to P47,
P50 to P57,
P60 to P67,
P70, P81,
P83 to P85,
PA0 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7

0.3

0.2

Hysteresis
input

"H" level output
voltage

P2 to PF

= 3.0 V

= 4.0 mA

0.5

"L" level output
voltage

P8 to PF

= 3.0 V

= 8.0 mA

0.4

Input leakage
current
(Hi-Z output
leakage current)

P2 to PF

= 3.6 V

0.45 V < V

< V

Pull-up
resistance

PULL

RST

= 3.6 V

= 0.45 V

100

Power supply
current

= 12.5 MHz

= 3.3 V

150

(4 multiplication)

Operation at
50 MHz

CCS

= 12.5 MHz

= 3.3 V

mA Sleep mode

CCH

= +25

= 3.3 V

1.4

150

A Stop mode

Input
capacitance

Except for V

, AV

, V

MB91106 Series

(2) Clock Timing Rating

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock

multiplication system.

*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and

a 1/8 gear.

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Clock frequency

X0, X1

Self-oscillation at
12.5 MHz
Internal operation
at 50 MHz (Via
PLL,quadruplex)

12.5

MHz

X0, X1

Self-oscillation
(divide-by-2 input)

MHz

X0, X1

External clock
(divide-by-2 input)

MHz

Clock cycle time

X0, X1

Self-oscillation at
12.5 MHz
Internal operation
at 50 MHz (Via
PLL,quadruplex)

X0, X1

100

Frequency shift ratio
(when locked)

Self-oscillation at
12.5 MHz
Internal operation
at 50 MHz (Via
PLL,quadruplex)

Input clock pulse width

X0, X1

12.5 MHz to
25.0 MHz

Input clock
pulse to X0
and X1

12.5 MHz and less

Input clock
pulse to X0
only

Input clock rising/falling time

X0, X1

+ t

)

Internal operating clock
frequency

CPU system

0.625*

MHz

CPP

Peripheral system

0.625*

MHz

Internal operating clock
cycle time

CPU system

1600*

CPP

Peripheral system

1600*

Center frequency

f =

100 (%)

MB91106 Series

(3) Clock Output Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

(internal operating clock cycle time), see "(2) Clock Timing Rating."

*2: t

CYC

is a frequency for 1 clock cycle including a gear cycle.

Use the doublure when CPU frequency is above 25 MHz.

*3: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : (1 n/2)

CYC

Max. : (1 n/2)

CYC

+ 10

Select a gear cycle of

1 when using the doublure.

*4: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : n/2

CYC

Max. : n/2

CYC

+ 10

Select a gear cycle of

1 when using the doublure.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Cycle time

CYC

CLK

CYC

CLK

Using the
doublure

CLK

CHCL

CLK

1/2

CYC

1/2

CYC

+ 5

CLK

CLCH

CLK

1/2

CYC

1/2

CYC

+ 5

CLK

CYC

CHCL

CLCH

MB91106 Series

The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows:

However, in this chart source oscillation input means X0 input clock.

Source oscillation input
(when using the doublure)

(1) PLL system
(CHC bit of GCR set to "0")

(a) Gear

1 CLK pin

CCK1/0: "00"

Source oscillation input

(2) 2 dividing system
(CHC bit of GCR set to "1")

(a) Gear

1 CLK pin

CCK1/0: "00"

(b) Gear

1/2 CLK pin

CCK1/0: "01"

1/4 CLK pin

CCK1/0: "10"

(d) Gear

1/8 CLK pin

CCK1/0: "11"

CYC

MB91106 Series

· Discreet type

( ): C

and C

internally connected 3 contacts type.

Oscillation frequency

[MHz]

Model

Load capacitance

= C

[pF]

Power supply voltage

[V]

5.00 to 6.30

CSA

2.9 to 5.5

CST

MGW

(30)

CSA

MG093

2.7 to 5.5

CST

MGW093

(30)

6.31 to 10.0

CSA

MTZ

2.9 to 5.5

CST

MTW

(30)

CSA

MTZ093

2.7 to 5.5

CST

MTW093

(30)

10.1 to 13.0

CSA

MTZ

3.0 to 5.5

CST

MTW

(30)

CSA

MTZ093

2.9 to 5.5

CST

MTW093

(30)

13.01 to 15.00

CSA

MXZ040

3.2 to 5.5

CST

MXW0C3

(15)

· Ceramic oscillator applications

Recommended circuit (2 contacts)

Recommended circuit (3 contacts)

* : Murata Mfg. Co., Ltd.

, C

internally

connected.

MB91106 Series

(5) Power on Supply Specifications (Power-on Reset)

(AV

= V

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

* : For information on t

(clock cycle time), see "(2) Clock Timing Rating."

Parameter

Symbol Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Power supply rising time

= 3.3 V

< 0.2 V

before the
power supply
rising

Power supply shut off time

OFF

Repeated
operations

Oscillation stabilizing time

OSC

+ 100

Notes:

Set RST pin to

"L" level when turning on the device, at least the described above duration after the

supply voltage reaches Vcc is necessary before turning the RST to "H" level.

Some internal resistors which are initialized only via power on reset are embedded in the device.
To initialize these resistors, run power on reset by returning on the power supply.

OFF

OSC

0.8 V

Note: Sudden change in supply voltage during operation may initiate a power-on sequence.

To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid
fluctuations in the supply voltage.

RST

RSTL

: Reset input time

RSTL

+ (

)

336 ms approx. (@12.5 MHz)

(Oscillation stabilizing time)

0.2 V

A voltage rising rate of 50 mV/ms or
less is recommended.

0.9 V

MB91106 Series

(6) Normal Bus Access Read/write Operation

(AV

= V

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

*2: When bus timing is delayed by automatic wait insertion or RDY input, add (t

CYC

extended cycle number for

delay) to this rating.

*3: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation: (2 n/2)

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

CS0 to CS5 delay time

CHCSL

CLK,
CS0 to CS5

CHCSH

CLK,
CS0 to CS5

Address delay time

CHAV

CLK,
A24 to A00

Data delay time

CHDV

CLK,
D31 to D16

RD delay time

CLRL

CLK, RD

CLRH

CLK, RD

WR0, WR1 delay time

CLWL

CLK,
WR0, WR1

CLWH

CLK,
WR0, WR1

Valid address

valid data

input time

AVDV

A24 to A00,
D31 to D16

3/2

CYC

*2
*3

valid data input time t

RLDV

RD,
D31 to D16

CYC

Data set up

time

DSRH

RD,
D31 to D16

data hold time

RHDX

RD,
D31 to D16

MB91106 Series

(8) Hold Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

* : For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

BGRNT delay time

CHBGL

CLK,
BGRNT

CHBGH

CLK,
BGRNT

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

* 10

CYC

* + 10

BGRNT

pin valid time

HAHV

BGRNT

CYC

* 10

CYC

* + 10

Each pin

0.8 V

2.4 V

CYC

CHBGL

BRQ

BGRNT

CLK

CHBGH

HAHV

XHAL

High impedance

2.4 V

MB91106 Series

(9) Normal DRAM Mode Read/Write Cycle

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

*2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.

*3: When Q1 cycle or Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

*4: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation: (3 n/2)

CYC

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CHRAL

CLK, RAS

CAS delay time

CLCASL

CLK, CS0H,
CS1H, CS0L,
CS1L

CLCASH

CLK, CS0H,
CS1H, CS0L,
CS1L

ROW address delay time

CHRAV

CLK,
A24 to A00

COLUMN address delay
time

CHCAV

CLK,
A24 to A00

DW delay time

CHDWL

CLK, DW*

CHDWH

CLK, DW*

Output data delay time

CHDV1

CLK,
D31 to D16

RAS

valid data input

time

RLDV

RAS,
D31 to D16

5/2

CYC

*3
*4

CAS

valid data input

time

CLDV

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

CYC

CAS

data hold time

CADH

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

MB91106 Series

(10) Normal DRAM Mode Fast Page Read/Write Cycle

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

*2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.

*3: When Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CAS delay time

CLCASL

CLK, CS0H,
CS1H, CS0L,
CS1L

CLCASH

CLK, CS0H,
CS1H, CS0L,
CS1L

COLUMN address delay
time

CHCAV

CLK,
A24 to A00

DW delay time

CHDWH

CLK, DW*

Output data delay time

CHDV1

CLK,
D31 to D16

CAS

valid data input

time

CLDV

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

CYC

CAS

data hold time

CADH

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

MB91106 Series

(11) Single DRAM Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

*2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH2

CLK, RAS

CHRAL2

CLK, RAS

CAS delay time

CHCASL2

CLK, CS0H,
CS1H, CS0L,
CS1L

n/2

CYC

CHCASH2

CLK, CS0H,
CS1H, CS0L,
CS1L

ROW address delay time

CHRAV2

CLK,
A24 to A00

COLUMN address delay
time

CHCAV2

CLK,
A24 to A00

DW delay time

CHDWL2

CLK, DW*

CHDWH2

CLK, DW*

Output data delay time

CHDV2

CLK,
D31 to D16

CAS

Valid data input

time

CLDV2

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

(1 n/2)

CYC

CAS

data hold time

CADH2

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

MB91106 Series

*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2: indicates the timing when the bus cycle begins from the high spead page mode.

CLK

RAS

CS0H,
CS1H,

CS0L,
CS1L,

A24 to A00

D31 to D16

Q4S

CYC

2.4 V

0.8 V

2.4 V

0.8 V

CLRAH2

CHCASL2

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

CHRAV2

CHCAV2

ROW address

COLUMN-1

CLDV2

CADH2

2.4 V

Read-1

2.4 V

0.8 V

CHDWL2

CHDWH2

2.4 V

0.8 V

Write-0

(Read)

(Write)

Q4S

2.4 V

CHRAL2

CHCASH2

2.4 V

0.8 V

COLUMN-2

0.8 V

COLUMN-0

Read-2

0.8 V

2.4 V

0.8 V

Read-0

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Write-2

CHDV2

Write-1

MB91106 Series

(12) Hyper DRAM Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

*1: For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

*2: DW expresses that DW0, DW1 and CS0H, CS1H are used for WE.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH3

CLK, RAS

CHRAL3

CLK, RAS

CAS delay time

CHCASL3

CLK, CS0H,
CS1H, CS0L,
CS1L

n/2

CYC

CHCASH3

CLK, CS0H,
CS1H, CS0L,
CS1L

ROW address delay time

CHRAV3

CLK,
A24 to A00

COLUMN address delay
time

CHCAV3

CLK,
A24 to A00

RD delay time

CHRL3

CLK, RD

CHRH3

CLK, RD

CLRL3

CLK, RD

DW delay time

CHDWL3

CLK, DW*

CHDWH3

CLK, DW*

Output data delay time

CHDV3

CLK,
D31 to D16

CAS

valid data input

time

CLDV3

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

CYC

CAS

data hold time

CADH3

CS0H, CS1H,
CS0L, CS1L,
D31 to D16

MB91106 Series

*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2: indicates the timing when the bus cycle begins from the high spead page mode.

CLK

RAS

CS0H,
CS1H,

CS0L,
CS1L,

A24 to A00

D31 to D16

Q4H

CYC

2.4 V

0.8 V

2.4 V

0.8 V

CLRAH3

CHCASL3

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

CHRAV3

CHCAV3

ROW address

COLUMN-1

CLDV3

CADH3

2.4 V

Read-1

2.4 V

0.8 V

CHDWH3

2.4 V

0.8 V

(Read)

(Write)

Q4H

2.4 V

CHRAL3

CHCASH3

2.4 V

0.8 V

COLUMN-2

0.8 V

COLUMN-0

0.8 V

2.4 V
0.8 V

Read-0

2.4 V

0.8 V

2.4 V

0.8 V

Write-2

CHDV3

Write-1

0.8 V

(Read)

2.4 V

0.8 V

CLRL3

CHRH3

CHDWL3

Write-0

CHDV3

CHRL3

MB91106 Series

(13) CBR Refresh

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CHRAL

CLK, RAS

CAS delay time

CLCASL

CLK, CS0H,
CS1H, CS0L,
CS1L

CLCASH

CLK, CS0H,
CS1H, CS0L,
CS1L

CLK

RAS

CS0H,
CS1H,

CS0L,
CS1L,

CYC

2.4 V

0.8 V

2.4 V

0.8 V

CLRAH

CHRAL

0.8 V

2.4 V

0.8 V

CLCASL

CLCASH

MB91106 Series

(15) UART Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

* : For information on t

CYCP

(a cycle time of peripheral system clock), see "(2) Clock Timing Rating."

Notes: This rating is for AC characteristics in CLK synchronous mode.

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

Serial clock cycle time

SCYC

Internal
shift clock
mode

CYCP

SCLK

SOUT delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

valid SIN hold

time

SHIX

Serial clock "H" pulse width

SHSL

External
shift clock
mode

CYCP

Serial clock "L" pulse width

SLSH

CYCP

SCLK

SOUT delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

valid SIN hold

time

SHIX

· Internal shift clock mode

· External shift clock mode

SCLK

SOUT

SCYC

0.8 V

2.4 V
0.8 V

SIN

2.4 V

0.8 V

SHIX

IVSH

0.8 V

0.2 V

0.8 V

0.2 V

SCLK

SOUT

SLSH

2.4 V
0.8 V

SIN

SHIX

IVSH

0.8 V

0.2 V

0.8 V

0.2 V

SHSL

0.8 V

(2.6V)

0.2 V

(0.7V)

0.2 V

(0.7V)

SLOV

0.8 V

(2.6V)

SLOV

MB91106 Series

(17) DMA Controller Timing

= 3.0 V to 3.6 V,

= AV

= 0.0 V, T

= 0

C to +70

* : For information on t

CYC

(a cycle time of peripheral system clock), see "(3) Clock Output Timing."

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

DREQ input pulse width t

DRWH

DREQ0 to DREQ2

CYC

DACK delay time
(Normal bus)
(Normal DRAM)

CLDL

CLK,
DACK0 to DACK2

CLDH

CLK,
DACK0 to DACK2

EOP delay time
(Normal bus)
(Normal DRAM)

CLEL

CLK,
EOP0 to EOP2

CLEH

CLK,
EOP0 to EOP2

DACK delay time
(Single DRAM)
(Hyper DRAM)

CHDL

CLK,
DACK0 to DACK2

n/2

CYC

CHDH

CLK,
DACK0 to DACK2

EOP delay time
(Single DRAM)
(Hyper DRAM)

CHEL

CLK,
EOP0 to EOP2

n/2

CYC

CHEH

CLK,
EOP0 to EOP2

CLK

DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)

CYC

2.4 V

0.8 V

2.4 V

0.8 V

CLDL

0.8 V

2.4 V

CLEL

CLDH

CLEH

2.4 V

CHDL

CHEL

DRWH

CHDH

DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)

DREQ0 to DREQ2

MB91106 Series

A/D Converter Block Electrical Characteristics

= AV

= 3.0 V to 3.6 V, V

= AV

= 0.0 V, AVRH = 3.0 V to 3.6 V, T

= 0

C to +70

*1: V

= AV

= 3.0 V to 3.6 V, machine clock 25 MHz

*2: Current value for A/D converters not in operation, CPU stop mode (V

= AV

= AVRH = 3.6 V)

Parameter

Symbol

Pin name

Value

Unit

Min.

Typ.

Max.

Resolution

bit

Total error

3.0

LSB

Linearity error

2.5

LSB

Differentiation linearity error

1.9

LSB

Zero transition voltage

AN0 to AN3

1.5LSB

+0.5LSB

+2.5LSB

Full-scale transition voltage

FST

AN0 to AN3

AVRH

4.5LSB

AVRH

1.5LSB

AVRH +

0.5LSB

Conversion time

5.6 *

Analog port input current

AIN

AN0 to AN3

0.1

Analog input voltage

AIN

AN0 to AN3

AVRH

Reference voltage

AVRH

Power supply current

5 *

Reference voltage supply current

AVRH

110

AVRH

5 *

Conversion variance between channels

AN0 to AN3

LSB

MB91106 Series

A/D Converter Glossary

· Resolution

The smallest change in analog voltage detected by A/D converter.

· Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000
0000"

"00 0000 0001") to the full-scale transition point (between "11 1111 1110"

"11 1111 1111").

· Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage.

· Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error, full-
scale transition error and linearity error.

(Continued)

3FF

3FE

3FD

004

003

002

001

Total error

1.5 LSB'

Actual conversion
characteristic

{1 LSB'

(N 1)

+ 0.5 LSB'}

(measured value)

Actual conversion
characteristic

Ideal characteristic

AVRL

AVRH

Analog input

0.5 LSB'

Digital output

Total error of digital output N =

{1 LSB'

(N 1) + 0.5 LSB'}

1 LSB'

[LSB]

' (ideal value) = AVRL + 0.5 LSB' [V]

FST

' (ideal value) = AVRL 1.5 LSB' [V]

: A voltage for causing transition of digital output from (N 1) to N

MB91106 Series

(Continued)

3FF

3FE

3FD

004

003

002

001

Linearity error

Actual conversion
characteristic

{1 LSB

(N 1) + V

}

(measured value)

Actual conversion
characteristic

Ideal characteristic

AVRL

AVRH

Analog input

Digital output

Linearity error of

{1 LSB'

(N 1) + V

}

1 LSB

[LSB]

FST

(measured
value)

(measured value)

N+1

Differential Iinearity error

Actual characteristic

(measured value)

Actual conversion characteristic

AVRL

AVRH

Analog input

Digital output

Ideal characteristic

(measured value)

(N + 1)T

digital output N

Differential Iinearity error

(N + 1)T

1 LSB

1 [LSB]

of digital output N =

1 LSB' (ideal value)

AVRH AVRL

1022

[V]

1 LSB

FST

1022

[V]

: A voltage for causing transition of digital output from (000)

to (001)

FST

: A voltage for causing transition of digital output from (3FE)

to (3FF)

: A voltage for causing transition of digital output from (N 1)

to N

MB91106 Series

Notes on Using A/D Converter

Output impedance of external circuit of analog input under following conditions;
Output impedance of external circuit < 7 k

If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate
sampling (sampling time is 5.6

s for a machine clock of 25 MHz).

ON1

· Analog input Equivalent Circuit

Analog input pin

Sample hold circuit

Comparator

ON2

ON3

ON4

ON1

ON2

ON3

ON4

ON1

: 5 k

ON2

: 620 k

ON3

: 620 k

ON4

: 620 k

: 2 pF

· Error

As the absolute value of AVRH decreases, relative error increases.

MB91106 Series

EXAMPLE CHARACTERISTICS

(1) "H" Level Output Voltage

(3) "H" Level Input Voltage/"L" Level
Input Voltage (CMOS Input)

(2) "L" Level Output Voltage

(4) "H" Level Input Voltage/"L" Level
Input Voltage (Hysteresis Input)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

(V)

-I

= 3.6 V

= 3.3 V

= 3.0 V

= 2.7 V

(mA)

= +25

-1

-2

-3

-4

-5

-6

-7

-8

0.25

0.20

0.15

0.10

0.05

0.00

(V)

-I

= 2.7 V

= 3.0 V

= 3.3 V

= 3.6 V

(mA)

= +25

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

(V)

-V

(V)

= +25

2.4

2.7

3.0

3.3

3.6

: Threshold when input voltage is set to "H" Level.

: Threshold when input voltage is set to "L" Level.

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

(V)

-V

(V)

= +25

2.4

2.7

3.0

3.3

3.6

: Threshold when input voltage in hysteresis

characteristics is set to "H" Level.

: Threshold when input voltage in hysteresis

characteristics is set to "L" Level.

MB91106 Series

(5) Power Supply Current (fcp = Internal clock frequency)

(6) Pull-up Resistance

100

(mA)

= +25

2.7

3.0

3.3

-V

= 50 MHz

= 40 MHz

= 20 MHz

= 10 MHz

3.6

3.9

CCS

(mA)

= +25

2.7

3.0

3.3

CCS

-V

= 50 MHz

= 40 MHz

= 20 MHz

= 10 MHz

3.6

3.9

2.7

3.0

3.3

3.6

3.9

(mA)

= +25

-AV

2.5

2.0

1.5

1.0

0.5

0.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

CCH

(

= +25

2.7

3.0

3.3

CCH

-V

3.6

(V)

2.7

3.0

3.3

3.6

3.9

= +25

(V)

-AV

(

130

125

120

115

110

105

100

= +25

2.7

3.0

3.3

3.6

3.9

(V)

R-V

R (k

)

100

MB91106 Series

INSTRUCTIONS (165 INSTRUCTIONS)

How to Read Instruction Set Summary

(1) Names of instructions

Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.

(2) Addressing modes specified as operands are listed in symbols.

Refer to "2. Addressing mode symbols" for further information.

(3) Instruction types

(4) Hexa-decimal expressions of instructions

(5) The number of machine cycles needed for execution

a: Memory access cycle and it has possibility of delay by Ready function.

b: Memory access cycle and it has possibility of delay by Ready function.

If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.

c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or

if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number

of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

For a, b, c and d, minimum execution cycle is 1.

(6) Change in flag sign

· Flag change

C : Change
: No change
0 : Clear
1 : Set

· Flag meanings

N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag

(7) Operation carried out by instruction

Mnemonic

Type

CYC

NZVC

Operation

Remarks

ADD

Rj,

* ADD

#s5,

,
,

A6
A4

,
,

1
1

,
,

CCCC
CCCC

,
,

Ri + Rj

Ri + s5

,
,

(1)

(2)

(3)

(4)

(5)

(6)

(7)

MB91106 Series

Addressing Mode Symbols

: Register direct (R0 to R15, AC, FP, SP)

R13

: Register direct (R13, AC)

: Register direct (Program status register)

: Register direct (TBR, RP, SSP, USP, MDH, MDL)

CRi

: Register direct (CR0 to CR15)

CRj

: Register direct (CR0 to CR15)

#i8

: Unsigned 8-bit immediate (128 to 255)

Note: 128 to 1 are interpreted as 128 to 255

#i20

: Unsigned 20-bit immediate (0X80000 to 0XFFFFF)

Note: 0X7FFFF to 1 are interpreted as 0X7FFFF to 0XFFFFF

#i32

: Unsigned 32-bit immediate (0X80000000 to 0XFFFFFFFF)

Note: 0X80000000 to 1 are interpreted as 0X80000000 to 0XFFFFFFFF

#s5

: Signed 5-bit immediate (16 to 15)

#s10

: Signed 10-bit immediate (512 to 508, multiple of 4 only)

#u4

: Unsigned 4-bit immediate (0 to 15)

#u5

: Unsigned 5-bit immediate (0 to 31)

#u8

: Unsigned 8-bit immediate (0 to 255)

#u10

: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)

@dir8

: Unsigned 8-bit direct address (0 to 0XFF)

@dir9

: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10

: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

label9

: Signed 9-bit branch address (0X100 to 0XFC, multiple of 2 only)

label12

: Signed 12-bit branch address (0X800 to 0X7FC, multiple of 2 only)

label20

: Signed 20-bit branch address (0X80000 to 0X7FFFF)

label32

: Signed 32-bit branch address (0X80000000 to 0X7FFFFFFF)

@Ri

: Register indirect (R0 to R15, AC, FP, SP)

@Rj

: Register indirect (R0 to R15, AC, FP, SP)

@(R13, Rj)

: Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14, disp10) : Register relative indirect (disp10: 0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: 0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: 0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+

: Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+

: Register indirect with post-increment (R13, AC)

@SP+

: Stack pop

@SP

: Stack push

(reglist)

: Register list

101

MB91106 Series

Detailed Description of Instructions

· Add/subtract operation instructions (10 instructions)

· Compare operation instructions (3 instructions)

· Logical operation instructions (12 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

ADD

Rj, Ri

* ADD

#s5, Ri

ADD

#i4, Ri

ADD2

#i4, Ri

C
C

A6
A4

A4
A5

1
1

C C C C
C C C C

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

ADDC

Rj, Ri

C C C C Ri + Rj + c

Add operation with
sign

ADDN

Rj, Ri

* ADDN

#s5, Ri

ADDN

#i4, Ri

ADDN2

#i4, Ri

C
C

A2
A0

A0
A1

1
1

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

SUB

Rj, Ri

C C C C Ri Rj

SUBC

Rj, Ri

C C C C Ri Rj c

Subtract operation with
carry

SUBN

Rj, Ri

Ri Rj

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

CMP

Rj, Ri

* CMP

#s5, Ri

CMP

#i4, Ri

CMP2

#i4, Ri

C
C

A8
A9

1
1

C C C C
C C C C

Ri Rj
Ri s5

Ri + extu (i4)
Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

AND

Rj, Ri

AND

Rj, @Ri

ANDH

Rj, @Ri

ANDB

Rj, @Ri

A
A
A
A

82
84
85
86

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri & = Rj
(Ri) & = Rj
(Ri) & = Rj
(Ri) & = Rj

Word
Word
Half word
Byte

Rj, Ri

Rj, @Ri

ORH

Rj, @Ri

ORB

Rj, @Ri

A
A
A
A

92
94
95
96

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri | = Rj
(Ri) | = Rj
(Ri) | = Rj
(Ri) | = Rj

Word
Word
Half word
Byte

EOR

Rj, Ri

EOR

Rj, @Ri

EORH

Rj, @Ri

EORB

Rj, @Ri

A
A
A
A

9C
9D

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj

Word
Word
Half word
Byte

MB91106 Series

102

· Bit manipulation arithmetic instructions (8 instructions)

*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH
may be generated.

*2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BORH if "u8&0xF0" leaves an active bit.

*3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BEORH if "u8&0xF0" leaves an active bit.

· Add/subtract operation instructions (10 instructions)

*1: DIVOS, DIV1

32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.

*2: DIVOU and DIV1

32 are generated. A total instruction code length of 66 bytes.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

BANDL

#u4, @Ri(u4: 0 to 0F

)

BANDH

#u4, @Ri(u4: 0 to 0F

)

* BAND

#u8, @Ri

C
C

80
81

1 + 2a
1 + 2a

(Ri) & = (F0

+ u4)

(Ri) & = ((u4<<4) + 0F

)

(Ri) & = u8

Manipulate lower 4 bits
Manipulate upper 4
bits

BORL

#u4, @Ri(u4: 0 to 0F

)

BORH

#u4, @Ri(u4: 0 to 0F

)

* BOR

#u8, @Ri

C
C

90
91

1 + 2a
1 + 2a

(Ri) | = u4
(Ri) | = (u4<<4)
(Ri) | = u8

Manipulate lower 4 bits
Manipulate upper 4
bits

BEORL

#u4, @Ri(u4: 0 to 0F

)

BEORH

#u4, @Ri(u4: 0 to 0F

)

* BEOR

#u8, @Ri

C
C

98
99

1 + 2a
1 + 2a

(Ri) ^ = u4
(Ri) ^ = (u4<<4)
(Ri) ^ = u8

Manipulate lower 4 bits
Manipulate upper 4
bits

BTSTL

#u4, @Ri(u4: 0 to 0F

)

BTSTH

#u4, @Ri(u4: 0 to 0F

)

C
C

88
89

2 + a
2 + a

0 C

C C

(Ri) & u4
(Ri) & (u4<<4)

Test lower 4 bits
Test upper 4 bits

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MUL

Rj, Ri

MULU

Rj, Ri

MULH

Rj, Ri

MULUH

Rj, Ri

A
A
A
A

5
5
3
3

C C C
C C C
C C
C C

MDH, MDL

MDL

32-bit

32-bit = 64-bit

Unsigned
16-bit

16-bit = 32-bit

Unsigned

DIVOS

DIVOU

DIV1

DIV2

DIV3
DIV4S
* DIV

* DIVU

E
E
E
E
E
E

97 4
97 5
97 6
97 7

9F 6
9F 7

1
1
d
1
1
1

C C
C C

C C

C C

MDL/Ri

MDL,

MDL%Ri

MDH

MDL/Ri

MDL,

MDL%Ri

MDH

Step calculation
32-bit/32-bit = 32-bit

Unsigned

103

MB91106 Series

· Shift arithmetic instructions (9 instructions)

· Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer

instruction) (3 instructions)

*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.

If an immediate value contains relative value or external reference, assembler selects i32.

· Memory load instructions (13 instructions)

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LSL

Rj, Ri

* LSL

#u5, Ri

LSL

#u4, Ri

LSL2

#u4, Ri

C
C

B6
B4
B4
B5

1
1
1
1

C C C
C C C
C C C
C C C

Ri<<Rj

Ri<<u5

Ri<<u4

Ri<<(u4 + 16)

Logical shift

LSR

Rj, Ri

* LSR

#u5, Ri

LSR

#u4, Ri

LSR2

#u4, Ri

C
C

B2
B0
B0
B1

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

ASR

Rj, Ri

* ASR

#u5, Ri

ASR

#u4, Ri

ASR2

#u4, Ri

C
C

B8
B8
B9

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDI: 32

#i32, Ri

LDI: 20

#i20, Ri

LDI: 8

#i8, Ri

* LDI

# {i8 | i20 | i32}, Ri

9F 8

3
2

i32

i20

{i8 | i20 | i32}

Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

@Rj, Ri

@(R13, Rj), Ri

@(R14, disp10), Ri

@(R15, udisp6), Ri

@R15 +, Ri

@R15 +, Rs

@R15 +, PS

A
A
B

E
E

04
00
20
03

07 0
07 8

07 9

b
b
b
b
b
b

1 + a + b

C C C C

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + udisp6)

(R15)

Ri, R15 + = 4

(R15)

Rs, R15 + = 4

(R15)

PS, R15 + = 4

Rs: Special-purpose

LDUH

@Rj, Ri

LDUH

@(R13, Rj), Ri

LDUH

@(R14, disp9), Ri

A
A
B

05
01
40

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp9)

Zero-extension
Zero-extension
Zero-extension

LDUB

@Rj, Ri

LDUB

@(R13, Rj), Ri

LDUB

@(R14, disp8), Ri

A
A
B

06
02
60

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp8)

Zero-extension
Zero-extension
Zero-extension

disp8

o8 = disp8

disp9

o8 = disp9>>1

disp10

o8 = disp10>>2

udisp6

u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

MB91106 Series

104

· Memory store instructions (13 instructions)

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

· Transfer instructions between registers/special-purpose registers transfer instructions

(5 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

Ri, @Rj

Ri, @(R13, Rj)

Ri, @(R14, disp10)

Ri, @(R15, udisp6)

Ri, @R15

Rs, @R15

PS, @R15

A
A
B

E
E

14
10
30
13

17 0
17 8

17 9

a
a
a
a
a
a

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + usidp6)

R15 = 4, Ri

(R15)

R15 = 4, Rs

(R15)

R15 = 4, PS

(R15)

Word
Word
Word

Rs: Special-purpose

STH

Ri, @Rj

STH

Ri, @(R13, Rj)

STH

Ri, @(R14, disp9)

A
A
B

15
11
50

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp9)

Half word
Half word
Half word

STB

Ri, @Rj

STB

Ri, @(R13, Rj)

STB

Ri, @(R14, disp8)

A
A
B

16
12
70

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp8)

Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MOV

Rj, Ri

MOV

Rs, Ri

MOV

Ri, Rs

MOV

PS, Ri

MOV

Ri, PS

E
E

17 1
07 1

C C C C

Transfer between
general-purpose
registers
Rs: Special-purpose

Rs: Special-purpose

disp8

o8 = disp8

disp9

o8 = disp9>>1

disp10

o8 = disp10>>2

udisp6

u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

105

MB91106 Series

· Non-delay normal branch instructions (23 instructions)

Notes: · "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.

· The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.
label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· RETI must be operated while S flag = 0.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP

@Ri

97 0

CALL

label12

CALL

@Ri

97 1

PC + 2

RP,

PC + 2 + rel11

PC + 2

RP, Ri

RET

97 2

Return

INT

#u8

3+3a

SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

I flag,

S flag,

(TBR + 3FC u8

INTE

9F 3 3 + 3a SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

S flag,

(TBR + 3D8 u8

For emulator

RETI

97 3 2 + 2a C C C C (R15)

PC, R15 = 4,

(R15)

PS, R15 = 4

BNO

label9

BRA

label9

BEQ

label9

BNE

label9

BNC

label9

BNV

label9

BLT

label9

BGE

label9

BLE

label9

BGT

label9

BLS

label9

BHI

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

E1
E0
E2
E3
E4
E5
E6
E7
E8
E9

EA
EB

EC
ED

1
2

2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1

Non-branch
PC + 2 + rel8

PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0

MB91106 Series

106

· Branch instructions with delays (20 instructions)

Notes: · The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.

label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· Delayed branch operation always executes next instruction (delay slot) before making a branch.
· Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other

instruction is stored, this device may operate other operation than defined.

The instruction described "1" in the other cycle column than branch instruction.
The instruction described "a", "b", "c" or "d" in the cycle column.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP:D

@Ri

9F 0

CALL:D

label12

CALL:D

@Ri

9F 1

PC + 4

RP,

PC + 2 + rel11

PC + 4

RP, Ri

RET:D

9F 2

Return

BNO:D

label9

BRA:D

label9

BEQ:D

label9

BNE:D

label9

BC:D

label9

BNC:D

label9

BN:D

label9

BP:D

label9

BV:D

label9

BNV:D

label9

BLT:D

label9

BGE:D

label9

BLE:D

label9

BGT:D

label9

BLS:D

label9

BHI:D

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

F1
F0
F2
F3
F4
F5
F6
F7
F8
F9

FA
FB

FC
FD

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Non-branch
PC + 2 + rel8

107

MB91106 Series

· Direct addressing instructions

Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from

disp8 to disp10 are as follows:

· Resource instructions (2 instructions)

· Co-processor instructions (4 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

DMOV

@dir10, R13

DMOV

R13, @dir10

DMOV

@dir10, @R13+

DMOV

@R13+, @dir10

DMOV

@dir10, @R15

DMOV

@R15+, @dir10

D
D
D
D
D
D

08
18

0C
1C

0B
1B

b
a

2a
2a
2a
2a

(dir10)

R13

(dir10)

(R13), R13 + = 4

(R13)

(dir10), R13 + = 4

R15 = 4, (dir10)

(R15)

(dir10), R15 = 4

Word
Word
Word
Word
Word
Word

DMOVH

@dir9,

R13

DMOVH

R13, @dir9

DMOVH

@dir9,

@R13+

DMOVH

@R13+, @dir9

D
D
D
D

09
19

0D
1D

b
a

2a
2a

(dir9)

R13

(dir9)

(R13), R13 + = 2

(R13)

(dir9), R13 + = 2

Half word
Half word
Half word
Half word

DMOVB

@dir8,

R13

DMOVB

R13, @dir8

DMOVB

@dir8,

@R13+

DMOVB

@R13+, @dir8

D
D
D
D

0A
1A
0E
1E

b
a

2a
2a

(dir8)

R13

(dir8)

(R13), R13 + +

(R13)

(dir8), R13 + +

Byte
Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDRES

@Ri+,

#u4

(Ri)

u4 resource

Ri + = 4

u4: Channel number

STRES

#u4, @Ri+

resource

(Ri)

Ri + = 4

u4: Channel number

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

COPOP

#u4, #CC, CRj, CRi

COPLD

#u4, #CC, Rj,

CRi

COPST

#u4, #CC, CRj, Ri

COPSV

#u4, #CC, CRj, Ri

E
E
E
E

9F C
9F D
9F E
9F F

2 + a

1 + 2a
1 + 2a
1 + 2a

Calculation
Rj

CRi

CRj

No error traps

disp8

dir + disp8

disp9

dir = disp9>>1

disp10

dir = disp10>>2

Each disp is a code extension

MB91106 Series

108

· Other instructions (16 instructions)

*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler

description s10 is as follows.
s10

s8 = s10>>2

*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler

description u10 is as follows.
u10

u8 = u10>>2

*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,

assembler generates LDM1. Both LDM0 and LDM1 may be generated.

*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following

calculation; a

(n 1) + b + 1 when "n" is number of registers specified.

*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,

assembler generates STM1. Both STM0 and STM1 may be generated.

*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following

calculation; a

n + 1 when "n" is number of registers specified.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

NOP

9F A

No changes

ANDCCR #u8
ORCCR

#u8

D
D

83
93

c
c

C C C C
C C C C

CCR and u8

CCR

CCR or u8

CCR

STILM

#u8

ILM

Set ILM immediate
value

ADDSP

#s10

R15 + = s10

ADD SP instruction

EXTSB

EXTUB

EXTSH

EXTUH

E
E
E
E

97 8
97 9

97 A
97 B

1
1
1
1

Sign extension 8

32 bits

Zero extension 8

32 bits

Sign extension 16

32 bits

Zero extension 16

32 bits

LDM0

(reglist)

LDM1

(reglist)

* LDM

(reglist)

(R15)

reglist,

R15 increment
(R15)

reglist,

R15 increment
(R15 + +)

reglist,

Load-multi R0 to R7

Load-multi R8 to R15

Load-multi R0 to R15

STM0

(reglist)

STM1

(reglist)

* STM2

(reglist)

R15 decrement,
reglist

(R15)

R15 decrement,
reglist

(R15)

reglist

(R15 + +)

Store-multi R0 to R7

Store-multi R8 to R15

Store-multi R0 to R15

ENTER

#u10

1+a

R14

(R15 4),

R15 4

R14,

R15 u10

R15

Entrance processing
of function

LEAVE

9F 9

R14 + 4

R15,

(R15 4)

R14

Exit processing of
function

XCHB

@Rj, Ri

TEMP,

(Rj)

Ri,

TEMP

(Rj)

For SEMAFO
management
Byte data

109

MB91106 Series

· 20-bit normal branch macro instructions

*1: CALL20

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL

@Ri

*2: BRA20

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP

@Ri

*3: Bcc20 (BEQ20 to BHI20)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20

label20, Ri

Next instruction address

RP, label20

Ri: Temporary register

* BRA20

label20, Ri

* BEQ20

label20, Ri

* BNE20

label20, Ri

* BC20

label20, Ri

* BNC20

label20, Ri

* BN20

label20, Ri

* BP20

label20, Ri

* BV20

label20, Ri

* BNV20

label20, Ri

* BLT20

label20, Ri

* BGE20

label20, Ri

* BLE20

label20, Ri

* BGT20

label20, Ri

* BLS20

label20, Ri

* BHI20

label20, Ri

label20

if (Z = = 1) then label20

ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0

Ri: Temporary register

MB91106 Series

110

· 20-bit delayed branch macro instructions

*1: CALL20:D

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL:D @Ri

*2: BRA20:D

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP:D

@Ri

*3: Bcc20:D (BEQ20:D to BHI20:D)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20:D label20, Ri

Next instruction address + 2

RP, label20

Ri: Temporary register

* BRA20:D label20, Ri
* BEQ20:D label20, Ri
* BNE20:D label20, Ri
* BC20:D

label20, Ri

* BNC20:D label20, Ri
* BN20:D

label20, Ri

* BP20:D

label20, Ri

* BV20:D

label20, Ri

* BNV20:D label20, Ri
* BLT20:D

label20, Ri

* BGE20:D label20, Ri
* BLE20:D

label20, Ri

* BGT20:D label20, Ri
* BLS20:D

label20, Ri

* BHI20:D

label20, Ri

label20

if (Z = = 1) then label20

Ri: Temporary register

111

MB91106 Series

· 32-bit normal macro branch instructions

*1: CALL32

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL

@Ri

*2: BRA32

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP

@Ri

*3: Bcc32 (BEQ32 to BHI32)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32

label32, Ri

Next instruction address

RP, label32

Ri: Temporary register

* BRA32

label32, Ri

* BEQ32

label32, Ri

* BNE32

label32, Ri

* BC32

label32, Ri

* BNC32

label32, Ri

* BN32

label32, Ri

* BP32

label32, Ri

* BV32

label32, Ri

* BNV32

label32, Ri

* BLT32

label32, Ri

* BGE32

label32, Ri

* BLE32

label32, Ri

* BGT32

label32, Ri

* BLS32

label32, Ri

* BHI32

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

MB91106 Series

112

· 32-bit delayed macro branch instructions

*1: CALL32:D

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL:D @Ri

*2: BRA32:D

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP:D

@Ri

*3: Bcc32:D (BEQ32:D to BHI32:D)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32:D label32, Ri

Next instruction address + 2

RP, label32

Ri: Temporary register

* BRA32:D label32, Ri
* BEQ32:D label32, Ri
* BNE32:D label32, Ri
* BC32:D

label32, Ri

* BNC32:D label32, Ri
* BN32:D

label32, Ri

* BP32:D

label32, Ri

* BV32:D

label32, Ri

* BNV32:D label32, Ri
* BLT32:D

label32, Ri

* BGE32:D label32, Ri
* BLE32:D

label32, Ri

* BGT32:D label32, Ri
* BLS32:D

label32, Ri

* BHI32:D

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

115

MB91106 Series

Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device.

1994 FUJITSU LIMITED F100008-3C-2

"A"

"B"

0.10(.004)

0.53(.021)MAX

0.18(.007)MAX

Details of "A" part

0 10°

Details of "B" part

12.35(.486)

REF

16.30±0.40

(.642±.016)

0.05(.002)MIN

(STAND OFF)

0.15±0.05(.006±.002)

INDEX

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

17.90±0.40

14.00±0.20

(.551±.008)

(.705±.016)

0.13(.005)

18.85(.742)REF

22.30±0.40(.878±.016)

100

0.25(.010)

0.30(.012)

0.65(.0256)TYP

0.30±0.10

(.012±.004)

LEAD No.

0.80±0.20

(.031±.008)

3.35(.132)MAX

(Mounting height)

Dimensions in mm (inches)

(FPT-100P-M06)

100-pin Plastic QFP

MB91106 Series

116

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9901

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91106PFV

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91106PFV