DS07-16305-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit RISC Microcontroller

CMOS

FR Series

MB91107/108

DESCRIPTION

The MB91107 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU,
the MB91107 normally operates in the external bus access mode and executes instructions on the internal
1 Kbyte cache memory and RAM (MB91107: 128 Kbytes, MB91108: 160 Kbytes) for enhanced performance.

The MB91107 is optimized for applications requiring high-performance CPU processing such as navigation sys-
tems, high-performance FAXs and printer controllers.

*: FR Family stands for FUJITSU RISC controller.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture, 5-stage pipeline
· Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
· General purpose registers: 32 bits

· 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
· Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
· Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

(Continued)

PACKAGE

120-pin Plastic LQFP

(FPT-120P-M21)

MB91107/108

(Continued)

· Register interlock functions, efficient assembly language coding
· Branch instructions with delay slots: Reduced overhead time in branch executions
· Internal multiplier/supported at instruction level

Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles

· Interrupt (push PC and PS): 6 cycles, 16 priority levels

Bus interface

· Clock doubler: Internal 50 MHz, external bus 25 MHz operation
· 25-bit address bus (32 Mbytes memory space)
· 8/16-bit data bus
· Basic external bus cycle: 2 clock cycles
· Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 8
· Interface supported for various memory technologies

DRAM interface (area 4 and 5)

· Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
· Unused data/address pins can be configured us input/output ports
· Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

· 2 banks independent control (area 4 and 5)
· Double CAS DRAM (normal DRAM I/F) / Single CAS DRAM / Hyper DRAM
· Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
· Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
· DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode

· Supports 8/9/10/12-bit column address width
· 2CAS/1WE, 2WE/1CAS selective

Cache memory

· 1-Kbyte instruction cache memory
· 2 way set associative
· 32 block/way, 4 entry(4 word)/block
· Lock function: For specific program code to be resident in cache memory

DMAC (DMA controller)

· 8 channels
· Transfer incident/external pins/internal resource interrupt requests
· Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
· Transfer data length: 8 bits/16 bits/32 bits selective
· NMI/interrupt request enables temporary stop operation

UART

· 3 independent channels
· Full-duplex double buffer
· Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
· Asynchronous (start-stop system), CLK-synchronized communication selective
· Multi-processor mode
· Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate

(Continued)

MB91107/108

(Continued)

· Use external clock can be used as a transfer clock
· Error detection: Parity, frame, overrun

10-bit A/D converter (successive approximation conversion type)

· 10-bit resolution, 4 channels
· Successive approximation type: Conversion time of 5.6

s at 25 MHz

· Internal sample and hold circuit
· Conversion mode: Single conversion/scanning conversion/repeated conversion selective
· Start: Software/external trigger/internal timer selective

16-bit reload timer

· 16-bit timer: 3 channels
· Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective

Other interval timers

· 16-bit timer: 3 channels (U-TIMER)
· PWM timer: 4 channels
· Watchdog timer: 1 channel

Bit search module

First bit transition "1" or "0" from MSB can be detected in 1 cycle

Interrupt controller

· External interrupt input: Non-maskable interrupt (NMI), normal interrupt 8 (INT0 to INT7)
· Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt

module

· Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 levels)

Others

· Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
· Low-power consumption mode: Sleep mode/stop mode
· Clock control

Gear function:Operating clocks for CPU and peripherals are independently selective

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
However, operating frequency for peripherals is less than 25 MHz.

· Packages: LQFP-120
· CMOS technology (0.35

m): MB91V108 (0.25

·····

Development model

MB91107 (0.25

·····

Production model

MB91108 (0.25

·····

Production model

· Power supply voltage: 3.3 V

0.3 V (internal regulator)

MB91107/108

PIN ASSIGNMENT

(TOP VIEW)

(FPT-120P-M21)

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

PB5/CS1L

PB6/CS1H

PB7/DW1

CS0

PA1/CS1
PA2/CS2
PA3/CS3
PA4/CS4
PA5/CS5
PA6/CLK

NMI

HST
RST

MD0
MD1
MD2

P80/RDY

P81/BGRNT

P82/BRQ

WR0

P85/WR1

P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21

PG5/INT5
PG4/INT4
PG3/INT3
PG2/INT2
PG1/INT1
PG0/INT0
V

PH7/OCPA3
PH6/OCPA2
PH5/OCPA1
PH4/OCPA0
PH3/TRG3/CS7
PH2/TRG2/CS6
PH1/TRG1
PH0/TRG0
AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24/P70
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

RAS1/PB4

DW0/PB3

CS0H/PB2

CS0L/PB1

RAS0/PB0

PI1/EOP2/ATG

PI0/DACK2

PE7/DREQ2

PE6/EOP1

PE5/DACK1

PE4/DREQ1

PE3/EOP0

PE2/DACK0

PE1/DREQ0

PE0/SC2

PF7/SO2

PF6/SI2

PF5/SC1

PF4/SO1

PF3/SI1

PF2/SC0

PF1/SO0

PF0/SI0

PG7/INT7

PG6/INT6

P26/D22

P27/D23

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

P60/A16

MB91107/108

PIN DESCRIPTION

(Continued)

Pin no.

Pin name

Circuit

type

Function

85
86
87
88
89
90
91
92

D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27

Bit 16 to bit 23 of external data bus.
Can be configured as ports (P20 to P27) when external data bus width is
set to 8-bit.

93
94
95
96
97
98
99

100

D24
D25
D26
D27
D28
D29
D30
D31

Bit 24 to bit 31 of external data bus.

102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118

A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15

Bit 00 to bit 15 of external address bus.

120

1
2
3
4
5
6
7

A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67

Bit 16 to bit 23 of external address bus.
Can be configured as ports(P60 to P67) when not used as address bus.

A24/P70

Bit 24 of external address bus.
Can be configured as a port(P70) when not used as address bus.

RDY/P80

External ready input.
Inputs "0" when bus cycle is being executed and not completed.
Can be configured as a port when this pin is not used.

MB91107/108

(Continued)

Pin no.

Pin name

Circuit

type

Function

BGRNT/P81

External bus release acknowledge output.
Outputs "L" level when external bus is released.
Can be configured as a port when this pin is not used.

BRQ/P82

External bus release request input.
Inputs "1" when release of external bus is required.
Can be configured as a port when this pin is not used.

Read strobe output pin for external bus.

WR0

Write strobe output pin for external bus. Relation between control signals
and effective byte locations is as follows:

Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister

when using at 16-bit bus width.

WR1/P85

CS0

Chip select 0 output ("L" active).

66
67
68
69
70

CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5

Chip select 1 output ("L" active).
Chip select 2 output ("L" active).
Chip select 3 output ("L" active).
Chip select 4 output ("L" active).
Chip select 5 output ("L" active).
Can be configured as ports when PA1 to PA5 are not used.

CLK/PA6

System clock output.
Outputs clock signal of external bus operating frequency.
Can be configured as a port when PA6 is not used.

56
57
58
59
60
61
62
63

RAS0/PB0

CS0L/PB1

CS0H/PB2

DW0/PB3

RAS1/PB4

CS1L/PB5

CS1H/PB6

DW1/PB7

RAS output for DRAM bank 0.
CASL output for DRAM bank 0.
CASH output for DRAM bank 0.
WE output for DRAM bank 0 ("L" active).
RAS output for DRAM bank 1.
CASL output for DRAM bank 1.
CASH output for DRAM bank 1.
WE output for DRAM bank 1 ("L" active)
Can be configured as a port when PB0 to PB7 are not used.

76
77
78

MD0
MD1
MD2

Mode pins 0 to 2.
MCU basic operation mode is set by these pins.
Directly connect these pins with V

or V

for use.

53
54

X1
X0

Clock (oscillator) output.
Clock (oscillator) input.

RST

External reset input.

HST

Hardware standby input ("L" active).

16-bit bus width

8-bit bus width

D31 to

D24

WR0

D23 to

D16

WR1

(I/O port enabled)

Refer to the
DRAM interface
for details.

MB91107/108

(Continued)

Pin no.

Pin name

Circuit

type

Function

NMI

NMI (non-maskable interrupt pin) input ("L" active).

SC2/PE0

(SC2)

Clock I/O pin for UART2.

Clock output is available when clock output of UART2 is enabled.

(PE0) General purpose I/O port.
This function is available when UART2 clock output is disabled.

DREQ0/PE1

(DREQ0)

External transfer request input pins for DMA. This pin is used

for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.

(PE1) General purpose I/O port.

DACK0/PE2

(DACK0) External transfer request acknowledge output pin for DMAC
(ch. 0). This function is available when transfer request output for DMAC
is enabled.

(PE2) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK0 output is disabled.

EOP0/PE3

(EOP0) Can be configured as DMAC EOP OUTPUT (ch.0) when DMAC
EOP output is enable.

(PE3) General purpose I/O port.

DREQ1/PE4

(DREQ1) External transfer request input pins for DMA. This pin is used
for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.

(PE4) General purpose I/O port.

DACK1/PE5

(DACK1) External transfer request acknowledge output pin for DMAC
(ch. 1). This function is available when transfer request output for DMAC
is enabled.

(PE5) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK1 output is disabled.

EOP1/PE6

(EOP1) Can be configured as DMAC EOP OUTPUT (ch.1) when DMAC
EOP output is enable.

(PE6) General purpose I/O port.

DREQ2/PE7

(DREQ2) External transfer request input pins for DMA.
This pin is used for input when external trigger is selected to cause
DMAC operation, and it is necessary to disable output for other functions
from this pin unless such output is made intentionally.

(PE7) General purpose I/O port.

MB91107/108

(Continued)

Pin no.

Pin name

Circuit

type

Function

SI0/PF0

(SI0) UART0 data input pin.
This pin is used for input during UART0 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.

(PF0) General purpose I/O port.

SO0/PF1

(SO0) UART0 data output pin.
This function is available when UART0 data output is enabled.

(PF1) General purpose I/O port.
This function is available when UART0 data output is disabled.

SC0/PF2

(SC0) UART0 clock I/O pin.
Clock output is available when UART0 clock output is enabled.

(PF2) General purpose I/O port.
This function is available when UART0 clock output is disabled.

SI1/PF3

(SI1) UART1 data input pin.
This pin is used for input during UART1 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.

(PF3) General purpose I/O port.

SO1/PF4

(SO1) UART1 data output pin.
This function is available when UART1 data output is enabled.

(PF4) General purpose I/O port.
This function is available when UART1 data output is disabled.

SC1/PF5

(SC1) Clock I/O pin for UART1.
Clock output is available when clock output of UART1 is enabled.

(PF5) General purpose I/O port.
This function is available when UART1 clock output is disabled.

SI2/PF6

(SI2) UART2 data input pin.
This pin is used for input during UART2 is in input operation, and it is
necessary to disable output for other functions from this pin unless such
output is made intentionally.

(PF6) General purpose I/O port.

SO2/PF7

(SO2) UART2 data output pin.
This function is available when UART2 data output is enabled.

(PF7) General purpose I/O port.
This function is available when UART2 data output is disabled.

MB91107/108

(Continued)

Pin no.

Pin name

Circuit

type

Function

25
26
27
28
29
30
31
32

INT0/PG0
INT1/PG1
INT2/PG2
INT3/PG3
INT4/PG4
INT5/PG5
INT6/PG6
INT7/PG7

(INT0 to INT7) External interrupt request input pin.
This pin is used for input during corresponding interrupt is enabled, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.

(PG0 and PG7) General purpose I/O port.

16
17

TRG0/PH0
TRG1/PH1

(TRG0 and TRG1) PWM timer external trigger input pin.
This function is available when PH0 and PH1 data outputs are disabled.

(PH0 and PH1) General purpose I/O port.

18
19

TRG2/PH2/

CS6

TRG3/PH3/

CS7

(TRG2 and TRG3) PWM timer external trigger input pin.
This function is available when PH2 and PH3 data outputs are disabled.

(PH2 and PH3) Can be configured as a I/O port when TRG2, TRG3,
CS6 and CS7 are not used.

Chip select 6 output ("L" active).
Chip select 7 output ("L" active).

20
21
22
23

OCPA0/PH4
OCPA1/PH5
OCPA2/PH6
OCPA3/PH7

(OCPA0 to OCPA3) PWM timer output pin.
This function is available when PWM timer output is enabled.

(PH4 to PH7) General purpose I/O port.

DACK2/PI0

(DACK2) External transfer request acknowledge output pin for DMAC
(ch. 2). This function is available when transfer request output for DMAC
is enabled.

(PI0) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK2 output is disabled.

EOP2/PI1/

ATG

(EOP2) EOP output pin for DMAC (ch.1).
This function is available when EOP output for DMAC is enabled.

(PI1) General purpose I/O port.
This function is available when transfer complete acknowledge output
for DMAC output is disabled.

(ATG)External trigger input pin for A/D converter.
This pin is used for input when external trigger is selected to cause A/D
converter operation, and it is necessary to disable output for other func-
tions from this pin unless such output is made intentionally.

12 to 15

AN0 to AN3

(AN0 to AN3) Analog input pins of A/D converter.
This function is available when AIC register is set to specify analog input
mode.

Power supply pin (V

) for A/D converter.

AVRH

Reference voltage input (high) for A/D converter.
Make sure to turn on and off this pin with potential of AVRH or more ap-
plied to V

MB91107/108

(Continued)

Note : In most of the above pins, I/O port and resource I/O are multiplexed e.g. xxx/Pxxx. In case of conflict between

output of I/O port and resource I/O, priority is always given to the output of resource I/O.

DRAM CONTROL REGISTER

Pin no.

Pin name

Circuit

type

Function

/ AVRL

Power supply pin (V

) for A/D converter and reference voltage input pin

(low).

24, 55,

110

Power supply pin (V

) for digital circuit.

Always three pins must be connected to the power supply

Bypass capacitor pin for internal capacitor.
Refer to the HANDLING DEVICES.

34, 52, 75,

101, 119

Earth level (V

) for digital circuit.

Pin

name

Data bus 16-bit mode

Data bus 8-bit

mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

RAS0

Area 4 RAS

Correspondence of "L" "H" to lower ad-
dress 1 bit (A0) in data bus 16-bit mode.

"L": "0"
"H": "1"

CASL : CAS which A0 corresponds to "0"

area

CASH : CAS which A0 corresponds to "1"

area

WEL : WE which A0 corresponds to "0"

area

WEH : WE which A0 corresponds to "1"

RAS1

Area 5 RAS

CS0L

Area 4 CASL

Area 4 CAS

CS0H

Area 4 CASH

Area 4 WEL

Area 4 CAS

CS1L

Area 5 CASL

Area 5 CAS

CS1H

Area 5 CASH

Area 5 WEL

Area 5 CAS

DW0

Area 4 WE

Area 4 WEL

Area 4 WE

DW1

Area 5 WE

Area 5 WEL

Area 5 WE

MB91107/108

HANDLING DEVICES

Preventing Latchup

In CMOS ICs, applying voltage higher than V

or lower than V

to input/output pin or applying voltage over

rating across V

and V

may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.

Treatment of Pins

Treatment of unused pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

Handling the output pins

Connecting an output pin to the power supply, to another output pin, or to a large-capacitance load may cause
a large current to flow. Since letting it flow for an extended period of time degrades the device, be careful in
using the device not to exceed the maximum rating.

Power supply pins

When there are several V

and V

pins, each of them is equipotentially connected to its counterpart inside of

the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to
prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to
observe the total output current standard, connect all V

and V

pins to the power supply or GND.

It is preferred to connect V

and V

of MB91107 to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1

F between V

and

at a position as close as possible to MB91107.

Mode setting

ins (MD0 to MD2)

Connect mode setting pins (MD0 to MD2) directly to V

or V

Arrange each mode setting pin and V

or V

patterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

Crystal oscillator circuit

Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0, X1
and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.
It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.

Notes on Use

External reset input

The RST pin requires "L" level input for at least five machine cycles before the the internal circuitry can be
completely reset.

External clock

To use an external clock, in principle, supply the X0 and X1 pins with a clock signal opposite in phase to the X0.
To use the STOP mode (oscillation stop mode) along with the external clock, in which the X1 pin stops with "H"
output, you should insert an external resistor of about 1 kilohm to prevent a collision between outputs.
Given the next page is an example of using an external clock.

MB91107/108

Notes on Internal DC-DC Regulator

· Since this product contains a regulator, be sure to supply current at 3.3 V to the VCC pin and insert a bypass

capacitor of about 0.1

F to the C pin for the regulator.

· The A/D converter requires a 3.3-V power supply separately.

·Notes on using the STOP mode

The regulator built in this product stops in the STOP mode. If the regulator stops due to a malfunction caused
by noise or a fault in the power supply during normal operation, the internal 2.5-V power supply may go below
the lower limit of the guaranteed operating voltage range. When using the STOP mode with the internal regulator,
therefore, be sure to supply an auxiliary external power to prevent the 3.3-V power supply from coming down.
Even in that case, the internal regulator can be restarted by input of a reset signal (To restart the regulator, keep
the reset pin at the L level for at least the oscillation settling time).

·Using an external clock (for normal use)

Note: To use the STOP mode (oscillation stop mode), insert a resistor to the X1 pin.

MB91108
MB91107

3.3 V

GND

AVRH

·Connecting to power supply

MB91107/108

Turning on the Power Supply

RST pin

When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power
supply voltage goes to V

level, at least after ensuring the time for 5 machine cycles, then set to "H" level.

Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 MHz.
Take care that the pin condition may be output condition at initial unstable condition.
(With the MB91107, however, initalization can be achieved in less than about 42 ms after turning on the internal
power supply by maintaining the RST pin at "L" level.)

Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.

Hardware Stand-by at Turning on the Power Supply

When turning on the power supply with the HST pin being set to "L" level, the hardware doesn't stand by. However
the HST pin becomes available after the reset cancellation, the HST pin must once be back to "H" level.

Power on Reset

Make sure to make power on reset at turning on the power supply or returning on the power supply when the
power supply voltage is below the warranty range for normal operation.

·Using STOP mode with 3.3 V power supply

3.3 V

2.4 k

7.6 k

0.1

MB91107/108

BLOCK DIAGRAM

FR CPU

I-bus

(16 bit)

D-bus (32 bit)

Instruction Cache

1 KB

Harvard

Princeton

Bus Converter

Bit Search Module

DMAC (8 ch)

DREQ0
DACK0
EOP0

DREQ1
DACK1
EOP1

DREQ2
DACK2
EOP2

32 bit 16 bit

Bus Converter

X0 X1

RST
HST

Clock Control Unit

(Watch Dog Timer)

INT0

INT7

NMI

Interrupt Control Unit

AN0

AN3

AVRH

AVRL

ATG

10 bit A/D

Converter (4 ch)

Reload Timer (3 ch)

Port

R-bus (16 bit)

UART (3 ch)

with

Baud Rate Timer

PWM Timer (4 ch)

SI0 SI1 SI2
SO0 SO1 SO2
SC0 SC1 SC2

OCPA0

OCPA3

TRG0

TRG3

(32 bit)

C-bus

Port 0

Port B

DRAM Controller

RAM 128 KB (MB91107)
RAM 160 KB (MB91108)

Bus Controller

RAS0
CS0L
CS0H
DW0

RAS1
CS1L
CS1H
DW1

D31

D16

A24

A00

RD
WR0

WR1

RDY
CLK
CS0

CS7

BRQ BGRNT

Note: Pins are display for functions (Actually some pins are multiplexer).

When using REALOS, time control should be done by using external interrupt or inner timer.

MB91107/108

CPU CORE

Memory Space

The FR family has a logical address space of 4 Gbytes (2

bytes) and the CPU linearly accesses the memory

space.

0000 0000

0000 0400

0000 0800

0001 0000

000C 0000

000E 0000

0010 0000

FFFF FFFF

I/O

000E 8000

Access inhibited

External ROM/external

bus mode

Access inhibited

Direct addressing area*

See "

I/O MAP"

*1:

The following areas on the memory space are assigned to direct addressing area for
I/O. In these areas, an address can be specified in a direct operand of a code.
Direct areas consists of the following areas dependent on accessible data sizes.

*2: Access inhibited of MB91107

Note : Only the above mode exist in this product.

byte data access

0-0FF

half word data access

0-1FF

word data access

0-3FF

External area

Internal RAM

External area

Internal RAM

External area

Internal 32KB-RAM *

(MB91108 only)

Internal 128 KB-RAM

Internal ROM/external

bus mode

Access inhibited

MB91107/108

Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.

Dedicated registers

Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).

Program counter (PC)

: 32-bit length, indicates the location of the instruction to be executed.

Program status (PS)

: 32-bit length, register for storing register pointer or condition codes.

Table base register (TBR)

: Holds top address of vector table used in EIT (Exceptional/Interrupt/

Trap processing.

Return pointer (RP)

: Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP) : Indicates system stack space.

User's stack pointer (USP)

: Indicates user's stack space.

Multiplication/division result
register (MDH/MDL)

: 32-bit length, register for multiplication/division.

32 bit

Initial value

Program counter

XXXX XXXX Indeterminate

Program status

ILM

SCR CCR

Table base register

TBR

0F FC

Return pointer

XXXX XXXX Indeterminate

System stack pointer

SSP

0 0

User's stack pointer

USP

XXXX XXXX Indeterminate

Multiplication/division re-
sult register

MDH

XXXX XXXX Indeterminate

MDL

XXXX XXXX Indeterminate

ILM4 to ILM0

ILM

SCR

CCR

MB91107/108

Condition code register (CCR)

System condition code register (SCR)

Interrupt level mask register (ILM)

S-flag

: Specifies a stack pointer used as R15.

I-flag

: Controls user interrupt request enable/disable.

N-flag

: Indicates sign bit when division result is assumed to be in the 2's complement format.

Z-flag

: Indicates whether or not the result of division was "0".

V-flag

: Assumes the operand used in calculation in the 2's complement format and indicates whether or

not overflow has occurred.

C-flag

: Indicates if a carry or borrow from the MSB has occurred.

T-flag : Specifies whether or not to enable step trace trap.

ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

High

Low

MB91107/108

GENERAL-PURPOSE REGISTERS

R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer.

Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.

R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000

(SSP value).

32 bit

Initial value

XXXX XXXX

R12

R13

R14

XXXX XXXX

R15

0 0 0 0 0 0 0 0

MB91107/108

SETTING MODE

Pin

Mode setting pins and modes

Registers

Mode data

Bus mode setting bits and functions

Note : MB91107 places 128-KB internal RAM in the internal ROM area.

To use the 128-KB internal RAM, be sure to set '01'.

Mode setting pins

Mode name

Reset vector

access area

External data bus

width

Bus mode

MD2

MD1

MD0

External vector

mode 0

External

8 bits

External ROM/external
bus mode

External vector

mode 1

External

16 bits

Inhibited

Internal vector mode

Internal

(Mode register)

Inhibited

Functions

Note

Single-chip mode

Internal ROM/external bus mode

Inhibited

External ROM/external bus mode

Inhibited

MODR

Initial value

Access

Address : 0000 07FFH

XXXX XXXX

Bus mode setting bit

Always write "0" except for M1 and M0.

MB91107/108

I/O MAP

The remainder of this section contains a list of the registers for peripheral resources in memory space.

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

000001

PDR2

Port 2 data registe

R/W

Port Data Register

XXXXXXXX

000004

PDR7

Port 7 data registe

R/W

000005

PDR6

Port 6 data registe

R/W

XXXXXXXX

000008

PDRB

Port B data registe

R/W

XXXXXXXX

000009

PDRA

Port A data registe

R/W

XXXXXX

00000B

PDR8

Port 8 data registe

R/W

XXX

000012

PDRE

Port E data registe

R/W

XXXXXXXX

000013

PDRF

Port F data registe

R/W

XXXXXXXX

000014

PDRG

Port G data registe

R/W

XXXXXXXX

000015

PDRH

Port H data registe

R/W

XXXXXXX0

000016

PDRI

Port I data registe

R/W

00001C

SSR0

Serial status register 0

R/W

UART0

0 0 0 0 1

0 0

00001D

SIDR0/

SODR0

Serial input data register 0/
Serial output data register

R/W

XXXXXXXX

00001E

SCR0

Serial control register 0

R/W

0 0 0 0 0 1 0 0

00001F

SMR0

Serial mode register 0

R/W

0 0

000020

SSR1

Serial status register 1

R/W

UART1

0 0 0 0 1

0 0

000021

SIDR1/

SODR1

Serial input data register 1/
Serial output data register

R/W

XXXXXXXX

000022

SCR1

Serial control register 1

R/W

0 0 0 0 0 1 0 0

000023

SMR1

Serial mode register 1

R/W

0 0

000024

SSR2

Serial status register 2

R/W

UART2

0 0 0 0 1

0 0

000025

SIDR2/

SODR2

Serial input data register 2/
Serial output data register

R/W

XXXXXXXX

000026

SCR2

Serial control register 2

R/W

0 0 0 0 0 1 0 0

000027

SMR2

Serial mode register 2

R/W

0 0

000028

TMRLR0

16-bit reload register 0

Reload Timer 0

XXXXXXXX

000029

XXXXXXXX

00002A

TMR0

16-bit timer register 0

XXXXXXXX

00002B

XXXXXXXX

00002E

TMCSR0

16-bit reload timer
control status register 0

R/W

0 0 0 0

00002F

0 0 0 0 0 0 0 0

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

000030

TMRLR1

16-bit reload register 1

Reload Timer 1

XXXXXXXX

000031

XXXXXXXX

000032

TMR1

16-bit timer register 1

XXXXXXXX

000033

XXXXXXXX

000036

TMCSR1

16-bit reload timer
control status register 1

R/W

0 0 0 0

000037

0 0 0 0 0 0 0 0

000038

ADCR

A/D converter data register

A/D Converter

(Successive

approximation type)

000039

XXXXXXXX

00003A

ADCS

A/D converte control status register

R/W

0 0 0 0 0 0 0 0

00003B

0 0 0 0 0 0 0 0

00003C

TMRLR2

16-bit reload register 2

Reload Timer 2

XXXXXXXX

00003D

XXXXXXXX

00003E

TMR2

16-bit timer register 2

XXXXXXXX

00003F

XXXXXXXX

000042

TMCSR2

16-bit reload timer control status
register 2

R/W

0 0 0 0

000043

0 0 0 0 0 0 0 0

000050

ASR6

Area select register 6

External Bus Interface

1 1 1 1 1 1 1 1

000051

1 1 1 1 1 1 1 1

000052

AMR6

Area mask register 6

0 0 0 0 0 0 0 0

000053

0 0 0 0 0 0 0 0

000054

ASR7

Area select register 7

1 1 1 1 1 1 1 1

000055

1 1 1 1 1 1 1 1

000056

AMR7

Area mask register 7

0 0 0 0 0 0 0 0

000057

0 0 0 0 0 0 0 0

000059

CS67

Output enable

R/W

0 0 1 1

000078

UTIM0/

UTIMR0

U-TIMER register ch.0
U-TIMER reload register ch.0

R/W

U-TIMER 0

0 0 0 0 0 0 0 0

000079

0 0 0 0 0 0 0 0

00007B

UTIMC0

U-TIMER control register ch.0

R/W

0 0 0 0 1

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

00007C

UTIM1/

UTIMR1

U-TIMER register ch.1
U-TIMER reload register ch.1

R/W

U-TIMER 1

0 0 0 0 0 0 0 0

00007D

0 0 0 0 0 0 0 0

00007F

UTIMC1

U-TIMER control register ch.1

R/W

0 0 0 0 1

000080

UTIM2/

UTIMR2

U-TIMER register ch.2
U-TIMER reload register ch.2

R/W

U-TIMER 2

0 0 0 0 0 0 0 0

000081

0 0 0 0 0 0 0 0

000083

UTIMC2

U-TIMER control register ch.2

R/W

0 0 0 0 1

000094

EIRR

External interrup request register

R/W

External Interrupt/NMI

0 0 0 0 0 0 0 0

000095

ENIR

Interrupt enabble register

R/W

0 0 0 0 0 0 0 0

000098

ELVR

External interrup request level
setup register

R/W

0 0 0 0 0 0 0 0

000099

0 0 0 0 0 0 0 0

0000D2

DDRE

Port E data direction register

Port E-I Data Direction
Register

0 0 0 0 0 0 0 0

0000D3

DDRF

Port F data direction register

0 0 0 0 0 0 0 0

0000D4

DDRG

Port G data direction register

0 0 0 0 0 0 0 0

0000D5

DDRH

Port H data direction register

0 0 0 0 0 0 0 1

0000D6

DDRI

Port I data direction register

0 0

0000DC

GCN1

General control register 1

R/W

PWM

0 0 1 1 0 0 1 0

0000DD

0 0 0 1 0 0 0 0

0000DF

GCN2

General control register 2

R/W

0 0 0 0 0 0 0 0

0000E0

PTMR0

PWM timer register 0

1 1 1 1 1 1 1 1

0000E1

1 1 1 1 1 1 1 1

0000E2

PCSR0

PWM cycle setting register 0

XXXXXXXX

0000E3

XXXXXXXX

0000E4

PDUT0

PWM duty setting register 0

XXXXXXXX

0000E5

XXXXXXXX

0000E6

PCNH0

Control status register H 0

R/W

0 0 0 0 0 0 0

0000E7

PCNL0

Control status register L 0

R/W

0 0 0 0 0 0 0 0

0000E8

PTMR1

PWM timer register 1

1 1 1 1 1 1 1 1

0000E9

1 1 1 1 1 1 1 1

0000EA

PCSR

PWM cycle setting register 1

XXXXXXXX

0000EB

XXXXXXXX

0000EC

PDUT

PWM duty setting register 1

XXXXXXXX

0000ED

XXXXXXXX

0000EE

PCNH

Control status register H 1

R/W

0 0 0 0 0 0 0

0000EF

PCNL

Control status register L 1

R/W

0 0 0 0 0 0 0 0

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

0000F0

PTMR2

PWM timer register 2

PWM

1 1 1 1 1 1 1 1

0000F1

1 1 1 1 1 1 1 1

0000F2

PCSR2

PWM cycle setting register 2

XXXXXXXX

0000F3

XXXXXXXX

0000F4

PDUT2

PWM duty setting register 2

XXXXXXXX

0000F5

XXXXXXXX

0000F6

PCNH2

Control status register H 2

R/W

0 0 0 0 0 0 0

0000F7

PCNL2

Control status register L 2

R/W

0 0 0 0 0 0 0 0

0000F8

PTMR3

PWM timer register 3

1 1 1 1 1 1 1 1

0000F9

1 1 1 1 1 1 1 1

0000FA

PCSR3

PWM cycle setting register 3

XXXXXXXX

0000FB

XXXXXXXX

0000FC

PDUT3

PWM duty setting register 3

XXXXXXXX

0000FD

XXXXXXXX

0000FE

PCNH3

Control status register H 3

R/W

0 0 0 0 0 0 0

0000FF

PCNL3

Control status register L 3

R/W

0 0 0 0 0 0 0 0

000200

DPDP

DMAC parameter descriptor point

R/W

DMAC

XXXXXXXX

000201

XXXXXXXX

000202

XXXXXXXX

000203

X 0 0 0 0 0 0 0

000204

DACSR

DMAC control status register

R/W

0 0 0 0 0 0 0 0

000205

0 0 0 0 0 0 0 0

000206

0 0 0 0 0 0 0 0

000207

0 0 0 0 0 0 0 0

000208

DATCR

DMAC pin control register

R/W

XXXXXXXX

000209

XX 0 0 0 0 0 0

00020A

XX 0 0 0 0 0 0

00020B

XX 0 0 0 0 0 0

0003E4

ICHCR

Instruction cache

R/W

Instruction Cache

0003E5

0003E6

0003E7

0 0 0 0 0 0

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

0003F0

BSD0

Bit search module
zero-detection data register

Bit Search Module

XXXXXXXX

0003F1

XXXXXXXX

0003F2

XXXXXXXX

0003F3

XXXXXXXX

0003F4

BSD1

Bit search module
single-detection data register

R/W

XXXXXXXX

0003F5

XXXXXXXX

0003F6

XXXXXXXX

0003F7

XXXXXXXX

0003F8

BSDC

Bit search module
transition-detection data register

XXXXXXXX

0003F9

XXXXXXXX

0003FA

XXXXXXXX

0003FB

XXXXXXXX

0003FC

BSRR

Bit search module result register

XXXXXXXX

0003FD

XXXXXXXX

0003FE

XXXXXXXX

0003FF

XXXXXXXX

000400

ICR00

Interrupt control register 0

R/W

Interrupt Controller

1 1 1 1 1

000401

ICR01

Interrupt control register 1

1 1 1 1 1

000402

ICR02

Interrupt control register 2

1 1 1 1 1

000403

ICR03

Interrupt control register 3

1 1 1 1 1

000404

ICR04

Interrupt control register 4

1 1 1 1 1

000405

ICR05

Interrupt control register 5

1 1 1 1 1

000406

ICR06

Interrupt control register 6

1 1 1 1 1

000407

ICR07

Interrupt control register 7

1 1 1 1 1

000408

ICR08

Interrupt control register 8

1 1 1 1 1

000409

ICR09

Interrupt control register 9

1 1 1 1 1

00040A

ICR10

Interrupt control register 10

1 1 1 1 1

00040B

ICR11

Interrupt control register 11

1 1 1 1 1

00040C

ICR12

Interrupt control register 12

1 1 1 1 1

00040D

ICR13

Interrupt control register 13

1 1 1 1 1

00040E

ICR14

Interrupt control register 14

1 1 1 1 1

00040F

ICR15

Interrupt control register 15

1 1 1 1 1

000410

ICR16

Interrupt control register 16

1 1 1 1 1

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

000411

ICR17

Interrupt control register17

R/W

Interrupt Controller

1 1 1 1 1

000412

ICR18

Interrupt control register 18

1 1 1 1 1

000413

ICR19

Interrupt control register 19

1 1 1 1 1

000414

ICR20

Interrupt control register 20

1 1 1 1 1

000415

ICR21

Interrupt control register 21

1 1 1 1 1

000416

ICR22

Interrupt control register 22

1 1 1 1 1

000417

ICR23

Interrupt control register 23

1 1 1 1 1

000418

ICR24

Interrupt control register 24

1 1 1 1 1

000419

ICR25

Interrupt control register 25

1 1 1 1 1

00041A

ICR26

Interrupt control register 26

1 1 1 1 1

00041B

ICR27

Interrupt control register 27

1 1 1 1 1

00041C

ICR28

Interrupt control register 28

1 1 1 1 1

00041D

ICR29

Interrupt control register 29

1 1 1 1 1

00041E

ICR30

Interrupt control register 30

1 1 1 1 1

00041F

ICR31

Interrupt control register 31

1 1 1 1 1

000420

ICR32

Interrupt control register 32

1 1 1 1 1

000421

ICR33

Interrupt control register 33

1 1 1 1 1

000422

ICR34

Interrupt control register 34

1 1 1 1 1

000423

ICR35

Interrupt control register 35

1 1 1 1 1

000424

ICR36

Interrupt control register 36

1 1 1 1 1

000425

ICR37

Interrupt control register 37

1 1 1 1 1

000426

ICR38

Interrupt control register 38

1 1 1 1 1

000427

ICR39

Interrupt control register 39

1 1 1 1 1

000428

ICR40

Interrupt control register 40

1 1 1 1 1

000429

ICR41

Interrupt control register 41

1 1 1 1 1

00042A

ICR42

Interrupt control register 42

1 1 1 1 1

00042B

ICR43

Interrupt control register 43

1 1 1 1 1

00042C

ICR44

Interrupt control register 44

1 1 1 1 1

00042D

ICR45

Interrupt control register 45

1 1 1 1 1

00042E

ICR46

Interrupt control register 46

1 1 1 1 1

00042F

ICR47

Interrupt control register 47

1 1 1 1 1

000430

DICR

Delayed interrupt

R/W

Delayed Interrupt Controller
Register

000431

HRCL

Holding request withdrawal
request level set register

R/W

1 1 1 1 1

MB91107/108

Note : Do not execute an RMW-type instruction for any register containing a write-only bit.

(Continued)

Address

Register

name

Register name

Access

Resource name

Initial value

000480

RSRR/

WTCR

Reset cause register/watchdog
cycle control register

R/W

Clock Controller

1 XXXX

0 0

000481

STCR

Stand-by controller register

R/W

0 0 0 1 1 1

000482

PDRR

DMA controller request prohibit
resister

R/W

0 0 0 0

000483

CTBR

Timebase timer clear register

XXXXXXXX

000484

GCR

Gear controller register

R/W

1 1 0 0 1 1

000485

WPR

Watchdog reset generation
postpone register

XXXXXXXX

000488

PCTR

PLL controller register

PLL Controller

0 0

000601

DDR2

Port 2 data direction register

Port Direction Register

0 0 0 0 0 0 0 0

000604

DDR7

Port 7 data direction register

000605

DDR6

Port 6 data direction register

0 0 0 0 0 0 0 0

000608

DDRB

Port B data direction register

0 0 0 0 0 0 0 0

000609

DDRA

Port A data direction register

0 0 0 0 0 0

00060B

DDR8

Port 8 data direction register

0 0 0 0 0 0

00060C

ASR1

Area selection register 1

External Bus Interface

0 0 0 0 0 0 0 0

00060D

0 0 0 0 0 0 0 1

00060E

AMR1

Area mask register 1

0 0 0 0 0 0 0 0

00060F

0 0 0 0 0 0 0 0

000610

ASR2

Area selection register 2

0 0 0 0 0 0 0 0

000611

0 0 0 0 0 0 1 0

000612

AMR2

Area mask register 2

0 0 0 0 0 0 0 0

000613

0 0 0 0 0 0 0 0

000614

ASR3

Area selection register 3

0 0 0 0 0 0 0 0

000615

0 0 0 0 0 0 11

000616

AMR3

Area mask register 3

0 0 0 0 0 0 0 0

000617

0 0 0 0 0 0 0 0

000618

ASR4

Area selection register 4

0 0 0 0 0 0 0 0

000619

0 0 0 0 0 1 0 0

00061A

AMR4

Area mask register 4

0 0 0 0 0 0 0 0

00061B

0 0 0 0 0 0 0 0

00061C

ASR5

Area selection register 5

0 0 0 0 0 0 0 0

00061D

0 0 0 0 0 1 0 1

MB91107/108

(Continued)

Note: Do not execute an RMW-type instruction for any register containing a write-only bit.

Note : RMW-type instructions (RMW: Read modify write)

Address

Register

name

Register name

Access

Resource name

Initial value

00061E

AMR5

Area mask register 5

External Bus Interface

0 0 0 0 0 0 0 0

00061F

0 0 0 0 0 0 0 0

000620

AMD0

Area mode register 0

R/W

0 0 1 1 1

000621

AMD1

Area mode register 1

R/W

0 0 0 0 0

000622

AMD32

Area mode register 32

R/W

0 0 0 0 0 0 0 0

000623

AMD4

Area mode register 4

R/W

0 0 0 0 0

000624

AMD5

Area mode register 5

R/W

0 0 0 0 0

000625

DSCR

DRAM signal control register

0 0 0 0 0 0 0 0

000626

RFCR

Refresh control register

R/W

XXXXXX

000627

0 0

0 0 0

000628

EPCR0

External pin control register 0

1 1 0 0

000629

1 1 1 1 1 1 1

00062A

EPCR1

External pin control register 1

00062B

1 1 1 1 1 1 1 1

00062C

DMCR4

DRAM control register 4

R/W

0 0 0 0 0 0 0 0

00062D

0 0 0 0 0 0 0

00062E

DMCR5

DRAM control register 5

R/W

0 0 0 0 0 0 0 0

00062F

0 0 0 0 0 0 0

0007FE

LER

Little endian register

Little Endian Registor
Mode Register

0 0 0

0007FF

MODR

Mode register

XXXXXXXX

AND

Rj, @Ri

EOR

Rj, @Ri

ANDH

Rj, @Ri

ORH

Rj, @Ri

EORH

Rj, @Ri

ANDB

Rj, @Ri

ORB

Rj, @Ri

EORB

Rj, @Ri

BANDL

#u4, @Ri

BORL #u4, @Ri

BEORL

#u4, @Ri

BANDH

#u4, @Ri

BORH #u4, @Ri

BEORH

#u4, @Ri

MB91107/108

INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal Hexadecimal

Register

Offset

Reset

3FC

0FFFFC

Reserved for system

3F8

0FFFF8

Reserved for system

3F4

0FFFF4

Reserved for system

3F0

0FFFF0

Reserved for system

3EC

0FFFEC

Reserved for system

3E8

0FFFE8

Reserved for system

3E4

0FFFE4

Reserved for system

3E0

0FFFE0

Reserved for system

3DC

0FFFDC

Reserved for system

3D8

0FFFD8

Reserved for system

3D4

0FFFD4

Reserved for system

3D0

0FFFD0

Reserved for system

3CC

0FFFCC

Reserved for system

3C8

0FFFC8

Exception for undefined instruction

3C4

0FFFC4

NMI request

fixed

3C0

0FFFC0

External interrupt 0

ICR00

3BC

0FFFBC

External interrupt 1

ICR01

3B8

0FFFB8

External interrupt 2

ICR02

3B4

0FFFB4

External interrupt 3

ICR03

3B0

0FFFB0

UART0 receive complete

ICR04

3AC

0FFFAC

UART1 receive complete

ICR05

3A8

0FFFA8

UART2 receive complete

ICR06

3A4

0FFFA4

UART0 transmit complete

ICR07

3A0

0FFFA0

UART1 transmit complete

ICR08

39C

0FFF9C

UART2 transmit complete

ICR09

398

0FFF98

DMAC0 (complete, error)

ICR10

394

0FFF94

DMAC1 (complete, error)

ICR11

390

0FFF90

DMAC2 (complete, error)

ICR12

38C

0FFF8C

DMAC3 (complete, error)

ICR13

388

0FFF88

DMAC4 (complete, error)

ICR14

384

0FFF84

DMAC5 (complete, error)

ICR15

380

0FFF80

DMAC6 (complete, error)

ICR16

37C

0FFF7C

DMAC7 (complete, error)

ICR17

378

0FFF78

MB91107/108

(Continued)

*: When using in REALOS/FR, interrupt 0x40, 0x41 for system code.

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal Hexadecimal

Register

Offset

A/D converter (successive
approximation conversion type)

ICR18

374

0FFF74

Reload timer 0

ICR19

370

0FFF70

Reload timer 1

ICR20

36C

0FFF6C

Reload timer 2

ICR21

368

0FFF68

PWM0

ICR22

364

0FFF64

PWM1

ICR23

360

0FFF60

PWM2

ICR24

35C

0FFF5C

PWM3

ICR25

358

0FFF58

U-TIMER0

ICR26

354

0FFF54

U-TIMER1

ICR27

350

0FFF50

U-TIMER2

ICR28

34C

0FFF4C

Reserved for system

ICR29

348

0FFF48

Reserved for system

ICR30

344

0FFF44

Reserved for system

ICR31

340

0FFF40

Reserved for system

ICR32

33C

0FFF3C

Reserved for system

ICR33

338

0FFF38

Reserved for system

ICR34

334

0FFF34

Reserved for system

ICR35

330

0FFF30

Reserved for system

ICR36

32C

0FFF2C

Reserved for system

ICR37

328

0FFF28

Reserved for system

ICR38

324

0FFF24

Reserved for system

ICR39

320

0FFF20

Reserved for system

ICR40

31C

0FFF1C

Reserved for system

ICR41

318

0FFF18

Reserved for system

ICR42

314

0FFF14

Reserved for system

ICR43

310

0FFF10

Reserved for system

ICR44

30C

0FFF0C

Reserved for system

ICR45

308

0FFF08

Reserved for system

ICR46

304

0FFF04

Delayed interrupt cause bit

ICR47

300

0FFF00

Reserved for system (used in REALOS*)

2FC

0FFEFC

Reserved for system (used in REALOS*)

2F8

0FFEF8

Used in INT instructions

66 to 255

42 to FF

2F4

000

0FFEF4

0FFC00

MB91107/108

PERIPHERAL RESOURCES

I/O Ports

There are 2 types of I/O port register structure; PDR (port data register) and DDR (data direction register) .
· For input (DDR = "0") setting;

PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.

· For output (DDR = "1") setting;

PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.

(1) Register configuration

·Port Data Register (PDR)

Address

bit 7

bit 0

Initial value

Access

000001

PDR2

XXXXXXXX

R/W

000005

PDR6

XXXXXXXX

R/W

000004

PDR7

- - - - - - - X

R/W

00000B

PDR8

- - X - - XXX

R/W

000009

PDRA

- XXXXXX -

R/W

000008

PDRB

XXXXXXXX

R/W

000012

PDRE

XXXXXXXX

R/W

000013

PDRF

XXXXXXXX

R/W

000014

PDRG

XXXXXXXX

R/W

000015

PDRH

XXXXXXX0

R/W

000016

PDRI

- - - - - - XX

R/W

R/W : Readable and writable

: Unused

: Indeterminate

MB91107/108

DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to en-
hanced performance of the system.
· 8 channels
· Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
· Transfer all through the area
· Max. 65536 of transfer cycles
· Interrupt function right after the transfer
· Selectable for address transfer increase/decrease by the software
· External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

(1) Register configuration

DMAC (DMAC internal registers)

RAM (DMA descriptor)

Address

bit 31

bit 0

DMAC parameter descriptor point

000200

DPDP

DMAC control status register

000204

DACSR

DMAC pin control register

000208

DATCR

bit 31

bit 0

DPDP

DMA

ch-0

descriptor

DPDP

DMA

ch-1

descriptor

DPDP

DMA

ch-7

descriptor

MB91107/108

UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchro-
nous communication, and it has the following features.

The MB91107 consists of 3 channels of UART.
· Full double double buffer
· Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
· Supporting multi-processor mode
· Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section "4. U-TIMER").

· Any baud rate can be set by external clock.
· Error checking function (parity, framing and overrun)
· Transfer signal: NRZ code
· Enable DMA transfer/start by interrupt.

(1) Register configuration

·Serial control register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

SCR0 :
SCR1 :
SCR2 :

00001E

000022

000026

SCR0 to SCR2

(SMR)

010

R/W

·Serial mode register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

SMR0 :
SMR1 :
SMR2 :

00001F

000023

000027

(SCR)

SMR0 to SMR2

0 - - 0 - 0

R/W

·Serial status register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

SSR0 :
SSR1 :
SSR2 :

00001C

000020

000024

SSR0 to SSR2

(SIDR/SODR)

01 - 0

R/W

·Serial input data register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

SIDR0 :
SIDR1 :
SIDR2 :

00001D

000021

000025

(SSR)

(SIDR/SODR)

XXXXXXXX

·Serial output data register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

SIDR0 :
SIDR1 :
SIDR2 :

00001D

000021

000025

(SSR)

(SIDR/SODR)

XXXXXXXX

R/W : Readable and writable

: Unused

: Read only

: Indeterminate

: Write only

MB91107/108

(2) Block diagram

MD1
MD0

CS0

SCKE
SOE

PEN
P
SBL
CL
A/D
REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

R - BUS

SIDR

SODR

Control signal

From U-TIMER

From external clock

(Receive data)

Clock

select
circuit

Receive status

judge circuit

Receive error
generate sig-
nal for DMA
( to DMAC)

Receive control

circuit

Start bit detect

circuit

Receive bit

counter

Receive parity

counter

Receive shifter

Receive

complete

Receive interrupt

( to CPU)

SC (clock)

Transmit interrupt

( to CPU)

Transmit start

circuit

Transmit bit

counter

Transmit parity

counter

Transmit shifter

Transmit

start

(Transmit data)

SMR

Control signals

SCR

Regis

SSR

Receive clock

Transmit control

circuit

Transmit clock

MB91107/108

U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91107 has 3 channel U-TIMER embedded on the chip. An interval of up to 2

can be counted.

(1) Register configuration

· U-TIMER register ch 0 to ch 2

Address

bit 15

bit 0

Initial value

Access

UTIM0 :
UTIM1 :
UTIM2 :

000078

00007C

000080

UTIM0 to UTIM2

· U-TIMER reload register ch 0 to ch 2

Address

bit 15

bit 0

Initial value

Access

UTIM0 :
UTIM1 :
UTIM2 :

000078

00007C

000080

UTIM0 to UTIM2

· U-TIMER control register ch 0 to ch 2

Address

bit 15

bit 0

Initial value

Access

UTIM0 :
UTIM1 :
UTIM2 :

00007B

00007F

000083

(Vacancy)

UTIMC0 to UTIMC2

0 - - 0

R/W

R/W : Readable and writable

: Read only

: Write only

: Unused

MB91107/108

PWM Timer

The PWM timer can output high accurate PWM waves efficiently.

MB91101 has inner 4-channel PWM timers, and has the following features.
· Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit

compare resister with a buffer for duty setting, and a pin controller.

· The count clock of a 16-bit down counter can be selected from the following four inner clocks.
· Inner clock

/4,

/16,

/64

· The counter value can be initialized "FFFF

" by the resetting or the counter borrow.

· PWM output (each channel)
· Resister description

Cycle setting register: Reload data register with a buffer
Duty factor setting register: Compare register with a buffer
Transfer from the buffers uses the counter borrow method.

· Pin control outline

Set to '1' at a duty factor match. (Preferential)
Set to '0' at a counter borrow.
The output value fixed mode is available, which makes all 'L' (or 'H') output easy.
The polarity can also be specified.

· Interrupt requests can be generated by selected a combination of events:

This timer is activated.
A counter borrow is generated (cycle match).
A duty factor match is generated.
A counter borrow is generated (cycle match) or a duty factor match is generated.

DMA transfer can be invoked by the above interrupt request.

· Simultaneous activation of multiple channels of the PWM timer can be set by software or by using another

interval timer. Restarting the PWM timer during operation can also be set.

MB91107/108

(1) Register configuration

Address

bit 15

bit 0

Initial value

Access

0000DC

GCN1

R/W

General control register 1

0000DF

GCN2

R/W

General control register 2

0000E0

PTMR

ch0 timer register

0000E2

PCSR

XXXXXXXX

ch0 cycle setting register

0000E4

PDUT

XXXXXXXX

ch0 duty setting register

0000E6

PCNH

PCNL

R/W

ch0 control status register

0000E8

PTMR

ch1 timer register

0000EA

PCSR

XXXXXXXX

ch1 cycle setting register

0000EC

PDUT

XXXXXXXX

ch1 duty setting register

0000EE

PCNH

PCNL

R/W

ch1 control status register

0000F0

PTMR

ch2 timer register

0000F2

PCSR

XXXXXXXX

ch2 cycle setting register

0000F4

PDUT

XXXXXXXX

ch2 duty setting register

0000F6

PCNH

PCNL

R/W

ch2 control status register

0000F8

PTMR

ch3 timer register

0000FA

PCSR

XXXXXXXX

(W) ch3 cycle setting register

0000FC

PDUT

XXXXXXXX

ch3 duty setting register

0000FE

PCNH

PCNL

R/W

ch3 control status register

R/W : Readable and writable

: Unused

: Read only

: Indeterminate

: Write only

MB91107/108

16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal
count clock and control registers.
Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).
The DMA transfer can be started by the interruption.
The MB91107 consists of 3 channels of the 16-bit reload timer.

(1) Register configuration

·Control status register

Address

bit 15

bit 0

Initial value

Access

TMCSR0 :
TMCSR1 :
TMCSR2 :

00002E

000036

000042

TMCSR0 to TMCSR2

- - - - 0

R/W

·16-bit timer register

Address

bit 15

bit 0

Initial value

Access

TMR0 :
TMR1 :
TMR2 :

00002A

000032

00003E

TMR0 to TMR2

XXXXXXXX

·16-bit reload register

Address

bit 15

bit 0

Initial value

Access

TMRLR0 :
TMRLR1 :
TMRLR2 :

000028

000030

00003C

TMRLR0 to TMRLR2

XXXXXXXX

R/W : Readable and writable

: Unused

: Read only

: Indeterminate

: Write only

MB91107/108

Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.

(1) Register configuration

(2) Block diagram

Address

bit 31

bit 0

Initial value

Access

0003F0

BSD0

XXXXXXXXXXXXXXXX

Zero-detection data register

0003F4

BSD1

XXXXXXXXXXXXXXXX

R/W

Single-detection data register

0003F8

BSDC

XXXXXXXXXXXXXXXX

Detection data register

0003FC

BSRR

XXXXXXXXXXXXXXXX

Search result register

R/W : Readable and writable

: Read only

: Write only

: Indeterminate

D-BUS

Address

decoder

Input latch

Detection

mode

Single-detection data register

Bit search circuit

Search result

MB91107/108

A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.
· Minimum converting time: 5.6

s/ch. (system clock: 25 MHz)

· Inner sample and hold circuit
· Resolution: 10 bits
· Analog input can be selected from 4 channels by program.

Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronising at

the beginning of conversion can be peformed.

· DMA transfer operation is available by interruption.
· Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer

(rising edge).

(1) Register configuration

·A/D converter control register

Address

bit 15

bit 0

Initial value

Access

00003A

ADCS

R/W

·A/D converter data register

Address

bit 15

bit 0

Initial value

Access

000038

ADCR

- -

- - -XX

XXXXXXXX

R/W : Readable and writable

: Read only

: Indeterminate

MB91107/108

Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

·Hardware configuration

This module consists of the following components:
· ICR register
· Interrupt priority evaluation circuit
· Interrupt level/interrupt number (vector) generator
· HOLD request cancel request generator

·Main Features

The major functions of this module are listed below:
· NMI request/interrupt request detection
· Priority evaluation (interrupt level and number)
· Transfer of interrupt level as evaluation factor (to the CPU)
· Transfer of interrupt number as evaluation factor (to the CPU)
· Instruction of returning from the stop mode by NMI/interrupt generation
· Generating a request to cancel the HOLD request to the bus master

MB91107/108

(1) Register configuration

Interrupt control

Address

bit 7

bit 0

Initial value Access

Address

bit 7

bit 0

Initial value Access

000400

ICR00

- - - 11111

R/W

000419

ICR25

- - - 11111

R/W

000401

ICR01

- - - 11111

R/W

00041A

ICR26

- - - 11111

R/W

000402

ICR02

- - - 11111

R/W

00041B

ICR27

- - - 11111

R/W

000403

ICR03

- - - 11111

R/W

00041C

ICR28

- - - 11111

R/W

000404

ICR04

- - - 11111

R/W

00041D

ICR29

- - - 11111

R/W

000405

ICR05

- - - 11111

R/W

00041E

ICR30

- - - 11111

R/W

000406

ICR06

- - - 11111

R/W

00041F

ICR31

- - - 11111

R/W

000407

ICR07

- - - 11111

R/W

000420

ICR32

- - - 11111

R/W

000408

ICR08

- - - 11111

R/W

000421

ICR33

- - - 11111

R/W

000409

ICR09

- - - 11111

R/W

000422

ICR34

- - - 11111

R/W

00040A

ICR10

- - - 11111

R/W

000423

ICR35

- - - 11111

R/W

00040B

ICR11

- - - 11111

R/W

000424

ICR36

- - - 11111

R/W

00040C

ICR12

- - - 11111

R/W

000425

ICR37

- - - 11111

R/W

00040D

ICR13

- - - 11111

R/W

000426

ICR38

- - - 11111

R/W

00040E

ICR14

- - - 11111

R/W

000427

ICR39

- - - 11111

R/W

00040F

ICR15

- - - 11111

R/W

000428

ICR40

- - - 11111

R/W

000410

ICR16

- - - 11111

R/W

000429

ICR41

- - - 11111

R/W

000411

ICR17

- - - 11111

R/W

00042A

ICR42

- - - 11111

R/W

000412

ICR18

- - - 11111

R/W

00042B

ICR43

- - - 11111

R/W

000413

ICR19

- - - 11111

R/W

00042C

ICR44

- - - 11111

R/W

000414

ICR20

- - - 11111

R/W

00042D

ICR45

- - - 11111

R/W

000415

ICR21

- - - 11111

R/W

00042E

ICR46

- - - 11111

R/W

000416

ICR22

- - - 11111

R/W

00042F

ICR47

- - - 11111

R/W

000417

ICR23

- - - 11111

R/W

000418

ICR24

- - - 11111

R/W

·Request level register for canceling hold request

Address

bit 7

bit 0

Initial value Access

00000431

HRCL

- - - 11111

R/W

R/W : Readable and writable

: Unused

MB91107/108

(2) Block diagram

*1 : DLY I stands for delayed interrupt module (delayed interrupt generation block) (refer to the section "11. Delayed

Interrupt Module" for detail).

*2 : INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3 : HLDCAN is a bus release request signal for bus masters other than CPU.

*4 : LEVEL 4 to LEVEL 0 are interrupt level outputs.

*5 : VCT5 to VCT0 are interrupt vector outputs.

INT0

NMI

RI00

RI47

(DLYIRQ)

DLYI

LEVEL
4

HLDCAN

VCT5

R-BUS

ICR00

ICR47

Priority judgment

NMI

processing

LEVEL judgment

VECTOR

judgment

LEVEL,

VECTOR

generation

HLDREQ

cancel

request

MB91107/108

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to
INT7 pins.
Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin).

(1) Register configuration

(2) Block diagram

·Interrupt enable register

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

000095

EIRR

ENIR

00000000

R/W

·External interrupt cause register

bit 15

bit 8 bit 7

bit 0

000094

EIRR

ENIR

00000000

R/W

·Request level setting register

bit 15

bit 8 bit 7

bit 0

000099

EIRR

ENIR

00000000

R/W

INT0 ~ INT7
NMI

R BUS

Interrupt

request

Interrupt enable register

Gate

Cause F/

Request level setting register

Interrupt cause register

Edge detection

circuit

MB91107/108

12. Clock Generation (Low-power consumption mechanism)

The clock control block is a module which undertakes the following functions.
· CPU clock generation (including gear function)
· Peripheral clock generation (including gear function)
· Reset generation and cause hold
· Standby function (including hardware standby)
· DMA request prohibit
· PLL (multiplier circuit) embedded

(1) Register configuration

·Reset cause register/watchdog cycle control register

Address

bit 15

bit 10

bit 8

bit 0

Initial value

Access

000480

RSRR

WTCR

(STCR)

1XXXX - 0

R/W

·Stand-by controled register

Address

bit 15

bit 10

bit 8

bit 0

Initial value

000481

(RSRR/WTCR)

STCR

111 - -

R/W

·DMA controlerrequest prohibit resister

Address

bit 15

bit 8

bit 0

Initial value

000482

PDRR

(CTBR)

- - - - 0

R/W

·Timebase timer clear resister

Address

bit 15

bit 8

bit 0

Initial value

000483

PDRR

(CTBR)

XXXXXXXX

·Gear control resister

Address

bit 15

bit 8

bit 0

Initial value

000484

GCR

(WPR)

- - - - 0

R/W

·Watchdog reset generation postpone resister

Address

bit 15

bit 8

bit 0

Initial value

000485

(GCR)

WPR

XXXXXXXX

·PLL control resister

Address

bit 15

bit 8

bit 0

Initial value

000488

PCTR

Vacancy

0 - - 0 - - -

R/W : Readable and writable

: Write only

: Unused

: Indeterminate

MB91107/108

(2) Block diagram

X0
X1

PLL

1/2

B
U
S

Internal reset

CPU hold enable

DMA request

Power on cell

RST pin

GCR register

CPU gear

Status

transition

control

circuit

PDRR register

(Watchdog control section)

Timebase timer

CPU clock

Internal bus clock

External bus clock

Internal bus
peripheral clock

STOP state

SLEEP state

CPU hold request

HST pin

Gear control

block

Peripheral

gear

Peripheral DMA clock

PCTR register

STCR register

Count clock

Watchdog F/F

(Reset cause circuit)

(DNA prohibit

circuit)

RSRR register

WPR register

CTBR register

Internal interrupt

Oscil-

lator

Selection

circuit

(Stop/sleep control section)

Reset

generation

F/F

Internal

clock

generator

circuit

Internal reset

MB91107/108

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.
· 25-bit (32 Mbytes) address output
· 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes

6 area setting is available by the address pin and the chip select pin.

· 8/16-bit bus width setting are available for every chip select area.

Areas 6 and 7 allow the inclusive areas to be set.

· Programmable automatic memory wait (max. for 7 cycles) can be inserted.
· DRAM interface support
· Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM

Hyper DRAM

· 2 banks independent control (RAS, CAS, etc. control signals)
· DRAM select is available from 2CAS/1WE and 1CAS/2WE.
· Hi-speed page mode supported
· CBR/self refresh supported
· Programmable wave form
· Unused address/data pin can be used for I/O port.
· Little endian mode supported
· Clock doubler: Internal bus 50 MHz, external bus 25 MHz

(1) Register configuration

(Continued)

·Area selection

resister

1 to 5

Address

bit 15

bit 0

Initial value

Access

00060C

ASR1

000610

ASR2

000614

ASR3

000618

ASR4

00061C

ASR5

·Area mask

resister

1 to 5

Address

bit 15

bit 0

Initial value

00060E

AMR1

000612

AMR2

000616

AMR3

00061A

AMR4

00061E

AMR5

MB91107/108

(Continued)

·Area mode

resister

0, 1, 32, 4, 5

Address

bit 15

bit 8 bit 7

bit 0

Initial value

Access

AMD0
AMD1

: 000620

: 000621

AMD0

AMD1

- - - 0

- -

R/W

AMD32
AMD4

: 000622

: 000023

AMD32

AMD4

0 - - 0

R/W

AMD5

: 000624

AMD5

(DSCR)

0 - - 0

R/W

·DRAM signal control

resister

Address

bit 15

bit 8 bit 7

bit 0

Initial value

000625

AMD5

DSCR

·Refresh control

resister

Address

bit 15

bit 0

Initial value

000626

RFCR

- - XXXXXX

R/W

- - - 0

·External pin control

resister

Address

bit 15

bit 0

Initial value

000628

EPCR0

- - - - 1

- 1

00062A

EPCR1

- - - - - - - 1

·DRAM control

resister

4, 5

Address

bit 15

bit 0

Initial value

00062C

DMCR4

R/W

00062E

DMCR5

R/W

·Little endian resister

Address

bit 15

bit 8 bit 7

bit 0

Initial value

0007FE

LER

(MODR)

- - - - - 0

·Mode

resister

Address

bit 15

bit 8 bit 7

bit 0

Initial value

0007FF

(MODR)

LER

XXXXXXXX

R/W : Readable and writable

: Write only

: Unused

: Indeterminate

MB91107/108

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(AV

0.0 V)

*1 : V

must not be less than V

0.3 V.

*2 : Make sure that the voltage does not exceed V

+ 0.3 V, such as when turning on the device.

*3 : Maximum output current is a peak current value measured at a corresponding pin.

*4 : Average output current is an average current for a 100 ms period at a corresponding pin.

*5 : Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

0.3

4.0

Analog supply voltage

0.3

4.0

Analog reference voltage

AVRH

0.3

4.0

Input voltage

0.3

Analog pin input voltage

0.3

Output voltage

0.3

"L" level maximum output current

"L" level average output current

OLAV

"L" level total maximum output current

100

"L" level total average output current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level total maximum output
current

"H" level total average output current

OHAV

Power consumption

500

Operating temperature

Storage temperature

Tstg

150

MB91107/108

Recommended Operating Conditions

(AV

0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

Parameter

Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

3.0

3.6

Normal operation

3.0

3.6

Retaining the RAM state in
stop mode

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

Operating temperature

MB91107/108

DC Characteristics

3.0 V to 3.6 V, AV

0.0 V, T

C to

: Hysteresis input pin : NMI, RST, P40

P47, P50

P57, P60

P67, P70, P81, P85, PA1

PA6, PB0

PB7,

PE0

PE7, PF0

PF7, PG0

PG7, PH0

PH7, PI0, PI1

*2 : The MB91V107 (development model) has larger supply current than the production models because it contains

an development tool interface circuit.

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level input
voltage

Input pin ex-
cept for hys-
teresis input

0.7

0.3

"L" level input
voltage

IHS

0.8

0.3

Hysteresis
input

Input pin ex-
cept for hys-
teresis input

0.3

0.25

ILS

0.3

0.2

Hysteresis
input

"H" level output
voltage

All output pins

3.0 V

4.0 mA

0.5

"L" level output
voltage

All output pins

3.0 V

8.0 mA

0.4

Input leak
current (Hi-Z Out-
put leak current)

All output pins

3.6 V

0.45 V<V

< V

Pull-up
resistance

PULL

RST

3.6 V

0.45 V

100

Pull-down
resistance

DOWN

BRQ

3.6 V

3.3 V

100

Power supply
current

12.5 MHz

3.3 V

150

(Four
multiplication
)

Operation
at 50 MHz

CCS

12.5 MHz

3.3 V

120

Sleep
mode

CCH

3.3 V

Stop mode

Input
capacitance

Except for V

, AV

MB91107/108

(1) Clock Timings

3.0 V to 3.6 V, AV

0.0 V, T

C to

*1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock

multiplication system.

*2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and

a 1/8 gear.

Parameter

Sym-

bol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Clock frequency (1)

X0
X1

12.5

MHz

Self-oscillation 12.5 MHz
Internal operation at 50 MHz
(Using PLL, 4 multiplication)

Clock cycle time

X0
X1

Frequency shift ratio

(when locked)

Clock frequency (2)

X0
X1

MHz

Self-oscillation
(divide-by-2 input)

Clock frequency (3)

X0
X1

MHz

External clock
(divide-by-2 input)

Clock cycle time

X0
X1

100

Input clock pulse width

X0
X1

12.5 to
25 MHz

Input to X0, X1

Less than
12.5 MH

Input to X0 only

Input clock rising/falling
time

X0
X1

)

Internal operating clock
frequency

0.625

MHz CPU system

CPP

0.625

MHz Peripheral system

Internal operating clock
cycle time

1600*

CPU system

CPP

1600*

Peripheral system

f =

100 (

)

Center frequency

MB91107/108

(MHz)

12.5

(MHz)

0.625

3.6

3.0

(V)

/ f

CPP

(MHz)

/ f

CPP

CPU

0.8 V

0.2 V

Clock timing rating measurement conditions

Operation warranty range

External / internal clock setting range

Power supply

Internal clock

Normal operation warranty range (T

= 0

C to +70

C).

Net masked area are f

CPP

Max. internal clock frequency setting

LL system
(12.5 MHz / 4 multiplication)

Peripheral

divide-by-2 system

External clock

Self-oscillation

Note:

When using PLL, the external clock must be used need 12.5 MHz.

PLL oscillation stabilizing period

100

The setting of internal clock must be within above ranges.

General oscillation input clock

MB91107/108

(2) Clock Output Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

*1 : t

CYC

is a frequency for 1 clock cycle including a gear cycle.

*2 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : (1 n/2)

CYC

Max. : (1 n/2)

CYC

+ 10

Select a gear cycle of

1 when using the doubler.

*3 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,

respectively.

Min.: n/2

CYC

Max.: n/2

CYC

+ 10

Select a gear cycle of

1 when using the doubler.

Parameter

Symbol

Pin

name

Condi-

tion

Value

Unit

Remarks

Min.

Max.

Cycle time

CYC

CLK

Using the doubler

CLK

CHCL

CLK

CYC

10 1

CYC

CLK

CLCH

CLK

CYC

10 1

CYC

CLK

CYC

CLCH

CHCL

MB91107/108

The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows. However, in this chart source oscillation input means X0 input clock.

CYC

Source oscillation input
(When using the dou-
blure)

PLL system

(CHC bit of GCR set
to "0")

(a) Gear

1 CLK pin

CCK1/0 : "00"

Source oscillation input

2 dividing system

(CHC bit of GCR set
to "1")

(a) Gear

1 CLK pin

CCK1/0 : "00"

(b) Gear

1/2 CLK pin

CCK1/0 : "01"

1/4 CLK pin

CCK1/0 : "10"

(d) Gear

1/8 CLK pin

CCK1/0 : "11"

MB91107/108

(4) Power-on Reset

3.0 V to 3.6 V, AV

0.0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Power supply rising
time

3.3 V

< 0.2 V

before the power
supply rising

Power supply shut
off time

OFF

Repeated opera-
tions

Oscillation stabilizing
time

OSC

100

0.2 V

0.9 V

RST

OFF

OSC

RSTL

Notes

1) Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply volt-

age during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply
voltage.

A voltage rising rate of 50 mV/
ms or less is recommended.

(Oscillation stabilizing

2) Set RST pin to "L" level when turning on the device, at least the t

RSTL

duration after the supply voltage reaches

is necessary before turning the RST to "H" level.

Not less than 3 V

3) If the supply voltage goes below the lower limit of the guaranteed operating voltage range, be sure to restart

the power supply from the V

level. This is because an internal power-on reset must be generated to restart

operation without allowing the internal circuit to run out of control.
The guaranteed operating voltage range of MB91107 is from 3.0 to 3.6 V.

MB91107/108

(5) Normal Bus Access Read/write Operation

3.0 V to 3.6 V, AV

0.0 V, T

C to

*1: When bus timing is delayed by automatic wait insertion or RDY input, add (t

CYC

extended cycle number for

delay) to this rating.

*2: Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively.

Equation: (2 n/2)

CYC

Parameter

Sym-

bol

Pin name

Condi-

tion

Value

Unit

Remarks

Min.

Max.

CS0 to CS7 delay time

CHCSL

CLK

CS0 to CS7

CS0 to CS7 delay time

CHCSH

Address delay time

CHAV

CLK

A24 to A00

Data delay time

CHDV

CLK

D31 to D16

RD delay time

CLRL

CLK

RD delay time

CLRH

WR0, WR1 delay time

CLWL

CLK

WR0 to WR1

WR0, WR1 delay time

CLWH

Valid address

valid data

input time

AVDV

A24 to A00

D31 to D16

CYC

*1
*2

valid data input time

RLDV

D31 to D16

CYC

Data set up

time

DSRH

data hold time

RHDX

MB91107/108

(7) Hold Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit

Remarks

Min.

Max.

BGRNT delay time

CHBGL

CLK

BGRNT

BGRNT delay time

CHBGH

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

pin valid time

HAHV

CYC

CLK

2.4 V

CHBGL

0.8 V

2.4 V

CHBGH

BRQ

BGRNT

CYC

HAHV

XHAL

Each pin

High impedance

MB91107/108

(8) Normal DRAM Mode Read/Write Cycle

3.0 V to 3.6 V, AV

0.0 V, T

C to

*1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

*2 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation: (3 n/2)

CYC

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit Remarks

Min.

Max.

RAS delay time

CLRAH

CLK

RAS

RAS delay time

CHRAL

CAS delay time

CLCASL

CLK

CAS

CAS delay time

CLCASH

ROW address delay time

CHRAV

CLK

A24 to A00

COLUMN address delay time

CHCAV

DW delay time

CHDWL

CLK

DW delay time

CHDWH

Output data delay time

CHDV1

CLK

D31 to D16

RAS

valid data input time

RLDV

RAS

D31 to D16

CYC

*1
*2

CAS

valid data input time

CLDV

CAS

D31 to D16

CYC

CAS

data hold time

CADH

MB91107/108

(9) Normal DRAM Mode Fast Page Read/Write Cycle

3.0 V to 3.6 V, AV

0.0 V, T

C to

* : When Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CAS delay time

CLCASL

CLK

CAS

CAS delay time

CLCASH

COLUMN address delay time

CHCAV

CLK

A24 to A00

DW delay time

CHDWH

CLK, DW

Output data delay time

CHDV1

CLK

D31 to D16

CAS

valid data input time

CLDV

CAS

D31 to D16

CYC

CAS

data hold time

CADH

MB91107/108

(10) Single DRAM Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit Remarks

Min.

Max.

RAS delay time

CLRAH2

CLK

RAS

RAS delay time

CHRAL2

CAS delay time

CHCASL2

CLK

CAS

CYC

CHCASH2

CAS delay time

CHCASH2

ROW address delay time

CHRAV2

CLK

A24 to A00

COLUMN address delay
time

CHCAV2

DW delay time

CHDWL2

CLK

DW delay time

CHDWH2

Output data delay time

CHDV2

CLK,

D31 to D16

CAS

Valid data input

time

CLDV2

CAS

D31 to D16

CYC

CAS

data hold time

CADH2

MB91107/108

COLUMN-2

CHCASH2

CHRAL2

CHDWH2

CHDWL2

CHDV2

D31 to D16

CLK

D31 to D16

RAS

CAS

A24 to A00

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Q4S

CADH2

CLDV2

CHRAV2

CHCAV2

CHCASL2

CYC

2.4 V

CLRAH2

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

COLUMN-0

COLUMN-1

(Read)

(Write)

ROW address

Read

-0

Read

-1

Read

-2

Write-0

Write-1

Write-2

*1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.

*2 :

indicates the timing when the bus cycle begins from the high speed page mode.

MB91107/108

(11) Hyper DRAM Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit Remarks

Min.

Max.

RAS delay time

CLRAH3

CLK

RAS

RAS delay time

CHRAL3

CAS delay time

CHCASL3

CLK

CAS

CYC

CHCASH3

CAS delay time

CHCASH3

ROW address delay time

CHRAV3

CLK

A24 to A00

COLUMN address delay time

CHCAV3

RD delay time

CHRL3

CLK

RD delay time

CHRH3

RD delay time

CLRL3

DW delay time

CHDWL3

CLK

DW delay time

CHDWH3

Output data delay time

CHDV3

CLK

D31 to D16

CAS

valid data input time

CLDV3

CAS

D31 to D16

CYC

CAS

data hold time

CADH3

MB91107/108

CHCASH3

CHRAL3

CHDWH3

CHDWL3

CHDV3

D31 to D16

CLK

D31 to D16

RAS

CAS

A24 to A00

2.4 V

0.8 V

2.4 V
0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Q4H

0.8 V

CADH3

CLDV3

CHRAV3

CLRL3

0.8 V

CHRL3

CHCASL3

CYC

2.4 V

CLRAH3

2.4 V

0.8 V

2.4 V

0.8 V

COLUMN-0

COLUMN-1

COLUMN-2

CHRH3

CHCAV3

0.8 V

2.4 V

0.8 V

(Read)

(Write)

ROW address

Read

-0

Read

-1

Write-0

Write-1

Write-2

*1 : Q4S indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle.

*2 :

indicates the timing when the bus cycle begins from the high speed page mode.

MB91107/108

(14) UART Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

Notes: · This rating is for AC characteristics in CLK synchronous mode.

· t

CYCP

: A cycle time of peripheral system clock

Parameter

Symbol Pin name

Condition

Value

Unit Remarks

Min.

Max.

Serial clock cycle time

SCYC

Internal shift
clock mode

8 t

CYCP

SCLK

SOUT delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

valid SIN hold time

SHIX

Serial clock "H" pulse width

SHSL

External shift
clock mode

4 t

CYCP

Serial clock "L" pulse width

SLSH

4 t

CYCP

SCLK

SOUT delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

valid SIN hold time

SHIX

MB91107/108

(16) DMA Controller Timing

3.0 V to 3.6 V, AV

0.0 V, T

C to

Parameter

Symbol

Pin name

Condi-

tion

Value

Unit

Remarks

Min.

Max.

DREQ input pulse
width

DRWH

DREQ0 to

DREQ2

2 t

CYC

DACK delay time
(Normal bus)
(Normal DRAM)

CLDL

CLK

DACK0 to

DACK2

CLDH

EOP delay time
(Normal bus)
(Normal DRAM)

CLEL

CLK

EOP0 to EOP2

CLEH

DACK delay time
(Single DRAM)
(Hyper DRAM)

CHDL

CLK

DACK0 to

DACK2

CYC

CHDH

EOP delay time
(Single DRAM)
(Hyper DRAM)

CHEL

CLK

EOP0 to EOP2

CYC

CHEH

CLK

DREQ0 to DREQ2

2.4 V

0.8 V

2.4 V

DACK0 to DACK2
EOP0 to EOP2

DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)

CYC

DRWH

CLDL

CLEL

CHDL

CHEL

CLDH

CLEH

CHDH

CHEH

(Normal bus)
(Normal DRAM)

MB91107/108

A/D Converter Block Electrical Characteristics

(AV

3.0 V to

3.6 V, AV

0.0 V, AVRH

3.0 V to

3.6 V, T

C to

*1: AV

= V

= 3.0 V to 3.6 V(for a machine clock of 25 MHz).

*2: Current value for A/D converters not in operation, CPU stop mode (V

= AV

= AVRH = 3.6 V)

Notes: · As the absolute value of AVRH decreases, relative error increases.

· Output impedance of external circuit of analog input under following conditions;

Output impedance of external circuit < 7 k

If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling.

Parameter

Symbol

Pin name

Value

Unit

Min.

Typ.

Max.

Resolution

bit

Total error

4.0

LSB

Linearity error

3.0

LSB

Differentiation linearity error

2.5

LSB

Zero transition voltage

AN0 to AN3

1.5

0.5

2.5

LSB

Full-scale transition voltage

FST

AN0 to AN3

AVRH

4.5

AVRH

1.5

AVRH

0.5

LSB

Conversion time

5.6*

Analog port input current

AIN

AN0 to AN3

0.1

Analog input voltage

AIN

AN0 to AN3

AVRH

Reference voltage

AVRH

Power supply current

500

Reference voltage supply
current

AVRH

500

Conversion variance between
channels

AN0 to AN3

LSB

Analog input circuit model plan

ON1

: 5 k

ON2

: 620

ON3

: 620

ON4

: 480

: 2 pF

ON1

ON2

ON3

ON4

Sample and hold circuit

Analog input

Comparator

Note: Listed values are for reference purposes only.

ONX

, C

are preliminary value.

MB91107/108

A/D Converter Glossary

· Resolution

The smallest change in analog voltage detected by A/D converter.

· Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000
0000"

"00 0000 0001") to the full-scale transition point (between "11 1111 1110"

"11 1111 1111").

· Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

{1 LSB

}

FST

AVRL

AVRH

1)T

Linearity error

Differential linearity error

Digital output

Actual conversion characteristic

Analog input

Linearity error of digital output N

{1 LSB

}

1 LSB

[LSB]

Differential linearity error of digital output N

V (

)

1 LSB

FST

1022

[V]

1 LSB (Ideal value)

AVRH

AVRL

1024

[V]

: A voltage for causing transition of digital output from (000)

to (001)

FST

: A voltage for causing transition of digital output from (3FE)

to (3FF)

: A voltage for causing transition of digital output from (N

1) to N

[LSB]

Actual conversion
characteristic

Actual conversion
character

istic

(Measured
value)

(Measured
val

ue)

(Measured
value)

(Measured

value)

Ideal val

Ideal valu

MB91107/108

· Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error, full-
scale transition error and linearity error.

{1 LSB

0.5 LSB}

1 LSB

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

1.5 LSB

0.5 LSB

{1 LSB

0.5 LSB}

Total error

Digital output

Analog input

Total error of digital output N

[LSB]

(Ideal value)

AVRL

0.5 LSB [V]

FST

(Ideal value)

AVRH

1.5 LSB [V]

: A voltage for causing transition of digital output from (N

1) to N

Ideal value

Actual conversion
characteristic

(Measured
value)

Actual conversion
characteristic

MB91107/108

REFERENCE DATA

(1) "H" level output voltage

(2) "L" level output voltage

"H" level output voltage vs. power supply voltage

"L" level output voltage vs. power supply voltage

(3) "H" level input / "L" level input voltage

(CMOS input)

(4) "H"level input / "L" level input voltage

(Hysteresys input)

Input level vs. power supply voltage

(CMOS )

Input level vs. power supply voltage

(Hysteresys )

4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00

2.7

3.0

3.3

3.6

3.9

(V)

140.0

135.0

130.0

125.0

120.0

150.0

110.0

105.0

100.0

2.7

3.0

3.3

3.6

3.9

(V)

3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6

2.7

3.0

3.3

3.6

3.9

(V)

3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6

2.7

3.0

3.3

3.6

3.9

(V)

MB91107/108

(5) Power supply current

100.0

90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0

0.0

2.7

3.0

3.3

3.6

3.9

50 MHz

25 MHz

(mA)

(V)

Power supply current vs. voltage

60.0

50.0

40.0

30.0

20.0

10.0

0.0

2.7

3.0

3.3

3.6

3.9

50 MHz

25 MHz

CCS

(mA)

(V)

Power supply current (sleep mode) vs.

power supply current

100.0

90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0

0.0

2.7

3.0

3.3

3.6

3.9

(V)

CCH

(

Power supply current (stop mode) vs.

power supply voltage

450

400

350

300

250

200

150

100

2.7

3.0

3.3

3.6

3.9

(V)

(

A/D conversion block Power supply current

vs. power supply voltage (25 MHz)

300

280

260

240

220

200

180

160

2.7

3.0

3.3

3.6

3.9

AVRH (V)

(

A/D conversion block reference voltage supply

current vs. voltage (25 MHz)

MB91107/108

INSTRUCTIONS (165 INSTRUCTIONS)

How to Read Instruction Set Summary

(1) Names of instructions

Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.

(2) Addressing modes specified as operands are listed in symbols.

Refer to "2. Addressing mode symbols" for further information.

(3) Instruction types

(4) Hexa-decimal expressions of instructions

(5) The number of machine cycles needed for execution

a: Memory access cycle and it has possibility of delay by Ready function.

b: Memory access cycle and it has possibility of delay by Ready function.

If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.

c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or

if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number

of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

For a, b, c and d, minimum execution cycle is 1.

(6) Change in flag sign

· Flag change

C : Change
: No change
0 : Clear
1 : Set

· Flag meanings

N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag

(7) Operation carried out by instruction

Mnemonic

Type

CYC

NZVC

Operation

Remarks

ADD

Rj,

* ADD

#s5,

,
,

A6
A4

,
,

1
1

,
,

CCCC
CCCC

,
,

Ri + Rj

Ri + s5

,
,

(1)

(2)

(3)

(4)

(5)

(6)

(7)

MB91107/108

2. Addressing Mode Symbols

: Register direct (R0 to R15, AC, FP, SP)

R13

: Register direct (R13, AC)

: Register direct (Program status register)

: Register direct (TBR, RP, SSP, USP, MDH, MDL)

CRi

: Register direct (CR0 to CR15)

CRj

: Register direct (CR0 to CR15)

#i8

: Unsigned 8-bit immediate (128 to 255)

Note: 128 to 1 are interpreted as 128 to 255

#i20

: Unsigned 20-bit immediate (0X80000 to 0XFFFFF)

Note: 0X7FFFF to 1 are interpreted as 0X7FFFF to 0XFFFFF

#i32

: Unsigned 32-bit immediate (0X80000000 to 0XFFFFFFFF)

Note: 0X80000000 to 1 are interpreted as 0X80000000 to 0XFFFFFFFF

#s5

: Signed 5-bit immediate (16 to 15)

#s10

: Signed 10-bit immediate (512 to 508, multiple of 4 only)

#u4

: Unsigned 4-bit immediate (0 to 15)

#u5

: Unsigned 5-bit immediate (0 to 31)

#u8

: Unsigned 8-bit immediate (0 to 255)

#u10

: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)

@dir8

: Unsigned 8-bit direct address (0 to 0XFF)

@dir9

: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10

: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

label9

: Signed 9-bit branch address (0X100 to 0XFC, multiple of 2 only)

label12

: Signed 12-bit branch address (0X800 to 0X7FC, multiple of 2 only)

label20

: Signed 20-bit branch address (0X80000 to 0X7FFFF)

label32

: Signed 32-bit branch address (0X80000000 to 0X7FFFFFFF)

@Ri

: Register indirect (R0 to R15, AC, FP, SP)

@Rj

: Register indirect (R0 to R15, AC, FP, SP)

@(R13, Rj)

: Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14, disp10) : Register relative indirect (disp10: 0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: 0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: 0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+

: Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+

: Register indirect with post-increment (R13, AC)

@SP+

: Stack pop

@SP

: Stack push

(reglist)

: Register list

MB91107/108

Detailed Description of Instructions

· Add/subtract operation instructions (10 instructions)

· Compare operation instructions (3 instructions)

· Logical operation instructions (12 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

ADD

Rj, Ri

* ADD

#s5, Ri

ADD

#i4, Ri

ADD2

#i4, Ri

C
C

A6
A4

A4
A5

1
1

C C C C
C C C C

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

ADDC

Rj, Ri

C C C C Ri + Rj + c

Add operation with
sign

ADDN

Rj, Ri

* ADDN

#s5, Ri

ADDN

#i4, Ri

ADDN2

#i4, Ri

C
C

A2
A0

A0
A1

1
1

Ri + Rj

Ri + s5

Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

SUB

Rj, Ri

C C C C Ri Rj

SUBC

Rj, Ri

C C C C Ri Rj c

Subtract operation with
carry

SUBN

Rj, Ri

Ri Rj

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

CMP

Rj, Ri

* CMP

#s5, Ri

CMP

#i4, Ri

CMP2

#i4, Ri

C
C

A8
A9

1
1

C C C C
C C C C

Ri Rj
Ri s5

Ri + extu (i4)
Ri + extu (i4)

MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

AND

Rj, Ri

AND

Rj, @Ri

ANDH

Rj, @Ri

ANDB

Rj, @Ri

A
A
A
A

82
84
85
86

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri & = Rj
(Ri) & = Rj
(Ri) & = Rj
(Ri) & = Rj

Word
Word
Half word
Byte

Rj, Ri

Rj, @Ri

ORH

Rj, @Ri

ORB

Rj, @Ri

A
A
A
A

92
94
95
96

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri | = Rj
(Ri) | = Rj
(Ri) | = Rj
(Ri) | = Rj

Word
Word
Half word
Byte

EOR

Rj, Ri

EOR

Rj, @Ri

EORH

Rj, @Ri

EORB

Rj, @Ri

A
A
A
A

9C
9D

1 + 2a
1 + 2a
1 + 2a

C C
C C
C C
C C

Ri ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj
(Ri) ^ = Rj

Word
Word
Half word
Byte

MB91107/108

· Bit manipulation arithmetic instructions (8 instructions)

*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH
may be generated.

*2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BORH if "u8&0xF0" leaves an active bit.

*3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates

BEORH if "u8&0xF0" leaves an active bit.

· Add/subtract operation instructions (10 instructions)

*1: DIVOS, DIV1

32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.

*2: DIVOU and DIV1

32 are generated. A total instruction code length of 66 bytes.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

BANDL

#u4, @Ri
(u4: 0 to 0F

)

BANDH

#u4, @Ri
(u4: 0 to 0F

)

* BAND

#u8, @Ri

1 + 2a

(Ri) & = (F0

+ u4)

(Ri) & = ((u4<<4) + 0F

)

(Ri) & = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BORL

#u4, @Ri
(u4: 0 to 0F

)

BORH

#u4, @Ri
(u4: 0 to 0F

)

* BOR

#u8, @Ri

1 + 2a

(Ri) | = u4

(Ri) | = (u4<<4)

(Ri) | = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BEORL

#u4, @Ri
(u4: 0 to 0F

)

BEORH

#u4, @Ri
(u4: 0 to 0F

)

* BEOR

#u8, @Ri

1 + 2a

(Ri) ^ = u4

(Ri) ^ = (u4<<4)

(Ri) ^ = u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BTSTL

#u4, @Ri
(u4: 0 to 0F

)

BTSTH

#u4, @Ri
(u4: 0 to 0F

)

2 + a

0 C

C C

(Ri) & u4

(Ri) & (u4<<4)

Test lower 4 bits

Test upper 4 bits

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MUL

Rj, Ri

MULU

Rj, Ri

MULH

Rj, Ri

MULUH

Rj, Ri

A
A
A
A

5
5
3
3

C C C
C C C
C C
C C

MDH, MDL

MDL

32-bit

32-bit = 64-bit

Unsigned
16-bit

16-bit = 32-bit

Unsigned

DIVOS

DIVOU

DIV1

DIV2

DIV3
DIV4S
* DIV

* DIVU

E
E
E
E
E
E

97 4
97 5
97 6
97 7

9F 6
9F 7

1
1
d
1
1
1

C C
C C

C C

C C

MDL/Ri

MDL,

MDL%Ri

MDH

MDL/Ri

MDL,

MDL%Ri

MDH

Step calculation
32-bit/32-bit = 32-bit

Unsigned

MB91107/108

· Shift arithmetic instructions (9 instructions)

· Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer

instruction) (3 instructions)

*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.

If an immediate value contains relative value or external reference, assembler selects i32.

· Memory load instructions (13 instructions)

NoteThe relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:
disp8

o8 = disp8:Each disp is a code extension.

disp9

o8 = disp9>>1:Each disp is a code extension.

disp10

o8 = disp10>>2:Each disp is a code extension.

udisp6

u4 = udisp6>>2:udisp4 is a 0 extension.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LSL

Rj, Ri

* LSL

#u5, Ri

LSL

#u4, Ri

LSL2

#u4, Ri

C
C

B6
B4
B4
B5

1
1
1
1

C C C
C C C
C C C
C C C

Ri<<Rj

Ri<<u5

Ri<<u4

Ri<<(u4 + 16)

Logical shift

LSR

Rj, Ri

* LSR

#u5, Ri

LSR

#u4, Ri

LSR2

#u4, Ri

C
C

B2
B0
B0
B1

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

ASR

Rj, Ri

* ASR

#u5, Ri

ASR

#u4, Ri

ASR2

#u4, Ri

C
C

B8
B8
B9

1
1
1
1

C C C
C C C
C C C
C C C

Ri>>Rj

Ri>>u5

Ri>>u4

Ri>>(u4 + 16)

Logical shift

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDI: 32

#i32, Ri

LDI: 20

#i20, Ri

LDI: 8

#i8, Ri

* LDI

# {i8 | i20 | i32}, Ri

9F 8

3
2

i32

i20

{i8 | i20 | i32}

Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

@Rj, Ri

@(R13, Rj), Ri

@(R14, disp10), Ri

@(R15, udisp6), Ri

@R15 +, Ri

@R15 +, Rs

@R15 +, PS

A
A
B

E
E

04
00
20
03

07 0
07 8

07 9

b
b
b
b
b
b

1 + a + b

C C C C

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + udisp6)

(R15)

Ri, R15 + = 4

(R15)

Rs, R15 + = 4

(R15)

PS, R15 + = 4

Rs: Special-purpose

LDUH

@Rj, Ri

LDUH

@(R13, Rj), Ri

LDUH

@(R14, disp9), Ri

A
A
B

05
01
40

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp9)

Zero-extension
Zero-extension
Zero-extension

LDUB

@Rj, Ri

LDUB

@(R13, Rj), Ri

LDUB

@(R14, disp8), Ri

A
A
B

06
02
60

b
b
b

(Rj)

(R13 + Rj)

(R14 + disp8)

Zero-extension
Zero-extension
Zero-extension

MB91107/108

100

· Memory store instructions (13 instructions)

NoteThe relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:
disp8

o8 = disp8:Each disp is a code extension.

disp9

o8 = disp9>>1:Each disp is a code extension.

disp10

o8 = disp10>>2:Each disp is a code extension.

udisp6

u4 = udisp6>>2:udisp4 is a 0 extension.

· Transfer instructions between registers/special-purpose registers transfer instructions

(5 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

Ri, @Rj

Ri, @(R13, Rj)

Ri, @(R14, disp10)

Ri, @(R15, udisp6)

Ri, @R15

Rs, @R15

PS, @R15

A
A
B

E
E

14
10
30
13

17 0
17 8

17 9

a
a
a
a
a
a

(Rj)

(R13 + Rj)

(R14 + disp10)

(R15 + usidp6)

R15 = 4, Ri

(R15)

R15 = 4, Rs

(R15)

R15 = 4, PS

(R15)

Word
Word
Word

Rs: Special-purpose

STH

Ri, @Rj

STH

Ri, @(R13, Rj)

STH

Ri, @(R14, disp9)

A
A
B

15
11
50

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp9)

Half word
Half word
Half word

STB

Ri, @Rj

STB

Ri, @(R13, Rj)

STB

Ri, @(R14, disp8)

A
A
B

16
12
70

a
a
a

(Rj)

(R13 + Rj)

(R14 + disp8)

Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

MOV

Rj, Ri

MOV

Rs, Ri

MOV

Ri, Rs

MOV

PS, Ri

MOV

Ri, PS

E
E

17 1
07 1

C C C C

Transfer between
general-purpose
registers
Rs: Special-purpose

Rs: Special-purpose

MB91107/108

101

· Non-delay normal branch instructions (23 instructions)

Notes: · "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.

· The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.
label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· RETI must be operated while S flag = 0.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP

@Ri

97 0

CALL

label12

CALL

@Ri

97 1

PC + 2

RP,

PC + 2 + rel11

PC + 2

RP, Ri

RET

97 2

Return

INT

#u8

3+3a

SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

I flag,

S flag,

(TBR + 3FC u8

INTE

9F 3 3 + 3a SSP = 4, PS

(SSP),

SSP = 4,
PC + 2

(SSP),

S flag,

(TBR + 3D8 u8

For emulator

RETI

97 3 2 + 2a C C C C (R15)

PC, R15 = 4,

(R15)

PS, R15 = 4

BNO

label9

BRA

label9

BEQ

label9

BNE

label9

BNC

label9

BNV

label9

BLT

label9

BGE

label9

BLE

label9

BGT

label9

BLS

label9

BHI

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

E1
E0
E2
E3
E4
E5
E6
E7
E8
E9

EA
EB

EC
ED

1
2

2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1

Non-branch
PC + 2 + rel8

PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0

MB91107/108

102

· Branch instructions with delays (20 instructions)

Notes: · The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.

label9

rel8 = (label9 PC 2)/2

label12

rel11 = (label12 PC 2)/2

· Delayed branch operation always executes next instruction (delay slot) before making a branch.
· Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other

instruction is stored, this device may operate other operation than defined.

The instruction described "1" in the other cycle column than branch instruction.
The instruction described "a", "b", "c" or "d" in the cycle column.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

JMP:D

@Ri

9F 0

CALL:D

label12

CALL:D

@Ri

9F 1

PC + 4

RP,

PC + 2 + rel11

PC + 4

RP, Ri

RET:D

9F 2

Return

BNO:D

label9

BRA:D

label9

BEQ:D

label9

BNE:D

label9

BC:D

label9

BNC:D

label9

BN:D

label9

BP:D

label9

BV:D

label9

BNV:D

label9

BLT:D

label9

BGE:D

label9

BLE:D

label9

BGT:D

label9

BLS:D

label9

BHI:D

label9

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

F1
F0
F2
F3
F4
F5
F6
F7
F8
F9

FA
FB

FC
FD

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Non-branch
PC + 2 + rel8

MB91107/108

103

· Direct addressing instructions

NoteThe relations between the dir field of TYPE-D in the instruction format and the assembler description from

disp8 to disp10 are as follows:
disp8

dir + disp8:Each disp is a code extension

disp9

dir = disp9>>1:Each disp is a code extension

disp10

dir = disp10>>2:Each disp is a code extension

· Resource instructions (2 instructions)

· Co-processor instructions (4 instructions)

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

DMOV

@dir10, R13

DMOV

R13, @dir10

DMOV

@dir10, @R13+

DMOV

@R13+, @dir10

DMOV

@dir10, @R15

DMOV

@R15+, @dir10

D
D
D
D
D
D

08
18

0C
1C

0B
1B

b
a

2a
2a
2a
2a

(dir10)

R13

(dir10)

(R13), R13 + = 4

(R13)

(dir10), R13 + = 4

R15 = 4, (dir10)

(R15)

(dir10), R15 + = 4

Word
Word
Word
Word
Word
Word

DMOVH

@dir9,

R13

DMOVH

R13, @dir9

DMOVH

@dir9,

@R13+

DMOVH

@R13+, @dir9

D
D
D
D

09
19

0D
1D

b
a

2a
2a

(dir9)

R13

(dir9)

(R13), R13 + = 2

(R13)

(dir9), R13 + = 2

Half word
Half word
Half word
Half word

DMOVB

@dir8,

R13

DMOVB

R13, @dir8

DMOVB

@dir8,

@R13+

DMOVB

@R13+, @dir8

D
D
D
D

0A
1A
0E
1E

b
a

2a
2a

(dir8)

R13

(dir8)

(R13), R13 + +

(R13)

(dir8), R13 + +

Byte
Byte
Byte
Byte

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

LDRES

@Ri+,

#u4

(Ri)

u4 resource

Ri + = 4

u4: Channel number

STRES

#u4, @Ri+

resource

(Ri)

Ri + = 4

u4: Channel number

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

COPOP

#u4, #CC, CRj, CRi

COPLD

#u4, #CC, Rj,

CRi

COPST

#u4, #CC, CRj, Ri

COPSV

#u4, #CC, CRj, Ri

E
E
E
E

9F C
9F D
9F E
9F F

2 + a

1 + 2a
1 + 2a
1 + 2a

Calculation
Rj

CRi

CRj

No error traps

MB91107/108

104

· Other instructions (16 instructions)

*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler

description s10 is as follows.
s10

s8 = s10>>2

*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler

description u10 is as follows.
u10

u8 = u10>>2

*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,

assembler generates LDM1. Both LDM0 and LDM1 may be generated.

*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following

calculation; a

(n 1) + b + 1 when "n" is number of registers specified.

*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,

assembler generates STM1. Both STM0 and STM1 may be generated.

*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following

calculation; a

n + 1 when "n" is number of registers specified.

Mnemonic

Type

Cycle N Z V C

Operation

Remarks

NOP

9F A

No changes

ANDCCR #u8
ORCCR

#u8

D
D

83
93

c
c

C C C C
C C C C

CCR and u8

CCR

CCR or u8

CCR

STILM

#u8

ILM

Set ILM immediate
value

ADDSP

#s10

R15 + = s10

ADD SP instruction

EXTSB

EXTUB

EXTSH

EXTUH

E
E
E
E

97 8
97 9

97 A
97 B

1
1
1
1

Sign extension 8

32 bits

Zero extension 8

32 bits

Sign extension 16

32 bits

Zero extension 16

32 bits

LDM0

(reglist)

LDM1

(reglist)

* LDM

(reglist)

(R15)

reglist,

R15 increment
(R15)

reglist,

R15 increment
(R15 + +)

reglist,

Load-multi R0 to R7

Load-multi R8 to R15

Load-multi R0 to R15

STM0

(reglist)

STM1

(reglist)

* STM2

(reglist)

R15 decrement,
reglist

(R15)

R15 decrement,
reglist

(R15)

reglist

(R15 + +)

Store-multi R0 to R7

Store-multi R8 to R15

Store-multi R0 to R15

ENTER

#u10

1+a

R14

(R15 4),

R15 4

R14,

R15 u10

R15

Entrance processing
of function

LEAVE

9F 9

R14 + 4

R15,

(R15 4)

R14

Exit processing of
function

XCHB

@Rj, Ri

TEMP,

(Rj)

Ri,

TEMP

(Rj)

For SEMAFO
management
Byte data

MB91107/108

105

· 20-bit normal branch macro instructions

*1: CALL20

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL

@Ri

*2: BRA20

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP

@Ri

*3: Bcc20 (BEQ20 to BHI20)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20

label20, Ri

Next instruction address

RP, label20

Ri: Temporary register

* BRA20

label20, Ri

* BEQ20

label20, Ri

* BNE20

label20, Ri

* BC20

label20, Ri

* BNC20

label20, Ri

* BN20

label20, Ri

* BP20

label20, Ri

* BV20

label20, Ri

* BNV20

label20, Ri

* BLT20

label20, Ri

* BGE20

label20, Ri

* BLE20

label20, Ri

* BGT20

label20, Ri

* BLS20

label20, Ri

* BHI20

label20, Ri

label20

if (Z = = 1) then label20

ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0

Ri: Temporary register

MB91107/108

106

· 20-bit delayed branch macro instructions

*1: CALL20:D

(1) If label20 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

CALL:D @Ri

*2: BRA20:D

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20

#label20, Ri

JMP:D

@Ri

*3: Bcc20:D (BEQ20:D to BHI20:D)

(1) If label20 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label20 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20

#label20, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL20:D label20, Ri

Next instruction address + 2

RP, label20

Ri: Temporary register

* BRA20:D label20, Ri
* BEQ20:D label20, Ri
* BNE20:D label20, Ri
* BC20:D

label20, Ri

* BNC20:D label20, Ri
* BN20:D

label20, Ri

* BP20:D

label20, Ri

* BV20:D

label20, Ri

* BNV20:D label20, Ri
* BLT20:D

label20, Ri

* BGE20:D label20, Ri
* BLE20:D

label20, Ri

* BGT20:D label20, Ri
* BLS20:D

label20, Ri

* BHI20:D

label20, Ri

label20

if (Z = = 1) then label20

Ri: Temporary register

MB91107/108

107

· 32-bit normal macro branch instructions

*1: CALL32

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL

label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL

@Ri

*2: BRA32

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP

@Ri

*3: Bcc32 (BEQ32 to BHI32)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32

label32, Ri

Next instruction address

RP, label32

Ri: Temporary register

* BRA32

label32, Ri

* BEQ32

label32, Ri

* BNE32

label32, Ri

* BC32

label32, Ri

* BNC32

label32, Ri

* BN32

label32, Ri

* BP32

label32, Ri

* BV32

label32, Ri

* BNV32

label32, Ri

* BLT32

label32, Ri

* BGE32

label32, Ri

* BLE32

label32, Ri

* BGT32

label32, Ri

* BLS32

label32, Ri

* BHI32

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

MB91107/108

108

· 32-bit delayed macro branch instructions

*1: CALL32:D

(1) If label32 PC 2 is between 0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

CALL:D @Ri

*2: BRA32:D

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

BRA:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32

#label32, Ri

JMP:D

@Ri

*3: Bcc32:D (BEQ32:D to BHI32:D)

(1) If label32 PC 2 is between 0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label32 PC 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32

#label32, Ri

JMP:D

@Ri

false:

Mnemonic

Operation

Remarks

* CALL32:D label32, Ri

Next instruction address + 2

RP, label32

Ri: Temporary register

* BRA32:D label32, Ri
* BEQ32:D label32, Ri
* BNE32:D label32, Ri
* BC32:D

label32, Ri

* BNC32:D label32, Ri
* BN32:D

label32, Ri

* BP32:D

label32, Ri

* BV32:D

label32, Ri

* BNV32:D label32, Ri
* BLT32:D

label32, Ri

* BGE32:D label32, Ri
* BLE32:D

label32, Ri

* BGT32:D label32, Ri
* BLS32:D

label32, Ri

* BHI32:D

label32, Ri

label32

if (Z = = 1) then label32

Ri: Temporary register

MB91107/108

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
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Tel: +81-3-5322-3347
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Singapore 556741
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Korea

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Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111

F0101

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.

Document Outline

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Document Outline

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