DS07-16303-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit RISC Microcontroller

CMOS

FR30 Series MB91121

MB91121

DESCRIPTION

The MB91121 is a microcontroller with a 32-bit RISC CPU (FR family *) as the core, incorporating a variety of
I/O resources, a bus control facility, and a multiplier-accumulator (simplified DSP) with internal program RAM for
built-in control applications which require advanced, high-speed CPU processing.

While being based on external bus access for supporting a vast address space accessed by the 32-bit CPU, it
contains 1 K bytes of instruction cache memory and 4 K bytes of RAM (8 K bytes when the DSP is not used) for
speeding up the execution of instructions by the CPU.

In this way, the device is designed for built-in applications which require high performance and processing power
of the CPU, such as digital camera, navigation system, and high-performance FAX, and printer controls.

* : FR Family stands for FUJITSU RISC controller.

FEATURES

FR CPU

· 32-bit RISC, load/store architecture, 5-stage pipeline
· Operating clock frequency : Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
· General purpose registers : 32 bits

· 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle
· Memory to memory transfer, bit processing, barrel shifter processing : Optimized for embedded applications

(Continued)

PACKAGE

120-pin plastic LQFP

(FPT-120P-M21)

MB91121

(Continued)

· Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

· Register interlock functions, efficient assembly language coding
· Branch instructions with delay slots : Reduced overhead time in branch executions
· Internal multiplier/supported at instruction level

Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles

· Interrupt (push PC and PS) : 6 cycles, 16 priority levels

Bus interface

· Clock doublure : Internal 50 MHz, external bus 25 MHz operation
· 25-bit address bus (32 Mbytes memory space)
· 8/16-bit data bus
· Basic external bus cycle : 2 clock cycles
· Chip select outputs for setting down to a minimum memory block size of 64 Kbytes : 6
· Interface supported for various memory technologies

DRAM interface (area 4 and 5)

· Automatic wait cycle insertion : Flexible setting, from 0 to 7 for each area
· Unused data/address pins can be configured us input/output ports
· Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

· 2 banks independent control (area 4 and 5)
· Double CAS DRAM (Normal DRAM I/F) /Single CAS DRAM/Hyper DRAM
· Basic bus cycle : Normally 5 cycles, 2-cycle access possible in high-speed page mode
· Programmable waveform : Automatic 1-cycle wait insertion to RAS and CAS cycles
· DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode

· Supports 8/9/10/12-bit column address width
· 2CAS/1WE, 2WE/1CAS selective

DSP Macros (Simplified DSP)

· High-speed multiply-accumulate operation (1 machine cycle)
· Data format :

16-bit fixed-point (16

40 bits)

· Instruction area :

256 words

16 bits

· Data area :

64 words

16 bits

1 set, 1024 words

16 bits

2 sets (banks)

· Capable of rounding and saturation processing
· Number of terms in addition : Up to 32 terms
· Instructions :

MAC, STR, and JMP instructions

· Delay processing :

Capable of free transfer within 32 words

· Fixed-point system :

Capable of selection from among Q12 to Q15

· Program execution control :

Capable of externally selecting eight calculation programs

· Variable monitoring :

Capable of monitoring calculation results of up to 4 words without stopping the

program

· Efficient data variable areas : Two banks of data variable areas provided, enabling the CPU to execute a DSP

calculation program using one bank while accessing a data variable in the other.

Cache memory

· 1 K-byte instruction cache
· 2-way set-associative configuration
· 32 blocks/way, 4 entries (4 words) /block

MB91121

(Continued)

· Lock feature: Keeping a specific program code resident in the cache

DMAC (DMA Controller)

· 8 channels
· Transfer incident/external pins/UART interrupt requests/DSP Macros/Software start
· Transfer sequence : Step transfer/block transfer/burst transfer/continuous transfer
· Transfer data length : 8 bits/16 bits/32 bits selective
· Interrupt request enables temporary stop operation

UART

· 3 independent channels
· Full-duplex double buffer
· Data length : 7 bits to 9 bits (non-parity) , 6 bits to 8 bits (parity)
· Asynchronous (start-stop system) , CLK-synchronized communication selective
· Multi-processor mode
· Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator : Generates any given baud rate
· Use external clock can be used as a transfer clock
· Error detection : Parity, frame, overrun

D converter

(

successive approximation conversion type

)

· 10-bit resolution, 8 channels
· Successive approximation type : Conversion time of 5.6

s at 25 MHz

· Internal sample and hold circuit
· Conversion mode : Single conversion/scanning conversion/repeated conversion selective
· Start : Software/external trigger/internal timer selective

Reload timer

· 16-bit timer : 3 channels
· Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective

10. Other interval timers

· 16-bit timer : 3 channels (U-TIMER)
· PWM timer : 4 channels
· Watchdog timer : 1 channel

11. Bit search module

· First bit transition "1" or "0" from MSB can be detected in 1 cycle

12. Interrupt controller

· External interrupt input : Non-maskable interrupt (NMI) , normal interrupt

8 (INT0 to INT7)

· Internal interrupt incident : UART, DMA controller (DMAC) , A/D converter, U-TIMER, delayed interrupt

module and DSP Macros

· Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)

Others

Reset cause

· Power-on reset/watchdog timer/software reset/external reset

Low-power consumption mode

· Sleep mode/stop mode

Clock control

· Gear function : Operating clocks for CPU and peripherals are independently selective

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
However, operating frequency for peripherals is less than 25 MHz.

MB91121

PIN ASSIGNMENT

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

PB5/CS1L

PB6/CS1H

PB7/DW1

CS0

PA1/CS1
PA2/CS2
PA3/CS3
PA4/CS4
PA5/CS5
PA6/CLK

NMI

MD3

RST

MD0
MD1
MD2

P80/RDY

P81/BGRNT

P82/BRQ

WR0

P85/WR1

P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

PG5/INT5/TRG1
PG4/INT4/TRG0
PG3/INT3
PG2/INT2
PG1/INT1
PG0/INT0
V

PH7/OCPA3
PH6/OCPA2
PH5/OCPA1
PH4/OCPA0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AV

/AVRL

AVRH
AV

A24
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61

P26/D22

P27/D23

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

P60/A16

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

RAS1/PB4

DW0/PB3

CSOH/PB2

CSOL/PB1

RAS0/PB0

PI1/EOP2/ATG

PI0/DACK2

PE7/DREQ2

PE6/EOP1

PE5/DACK1

PE4/DREQ1

PE3/EOP0

PE2/DACK0

PE1/DREQ0

PE0/SC2

PF7/SO2

PF6/SI2

PF5/SC1

PF4/SO1

PF3/SI1

PF2/SC0

PF1/SO0

PF0/SI0

PG7/INT7/TRG3

PG6/INT6/TRG2

(TOP VIEW)

(FPT-120P-M21)

MB91121

PIN DESCRIPTION

Pin no.

Pin name

Circuit type

Function

1
2
3
4
5
6
7

A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67

Bits 16 to 23 for the external address bus.
When not used for the address bus, these pins serve as ports (P60
to P67) .

A24

Bit 24 for the external address bus

A/D converter V

power supply

AVRH

A/D converter reference voltage (high potential side)
The V

pin must be applied with voltage equal to or higher than

the voltage at this pin (AVRH) when the AVRH pin is turned on or
off.

/AVRL

A/D converter V

power supply or reference voltage (low potential

side)

12 to 19

AN0 to AN7

[AN0 to AN7] A/D converter analog input. This function is enabled
with the AIC register set for the analog input.

20 to 23

OCPA0/PH4
OCPA1/PH5
OCPA2/PH6
OCPA3/PH7

[OCPA0 to OCPA3] PWM timer output. This function is enabled
with the PWM timer output flag set to "Enabled".

[PH4 to PH7] General-purpose I/O port

25 to 32

INT0/PG0
INT1/PG1
INT2/PG2
INT3/PG3
INT4/PG4/TRG0
INT5/PG5/TRG1
INT6/PG6/TRG2
INT7/PG7/TRG3

[INT0 to INT7] External inter-
rupt request input

Since these inputs are used dur-
ing their respective input opera-
tions, the output by the other
function must remain off unless
used intentionally.

[TRG0 to TRG3] PWM timer
external trigger input

[PG0 to PG7] General-purpose I/O port

SI0/PF0

[SI0] UART0 data input. Since this input is used whenever
UART0 is in input operation, the output by the other function must
remain off unless used intentionally.

[PF0] General-purpose I/O port

SO0/PF1

[SO0] UART0 data output. This function is enabled with the
UART0 data output flag set to "Enabled".

[PF1] General-purpose I/O port. This function is enabled with the
UART0 data output flag set to "Disabled".

SC0/PF2

[SC0] UART0 clock input/output. The clock output is enabled with
the UART0 clock output flag set to "Enabled".

[PF2] General-purpose I/O port. This function is enabled with the
UART0 clock output flag set to "Disabled".

(Continued)

MB91121

SI1/PF3

[SI1] UART1 data input. Since this input is used whenever
UART1 is in input operation, the output by the other function must
remain off unless used intentionally.

[PF3] General-purpose I/O port

SO1/PF4

[SO1] UART1 data output. This function is enabled with the
UART1 data output flag set to "Enabled".

[PF4] General-purpose I/O port. This function is enabled with the
UART1 data output flag set to "Disabled".

SC1/PF5

[SC1] UART1 clock input/output. The clock output is enabled with
the UART1 clock output flag set to "Enabled".

[PF5] General-purpose I/O port. This function is enabled with the
UART1 clock output flag set to "Disabled".

SI2/PF6

[SI2] UART2 data input. Since this input is used whenever
UART2 is in input operation, the output by the other function must
remain off unless used intentionally.

[PF6] General-purpose I/O port

SO2/PF7

[SO2] UART2 data output. This function is enabled with the
UART2 data output flag set to "Enabled".

[PF7] General-purpose I/O port. This function is enabled with the
UART2 data output flag set to "Disabled".

SC2/PE0

[SC2] UART2 clock input/output. The clock output is enabled with
the UART2 clock output flag set to "Enabled".

[PE0] General-purpose I/O port. This function is enabled with the
UART2 clock output flag set to "Disabled".

DREQ0/PE1

[DREQ0] DMA external transfer request input (ch0) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.

[PE1] General-purpose I/O port

DACK0/PE2

[DACK0] DMAC external transfer request acknowledge output
(ch0) . This function is enabled with the DMAC transfer request ac-
knowledge output flag set to "Enabled".

[PE2] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to "Disabled".

EOP0/PE3

[EOP0] DMAC EOP output (ch0) . This function is enabled with
the EOP output flag set to "Enabled".

[PE3] General-purpose I/O port

DREQ1/PE4

[DREQ1] DMA external transfer request input (ch1) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.

[PE4] General-purpose I/O port

(Continued)

Pin no.

Pin name

Circuit type

Function

(Continued)

MB91121

DACK1/PE5

[DACK1] DMAC external transfer request acknowledge output
(ch1) . This function is enabled with the DMAC transfer request ac-
knowledge output flag set to "Enabled".

[PE5] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to "Disabled".

EOP1/PE6

[EOP1] DMAC EOP output (ch1) . This function is enabled with
the EOP output flag set to "Enabled".

[PE6] General-purpose I/O port

DREQ2/PE7

[DREQ2] DMA external transfer request input (ch2) . Since this
input is used whenever the DMA external transfer request has
been selected as a DMA transfer trigger event, the output by the
other function must remain off unless used intentionally.

[PE7] General-purpose I/O port

DACK2/PI0

[DACK2] DMAC external transfer request acknowledge output
(ch2) . This function is enabled with the DMAC transfer request ac-
knowledge output flag set to "Enabled".

[PI0] General-purpose I/O port. This function is enabled with the
DMAC transfer request acknowledge output flag or DACK0 output
flag set to "Disabled".

EOP2/ATG/PI1

[EOP2] DMAC EOP output (ch2) . This function is enabled with
the EOP output flag set to "Enabled".

[ATG] A/D converter external trigger input. Since this input is used
whenever the A/D converter external trigger signal has been se-
lected as an A/D trigger event, the output by the other function
must remain off unless used intentionally.

[PI1] General-purpose I/O port. This function is enabled with the
DMAC transfer termination signal output flag set to "Disabled".

53
54

X1
X0

Clock (oscillation) input.
Clock (oscillation) output.

56
57
58
59
60

RAS0/PB0
CSOL/PB1
CSOH/PB2
DW0/PB3
RAS1/PB4

RAS output of DRAM bank 0
CASL output of DRAM bank 0
CASH output of DRAM bank 0
WE output of DRAM bank 0 (Low active)
RAS output of DRAM bank 1

[PB0 to PB3] Can serve as a port when not used for signal output.

61
62
63

CS1L/PB5
CS1H/PB6
DW1/PB7

CASL output of DRAM bank 1
CASH output of DRAM bank 1
WE output of DRAM bank 1 (Low active)

[PB5 to PB7] Can serve as a port when not used for signal output.

CS0

Chip select 0 output (Low active) .

(Continued)

Pin no.

Pin name

Circuit type

Function

(Continued)

MB91121

66
67
68
69
70

CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5

Chip select 1 output (Low active) .
Chip select 2 output (Low active) .
Chip select 3 output (Low active) .
Chip select 4 output (Low active) .
Chip select 5 output (Low active) .

[PA1 to PA5] Can serve as a port when not used for signal output.

CLK/PA6

System clock output. This pin outputs the same clock frequency
as the external bus operating frequency.

[PA6] Can serve as a port when not used for signal output.

NMI

NMI (Non Maskable Interrupt) input (Low active) .

MD3

Mode pin 3.
Connect this pin directly to the V

or V

pin.

RST

External reset input.

76
77
78

MD0
MD1
MD2

Mode pins 0 to 2.
These pins are set to MCU basic operation modes.
Connect this pin directly to the V

or V

pin.

RDY/P80

External ready signal input. This pin inputs 0 when the bus cycle
being executed is not completed. It can serve as a port when not
used for that input.

BGRNT/P81

External bus release request acknowledge output. This pin out-
puts the L signal when the eternal bus has been released. The pin
can serve as a port when not used for that output.

BRQ/P82

External bus release request input. Input 1 to this pin to release
the external bus. The pin can serve as a port when not used for
that input.

External bus read strobe.

WR0

External bus write strobe. The control signals and data bus byte
locations have the following relationships.

Note : WR1 remains in the Hi-Z state during a reset. For use with

a 16-bit bus width, add an external pull-up resistor.

WR1/P85

85
86
87
88
89
90
91
92

D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27

External data bus bits 16 to 23.
These pins can be used as ports (P20 to P27) when the external
bus width has been set to 8 bits.

Pin no.

Pin name

Circuit type

Function

16-bit bus width

8-bit bus width

D31 to D24

WR0

D23 to D16

WR1

(Usable as port)

(Continued)

MB91121

Note : In most of the above pins, I/O port and resource I/O are multiplexed xxxx/Pxx. In case of conflict between

output of I/O port and resource I/O, priority is always given to the output of resource I/O.

93
94
95
96
97
98
99

100

D24
D25
D26
D27
D28
D29
D30
D31

External data bus bits 24 to 31.

102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118

A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15

External address bus bits 00 to 15.

120

A16/P60

External address bus bit 16. This pin can serve as a port (P60)
when not used as the address bus.

24
55
64

110

Power supply pin for digital circuit.

34
52
75

101
119

Earth level for digital circuit.

Pin no.

Pin name

Circuit type

Function

(Continued)

MB91121

DRAM CONTROL PIN

Pin name

Data bus 16-bit mode

Data bus 8-bit mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

RAS0

Area 4 RAS

Correspondence of "L"
"H" to lower address 1 bit
(A0) in data bus 16-bit
mode
"L" : "0"
"H" : "1"
CASL : CAS which A0

corresponds to
"0" area

CASH : CAS which A0

corresponds to
"1" area

WEL : WE which A0

corresponds to
"0" area

WEH : WE which A0

corresponds to
"1" area

RAS1

Area 5 RAS

CS0L

Area 4 CASL

Area 4 CAS

CS0H

Area 4 CASH

Area 4 WEL

Area 4 CAS

CS1L

Area 5 CASL

Area 5 CAS

CS1H

Area 5 CASH

Area 5 WEL

Area 5 CAS

DW0

Area 4 WE

Area 4 WEH

Area 4 WE

DW1

Area 5 WE

Area 5 WEH

Area 5 WE

MB91121

HANDLING DEVICES

· Preventing Latchup

In CMOS ICs, applying voltage higher than V

or lower than V

to input/output pin or applying voltage over

rating across V

and V

may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.

Take care that the analog power supply (AV

AVR) and the analog input do not exceed the digital power supply

) when the analog power supply turned on or off.

· Treatment of Unused Pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

· External Reset Input

It takes at least 5 machine cycle to input "L" level to the RST pin and to ensure inner reset operation properly.

· Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops
at "H" output in stop mode) .

And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.

· Power Supply Pins

When there are several V

and V

pins, each of them is equipotentially connected to its counterpart inside of

the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to
prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to
observe the total output current standard, connect all V

and V

pins to the power supply or GND.

It is preferred to connect V

and V

of MB91121 to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1

F between V

and

at a position as close as possible to MB91121.

OPEN

MB91121

Using an external clock (normal)

Note: Can not be used stop mode (oscillation stop mode).

Using an external clock (can be used at 12.5 MHz and less than.)

· Using an external clock

MB91121

· Crystal Oscillator Circuit

Noises around X0 and X1 pins may cause malfunctions of MB91121. In designing the PC board, layout X0, X1
and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.

It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.

· Treatment of N.C. Pins

Make sure to leave N.C. pins open.

· Mode Setting Pins (MD0 to MD3)

Connect mode setting pins (MD0 to MD3) directly to V

or V

Arrange each mode setting pin and V

or V

patterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

· Turning on the Power Supply

When turning on the power supply, never fail to start from setting the RST pin to "L" level. And after the power
supply voltage goes to V

level, at least after ensuring the time for 5 machine cycle, then set to "H" level.

· Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation becomes stable.

· Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting.

· The device contains registers which are initialized only at a power-on reset. When it is expected to initialize

them, recycle the power to execute a power-on reset.

· Even when the A/D converter is not used, make the connections : AV

, AV

MB91121

BLOCK DIAGRAM

Bit Search Module

Instruction Cache (1 KB)

D -bus (32 bit)

I -bus (16 bit)

C-bus (32 bit)

R -bus (16 bit)

Clock Control Unit
(Watct Dog Timer)

Interrupt Control
Unit

10 bit A/D
Converter (8 ch)

Reload Timer (3 ch)

Port

Bus Converter (32 bit

16 bit)

Port 0 to Port B

UART (3 ch)
with
Baud Rate Timer

PWM Timer (4 ch)

DMAC (8 ch)

(Harvard

Princeton)

FR CPU

X0
X1
RST

DREQ0 to DREQ2
DACK0 to DACK2
EOP0 to EOP2

D16 to D31
A00 to A24
RDY
WR0 to WR1
RDY
CLK
CS0 to CS5
BRQ
BGRNT

SI0 to SI2
SO0 to SO2
SC0 to SC2

INT0 to INT7
NMI

RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1

AN0 to AN7
AV

AVRH
AV

AVRL

DRAM Controller

OCPA0 to OCPA3
TRG0 to TRG3

Bus Controller

RAM (4 KB)

(Embedded RAM 4 )

Soft DMA Start Circuit

STRG

DSP macro

Bus Converter

Note : Pins are display for functions (Actually some pins are multiplexer) .

When using REALOS, time control should be done by using external interrupt or inner timer.

MB91121

CPU CORE

Memory Space

The FR family has a logical address space of 4 Gbytes (2

bytes) and the CPU linearly accesses the memory

space.

· Direct addressing area

The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an
address can be specified in a direct operand of a code.

Direct areas consists of the following areas dependent on accessible data sizes.

Byte data access : 000

to 0FF

Half word data access : 000

to 1FF

Word data access : 000

to 3FF

· Memory space

External ROM/external bus mode

I/O

Access inhibited

Embedded RAM 4 KB

Y-RAM1

Access inhibited

DSP Macros

Access inhibited

External area

Direct addressing area

See "

I/O MAP"

0000 0000

0000 0400

0000 0800

0000 1000

0000 2000

0000 2800

0000 3000

0000 F000

0000 F300

0001 0000

FFFF FFFF

Usable as RAM in the DSP Macros YBANK unused mode.

Usable as RAM when DSP Macros is not used.

MB91121

Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.

· Dedicated registers

Program counter (PC) :

32-bit length, indicates the location of the instruction to be executed.

Program status (PS) :

32-bit length, register for storing register pointer or condition codes

Table base register (TBR) : Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)

processing.

Return pointer (RP) :

Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP) : Indicates system stack space.
User's stack pointer (USP) : Indicates user's stack space.
Multiplication/division result register (MDH/MDL) : 32-bit length, register for multiplication/division

· Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR) , a system condition
code register (SCR) and a interrupt level mask register (ILM) .

32 bit

Initial value

Program counter

XXXX XXXX

Indeterminate

Program status

TBR

Table base register

0 0 0 F FC0 0

Return pointer

XXXX XXXX

Indeterminate

SSP

System stack pointer

0 0 0 0 0 0 0 0

USP

User's stack pointer

XXXX XXXX

Indeterminate

MDH

XXXX XXXX

Indeterminate

Multiplication/division result register

MDL

XXXX XXXX

Indeterminate

ILM4 ILM3 ILM2 ILM1 ILM0

ILM

SCR

CCR

MB91121

· Condition code register (CCR)

S-flag :

Specifies a stack pointer used as R15.

I-flag :

Controls user interrupt request enable/disable.

N-flag :

Indicates sign bit when division result is assumed to be in the 2's complement format.

Z-flag :

Indicates whether or not the result of division was "0".

V-flag :

Assumes the operand used in calculation in the 2's complement format and indicates whether

or not overflow has occurred.

C-flag :

Indicates if a carry or borrow from the MSB has occurred.

· System condition code register (SCR)

T-flag :

Specifies whether or not to enable step trace trap.

· Interrupt level mask register (ILM)

ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

High

:
:

Low

MB91121

GENERAL-PURPOSE REGISTERS

R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer (field for indicating address) .

Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.

R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000

(SSP value) .

· Register bank structure

32 bits

Initial value

XXXX XXXX

R12
R13

AC (Accumulator)

R14

FP (Frame Pointer)

XXXX XXXX

R15

SP (Stack Pointer)

0 0 0 0 0 0 0 0

MB91121

SETTING MODE

Pin

· Mode setting pins and modes

* : MB91121 does not support single-chip mode.

Registers

· Mode setting registers (MODR) and modes

· Bus mode setting bits and functions

Note : Because of without internal ROM, MB91121 allows "10

" setting value only.

Mode setting pins

Mode name

Reset vector

access area

External data

bus width

Bus mode

MD3 MD2 MD1 MD0

External vector mode 0

External

8 bits

External ROM/external
bus mode

External vector mode 1

External

16 bits

Inhibited

Internal vector mode

Internal

(Mode register)

Single-chip mode*

Inhibited

Functions

Note

Single-chip mode

Internal ROM/external bus mode

External ROM/external bus mode

Inhibited

W : Write only

X : Indeterminate

* : Always write "0" except for M1 and M0.

Initial value

Access

XXXX XXXX

Address

0000 07FF

Bus mode setting bit

MB91121

I/O MAP

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

0000

(Vacancy)

0001

PDR2

Port 2 data register

R/W

XXXXXXXX

0002

0004

(Vacancy)

0005

PDR6

Port 6 data register

R/W

XXXXXXXX

0006

(Vacancy)

0007

0008

PDRB

Port B data register

R/W

XXXXXXXX

0009

PDRA

Port A data register

R/W

XXXXXX

000A

(Vacancy)

000B

PDR8

Port 8 data register

R/W

- -

XXX

000C

0011

(Vacancy)

0012

PDRE

Port E data register

R/W

XXXXXXXX

0013

PDRF

Port F data register

R/W

XXXXXXXX

0014

PDRG

Port G data register

R/W

XXXXXXXX

0015

PDRH

Port H data register

R/W

XXXX

- - - -

0016

PDRI

Port I data register

R/W

- - - - - -

0017

001B

(Vacancy)

001C

SSR0

Serial status register 0

R/W

0 0 0 0 1

0 0

001D

SIDR0/SODR0

Serial input register 0/serial output register 0

R/W

XXXXXXXX

001E

SCR0

Serial control register 0

R/W

0 0 0 0 0 1 0 0

001F

SMR0

Serial mode register 0

R/W

0 0

- -

0 0

0020

SSR1

Serial status register 1

R/W

0 0 0 0 1

0 0

0021

SIDR1/SODR1

Serial input register 1/serial output register 1

R/W

XXXXXXXX

0022

SCR1

Serial control register 1

R/W

0 0 0 0 0 1 0 0

0023

SMR1

Serial mode register 1

R/W

0 0

- -

0 0

0024

SSR2

Serial status register 2

R/W

0 0 0 0 1

0 0

0025

SIDR2/SODR2

Serial input register 2/serial output register 2

R/W

XXXXXXXX

0026

SCR2

Serial control register 2

R/W

0 0 0 0 0 1 0 0

0027

SMR2

Serial mode register 2

R/W

0 0

- -

0 0

(Continued)

MB91121

0028

TMRLR0

16-bit reload register ch. 0

XXXXXXXX

0029

XXXXXXXX

002A

TMR0

16-bit timer register ch. 0

XXXXXXXX

002B

XXXXXXXX

002C

(Vacancy)

002D

002E

TMCSR0

16-bit reload timer control status register ch. 0

R/W

- - - -

0 0 0 0

002F

0 0 0 0 0 0 0 0

0030

TMRLR1

16-bit reload register ch. 1

XXXXXXXX

0031

XXXXXXXX

0032

TMR1

16-bit timer register ch. 1

XXXXXXXX

0033

XXXXXXXX

0034

(Vacancy)

0035

0036

TMCSR1

16-bit reload timer control status register ch. 1

R/W

- - - -

0 0 0 0

0037

0 0 0 0 0 0 0 0

0038

ADCR

A/D converter data register

- - - - - -

0039

XXXXXXXX

003A

ADCS

A/D converter control status register

R/W

0 0 0 0 0 0 0 0

003B

0 0 0 0 0 0 0 0

003C

TMRLR2

16-bit reload register ch. 2

XXXXXXXX

003D

XXXXXXXX

003E

TMR2

16-bit timer register ch. 2

XXXXXXXX

003F

XXXXXXXX

0040

(Vacancy)

0041

0042

TMCSR2

16-bit reload timer control status register ch. 2

R/W

- - - -

0 0 0 0

0043

0 0 0 0 0 0 0 0

0044

004F

(Vacancy)

0050

STRG

Soft DMA Start

R/W

- - - - - -

0 0

0051

0077

(Vacancy)

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

0078

UTIM0/UTIMR0

U-TIMER register ch. 0/reload register ch. 0

R/W

0 0 0 0 0 0 0 0

0079

0 0 0 0 0 0 0 0

007A

(Vacancy)

007B

UTIMC0

U-TIMER control register ch. 0

R/W

- -

0 0 0 0 1

007C

UTIM1/UTIMR1

U-TIMER register ch. 1/reload register ch. 1

R/W

0 0 0 0 0 0 0 0

007D

0 0 0 0 0 0 0 0

007E

(Vacancy)

007F

UTIMC1

U-TIMER control register ch. 1

R/W

- -

0 0 0 0 1

0080

UTIM2/UTIMR2

U-TIMER register ch. 2/reload register ch. 2

R/W

0 0 0 0 0 0 0 0

0081

0 0 0 0 0 0 0 0

0082

(Vacancy)

0083

UTIMC2

U-TIMER control register ch. 2

R/W

- -

0 0 0 0 1

0084

0093

(Vacancy)

0094

EIRR

External interrupt cause register

R/W

0 0 0 0 0 0 0 0

0095

ENIR

Interrupt enable register

R/W

0 0 0 0 0 0 0 0

0096

0097

(Vacancy)

0098

ELVR

External interrupt request level setting register

0099

R/W

0 0 0 0 0 0 0 0

009A

00D1

(Vacancy)

00D2

DDRE

Port E data direction register

0 0 0 0 0 0 0 0

00D3

DDRF

Port F data direction register

0 0 0 0 0 0 0 0

00D4

DDRG

Port G data direction register

0 0 0 0 0 0 0 0

00D5

DDRH

Port H data direction register

0 0 0 0

- - - -

00D6

DDRI

Port I data direction register

- - - - - -

0 0

00D7

00DB

(Vacancy)

00DC

GCN1

General control register 1

R/W

0 0 1 1 0 0 1 0

00DD

0 0 0 1 0 0 0 0

00DE

(Vacancy)

00DF

GCN2

General control register 2

R/W

0 0 0 0 0 0 0 0

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

00E0

PTMR0

PWM timer register

1 1 1 1 1 1 1 1

00E1

1 1 1 1 1 1 1 1

00E2

PCSR0

PWM cycle setting register

XXXXXXXX

00E3

XXXXXXXX

00E4

PDUT0

PWM duty setting register

XXXXXXXX

00E5

XXXXXXXX

00E6

PCNH0

PWM control status register H

R/W

0 0 0 0 0 0 0

00E7

PCNL0

PWM control status register L

R/W

0 0 0 0 0 0 0 0

00E8

PTMR1

PWM timer register

1 1 1 1 1 1 1 1

00E9

1 1 1 1 1 1 1 1

00EA

PCSR1

PWM cycle setting register

XXXXXXXX

00EB

XXXXXXXX

00EC

PDUT1

PWM duty setting register

XXXXXXXX

00ED

XXXXXXXX

00EE

PCNH1

PWM control status register H

R/W

0 0 0 0 0 0 0

00EF

PCNL1

PWM control status register L

R/W

0 0 0 0 0 0 0 0

00F0

PTMR2

PWM timer register

1 1 1 1 1 1 1 1

00F1

1 1 1 1 1 1 1 1

00F2

PCSR2

PWM cycle setting register

XXXXXXXX

00F3

XXXXXXXX

00F4

PDUT2

PWM duty setting register

XXXXXXXX

00F5

XXXXXXXX

00F6

PCNH2

PWM control status register H

R/W

0 0 0 0 0 0 0

00F7

PCNL2

PWM control status register L

R/W

0 0 0 0 0 0 0 0

00F8

PTMR3

PWM timer register

1 1 1 1 1 1 1 1

00F9

1 1 1 1 1 1 1 1

00FA

PCSR3

PWM cycle setting register

XXXXXXXX

00FB

XXXXXXXX

00FC

PDUT3

PWM duty setting register

XXXXXXXX

00FD

XXXXXXXX

00FE

PCNH3

PWM control status register H

R/W

0 0 0 0 0 0 0

00FF

PCNL3

PWM control status register L

R/W

0 0 0 0 0 0 0 0

0100

01FF

(Vacancy)

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

0200

DPDP

DMAC parameter descriptor pointer

R/W

XXXXXXXX

0201

XXXXXXXX

0202

XXXXXXXX

0203

X 0 0 0 0 0 0 0

0204

DACSR

DMAC control status register

R/W

0 0 0 0 0 0 0 0

0205

0 0 0 0 0 0 0 0

0206

0 0 0 0 0 0 0 0

0207

0 0 0 0 0 0 0 0

0208

DATCR

DMAC pin control register

R/W

XXXXXXXX

0209

XXXX 0 0 0 0

020A

XXXX 0 0 0 0

020B

XXXX 0 0 0 0

020C

020F

(Vacancy)

0210

OFAS

DSP macro register

R/W

- - - -

0 0 0 0

0211

0 0 0 0 0 0 0 0

0212

STRS

- - - -

0 0 0 0

0213

0 0 0 0 0 0 0 0

0214

OFSC

0 0 0 0

- - -

0215

(Vacancy)

0216

OFSS

DSP macro register

R/W

0 0 0 0 0 0 0 0

0217

Y-BANKC

R/W

- -

0 0 0 0 0

0218

OFSD

R/W

0 0 0 0 0 0 0 0

0219

0 0 0 0 0 0 0 0

021A

DSP-PC

R/W

XXXXXXXX

021B

DSP-CSR

R/W

0 0 0 0 0 0 0 0

021C

DSP-LY

R/W

XXXXXXXX

021D

XXXXXXXX

021E

DSP-OT0

XXXXXXXX

021F

XXXXXXXX

0220

DSP-OT1

XXXXXXXX

0221

XXXXXXXX

0222

DSP-OT2

XXXXXXXX

0223

XXXXXXXX

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

0224

DSP-OT3

DSP macro register

XXXXXXXX

0225

XXXXXXXX

0226

03E3

(Vacancy)

03E4

ICHCR

Instruction cache control register

R/W

- - - - - - - -

03E5

- - - - - - - -

03E6

- - - - - - - -

03E7

- -

0 0 0 0 0 0

03E8

03EF

(Vacancy)

03F0

BSD0

Bit search module 0-detection data register

XXXXXXXX

03F1

XXXXXXXX

03F2

XXXXXXXX

03F3

XXXXXXXX

03F4

BSD1

Bit search module 1-detection data register

R/W

XXXXXXXX

03F5

XXXXXXXX

03F6

XXXXXXXX

03F7

XXXXXXXX

03F8

BSDC

Bit search module transition-detection data
register

XXXXXXXX

03F9

XXXXXXXX

03FA

XXXXXXXX

03FB

XXXXXXXX

03FC

BSRR

Bit search module detection result register

XXXXXXXX

03FD

XXXXXXXX

03FE

XXXXXXXX

03FF

XXXXXXXX

0400

ICR00

Interrupt control register 0

R/W

- - -

1 1 1 1 1

0401

ICR01

Interrupt control register 1

R/W

- - -

1 1 1 1 1

0402

ICR02

Interrupt control register 2

R/W

- - -

1 1 1 1 1

0403

ICR03

Interrupt control register 3

R/W

- - -

1 1 1 1 1

0404

ICR04

Interrupt control register 4

R/W

- - -

1 1 1 1 1

0405

ICR05

Interrupt control register 5

R/W

- - -

1 1 1 1 1

0406

ICR06

Interrupt control register 6

R/W

- - -

1 1 1 1 1

0407

ICR07

Interrupt control register 7

R/W

- - -

1 1 1 1 1

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

0408

ICR08

Interrupt control register 8

R/W

- - -

1 1 1 1 1

0409

ICR09

Interrupt control register 9

R/W

- - -

1 1 1 1 1

040A

ICR10

Interrupt control register 10

R/W

- - -

1 1 1 1 1

040B

ICR11

Interrupt control register 11

R/W

- - -

1 1 1 1 1

040C

ICR12

Interrupt control register 12

R/W

- - -

1 1 1 1 1

040D

ICR13

Interrupt control register 13

R/W

- - -

1 1 1 1 1

040E

ICR14

Interrupt control register 14

R/W

- - -

1 1 1 1 1

040F

ICR15

Interrupt control register 15

R/W

- - -

1 1 1 1 1

0410

ICR16

Interrupt control register 16

R/W

- - -

1 1 1 1 1

0411

ICR17

Interrupt control register 17

R/W

- - -

1 1 1 1 1

0412

ICR18

Interrupt control register 18

R/W

- - -

1 1 1 1 1

0413

ICR19

Interrupt control register 19

R/W

- - -

1 1 1 1 1

0414

ICR20

Interrupt control register 20

R/W

- - -

1 1 1 1 1

0415

ICR21

Interrupt control register 21

R/W

- - -

1 1 1 1 1

0416

ICR22

Interrupt control register 22

R/W

- - -

1 1 1 1 1

0417

ICR23

Interrupt control register 23

R/W

- - -

1 1 1 1 1

0418

ICR24

Interrupt control register 24

R/W

- - -

1 1 1 1 1

0419

ICR25

Interrupt control register 25

R/W

- - -

1 1 1 1 1

041A

ICR26

Interrupt control register 26

R/W

- - -

1 1 1 1 1

041B

ICR27

Interrupt control register 27

R/W

- - -

1 1 1 1 1

041C

ICR28

Interrupt control register 28

R/W

- - -

1 1 1 1 1

041D

ICR29

Interrupt control register 29

R/W

- - -

1 1 1 1 1

041E

ICR30

Interrupt control register 30

R/W

- - -

1 1 1 1 1

041F

ICR31

Interrupt control register 31

R/W

- - -

1 1 1 1 1

0420

042E

ICR32 to ICR46

Interrupt control register 32 to 46

R/W

- - -

1 1 1 1 1

042F

ICR47

Interrupt control register 47

R/W

- - -

1 1 1 1 1

0430

DICR

Delayed interrupt control register

R/W

- - - - - - -

0431

HRCL

Hold request cancel request level setting register

R/W

- - -

1 1 1 1 1

0432

047F

(Vacancy)

0480

RSRR/WTCR

Reset cause register/
watchdog peripheral control register

R/W

1 XXXX

0 0

0481

STCR

Standby control register

R/W

0 0 0 1 1 1

- -

0482

PDRR

DMA controller request squelch register

R/W

- - - -

0 0 0 0

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

0483

CTBR

Timebase timer clear register

XXXXXXXX

0484

GCR

Gear control register

R/W

1 1 0 0 1 1

0485

WPR

Watchdog reset occurrence postpone register

XXXXXXXX

0486

(Vacancy)

0487

0488

PCTR

PLL control register

R/W

0 0

- -

- - -

0489

0600

(Vacancy)

0601

DDR2

Port 2 data direction register

0 0 0 0 0 0 0 0

0602

0604

(Vacancy)

0605

DDR6

Port 6 data direction register

0 0 0 0 0 0 0 0

0606

(Vacancy)

0607

0608

DDRB

Port B data direction register

0 0 0 0 0 0 0 0

0609

DDRA

Port A data direction register

0 0 0 0 0 0

060A

(Vacancy)

060B

DDR8

Port 8 data direction register

- -

0 0 0

060C

ASR1

Area select register 1

0 0 0 0 0 0 0 0

060D

0 0 0 0 0 0 0 1

060E

AMR1

Area mask register 1

0 0 0 0 0 0 0 0

060F

0 0 0 0 0 0 0 0

0610

ASR2

Area select register 2

0 0 0 0 0 0 0 0

0611

0 0 0 0 0 0 1 0

0612

AMR2

Area mask register 2

0 0 0 0 0 0 0 0

0613

0 0 0 0 0 0 0 0

0614

ASR3

Area select register 3

0 0 0 0 0 0 0 0

0615

0 0 0 0 0 0 1 1

0616

AMR3

Area mask register 3

0 0 0 0 0 0 0 0

0617

0 0 0 0 0 0 0 0

0618

ASR4

Area select register 4

0 0 0 0 0 0 0 0

0619

0 0 0 0 0 1 0 0

061A

AMR4

Area mask register 4

0 0 0 0 0 0 0 0

061B

0 0 0 0 0 0 0 0

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

MB91121

(Continued)

Address

Register name

(abbreviated)

Register name

Read/write

Initial value

061C

ASR5

Area select register 5

0 0 0 0 0 0 0 0

061D

0 0 0 0 0 1 0 1

061E

AMR5

Area mask register 5

0 0 0 0 0 0 0 0

061F

0 0 0 0 0 0 0 0

0620

AMD0

Area mode register 0

R/W

- - -

0 0 1 1 1

0621

AMD1

Area mode register 1

R/W

- -

0 0 0 0 0

0622

AMD32

Area mode register 32

R/W

0 0 0 0 0 0 0 0

0623

AMD4

Area mode register 4

R/W

- -

0 0 0 0 0

0624

AMD5

Area mode register 5

R/W

- -

0 0 0 0 0

0625

DSCR

DRAM signal control register

0 0 0 0 0 0 0 0

0626

RFCR

Refresh control register

R/W

- -

XXXXXX

0627

0 0

- - -

0 0 0

0628

EPCR0

External pin control register 0

- - - -

1 1 0 0

0629

1 1 1 1 1 1 1

062A

(Vacancy)

062B

EPCR1

External pin control register 1

1 1 1 1 1 1 1 1

062C

DMCR4

DRAM control register 4

R/W

0 0 0 0 0 0 0 0

062D

0 0 0 0 0 0 0

062E

DMCR5

DRAM control register 5

R/W

0 0 0 0 0 0 0 0

062F

0 0 0 0 0 0 0

0630

07FD

(Vacancy)

07FE

LER

Little endian register

- - - - -

0 0 0

07FF

MODR

Mode register

XXXXXXXX

002000

002FFF

Y-RAM
(Variable RAM)
4096 byte (Max.)

DSP macro RAM

00F000

00F07F

X-RAM
(Coefficient RAM)
128 byte

00F100

00F2FF

I-RAM
(Instruction RAM)
512 byte

Note : Do not use (vacancy) .

MB91121

INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

Reset

3F4

000FFFFC

Reserved for system

3F8

000FFFF8

Reserved for system

3F4

000FFFF4

Reserved for system

3F0

000FFFF0

Reserved for system

3EC

000FFFEC

Reserved for system

3E8

000FFFE8

Reserved for system

3E4

000FFFE4

Reserved for system

3E0

000FFFE0

Reserved for system

3DC

000FFFDC

Reserved for system

3D8

000FFFD8

Reserved for system

3D4

000FFFD4

Reserved for system

3D0

000FFFD0

Reserved for system

3CC

000FFFCC

Reserved for system

3C8

000FFFC8

Exception for undefined instruction

3C4

000FFFC4

NMI request

fixed

3C0

000FFFC0

External interrupt 0

ICR00

3BC

000FFFBC

External interrupt 1

ICR01

3B8

000FFFB8

External interrupt 2

ICR02

3B4

000FFFB4

External interrupt 3

ICR03

3B0

000FFFB0

UART0 receive complete

ICR04

3AC

000FFFAC

UART1 receive complete

ICR05

3A8

000FFFA8

UART2 receive complete

ICR06

3A4

000FFFA4

UART0 transmit complete

ICR07

3A0

000FFFA0

UART1 transmit complete

ICR08

39C

000FFF9C

UART2 transmit complete

ICR09

398

000FFF98

DMAC0 (complete, error)

ICR10

394

000FFF94

DMAC1 (complete, error)

ICR11

390

000FFF90

DMAC2 (complete, error)

ICR12

38C

000FFF8C

DMAC3 (complete, error)

ICR13

388

000FFF88

DMAC4 (complete, error)

ICR14

384

000FFF84

DMAC5 (complete, error)

ICR15

380

000FFF80

DMAC6 (complete, error)

ICR16

37C

000FFF7C

(Continued)

MB91121

DMAC7 (complete, error)

ICR17

378

000FFF78

A/D converter (successive approxima-
tion conversion type)

ICR18

374

000FFF74

16-bit reload timer 0

ICR19

370

000FFF70

16-bit reload timer 1

ICR20

36C

000FFF6C

16-bit reload timer 2

ICR21

368

000FFF68

PWM 0

ICR22

364

000FFF64

PWM 1

ICR23

360

000FFF60

PWM 2

ICR24

35C

000FFF5C

PWM 3

ICR25

358

000FFF58

U-TIMER 0

ICR26

354

000FFF54

U-TIMER 1

ICR27

350

000FFF50

U-TIMER 2

ICR28

34C

000FFF4C

External interrupt 4

ICR29

348

000FFF48

External interrupt 5

ICR30

344

000FFF44

External interrupt 6

ICR31

340

000FFF40

External interrupt 7

ICR32

33C

000FFF3C

DSP Macros soft interrupt

ICR33

338

000FFF38

DSP Macros offset interrupt

ICR34

334

000FFF34

Reserved for system

ICR35

330

000FFF30

Reserved for system

ICR36

32C

000FFF2C

Reserved for system

ICR37

328

000FFF28

Reserved for system

ICR38

324

000FFF24

Reserved for system

ICR39

320

000FFF20

Reserved for system

ICR40

31C

000FFF1C

Reserved for system

ICR41

318

000FFF18

Reserved for system

ICR42

314

000FFF14

Reserved for system

ICR43

310

000FFF10

Reserved for system

ICR44

30C

000FFF0C

Reserved for system

ICR45

308

000FFF08

Reserved for system

ICR46

304

000FFF04

Delayed interrupt cause bit

ICR47

300

000FFF00

Reserved for system
(used in REALOS*)

2FC

000FFEFC

Reserved for system
(used in REALOS*)

2F8

000FFEF8

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal

Hexadecimal

Register

Offset

MB91121

PERIPHERAL RESOURCES

I/O Ports

There are 2 types of I/O port register structure; port data register (PDR2, 6, 8, A, B, E to I) and data direction
register (DDR2, 6, 8, A, B, E to I) , where bits PDR2, 6, 8, A, B, E to I and bits DDR2, 6, 8, A, B, E to I corresponds
respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of
the port configures input/output function of the port, while corresponding bit (pin) configures input/output function
in data direction registers. Bit "0" specifies input and "1" specifies output.

· For input (DDR

"0") setting;

PDR reading operation : reads level of corresponding external pin.
PDR writing operation : writes set value to PDR.

· For output (DDR

"1") setting;

PDR reading operation : reads PDR value.
PDR writing operation : outputs PDR value to corresponding external pin.

· Block diagram

PDR

DDR

(Port data register)

(Data direction register)

Resource output enable

Resource output

PDR read

Resource input

Data bus

MB91121

· Register explanation

· Port Data Register (PDR)

P27

P26

P25

P24

P23

P22

P21

P20

P67

P66

P65

P64

P63

P62

P61

P60

P85

P82

P81

P80

PA6

PA5

PA4

PA3

PA2

PA1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

PH7

PH6

PH5

PH4

PI1

PI0

PDR2
Address : 000001

PDR6
Address : 000005

PDR8
Address : 00000B

PDRA
Address : 000009

PDRB
Address : 000008

PDRE
Address : 000012

PDRF
Address : 000013

PDRG
Address : 000014

PDRH
Address : 000015

PDRI
Address : 000016

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

- -

X X X

R/W

Initial value

Access

X X X X X X

R/W

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

X X X X X X X X

R/W

Initial value

Access

X X X X

- - - -

R/W

Initial value

Access

- - - - - -

X X

R/W

PDR2 to PDRI is the I/O port input/output data register.
The associated register, DDR2 to DDRI, controls the input/output.

MB91121

· Data Direction Register (DDR)

P27

P26

P25

P24

P23

P22

P21

P20

P67

P66

P65

P64

P63

P62

P61

P60

P85

P82

P81

P80

PA6

PA5

PA4

PA3

PA2

PA1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PG7

PG6

PG5

PG4

PG3

PG2

PG1

PG0

PH7

PH6

PH5

PH4

PI1

PI0

DDR2
Address : 000601

DDR6
Address : 000605

DDR8
Address : 00060B

DDRA
Address : 000609

DDRB
Address : 000608

DDRE
Address : 0000D2

DDRF
Address : 0000D3

DDRG
Address : 0000D4

DDRH
Address : 0000D5

DDRI
Address : 0000D6

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

- -

0 0 0

Initial value

Access

0 0 0 0 0 0

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

0 0 0 0 0 0 0 0

Initial value

Access

0 0 0 0

- - - -

Initial value

Access

- - - - - -

0 0

DDR2 to DDRI controls the I/O port input/output direction bit by bit.

0 : Input
1 : Output

MB91121

DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to
enhanced performance of the system.

· 8 channels
· Mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer
· Transfer all through the area
· Max. 65536 of transfer cycles
· Interrupt function right after the transfer
· Selectable for address transfer increase/decrease by the software
· External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

· Block diagram

DREQ0 to DREQ2

DACK0 to DACK2

EOP0 to EOP2

Interrupt request

DPDP

DACSR

DATCR

BLK DEC

INC / DEC

BLK

DMACT

SADR

DADR

Sequencer

Edge/level

detection circuit

Inner resource
transfer request

Data buffer

Switcher

Data bus

Mode

MB91121

Address

Initial value

bit 31

bit 16

bit 0

00000200

X X X X X X X X

00000201

DPDP

X X X X X X X X

(R/W)

00000202

X X X X X X X X

00000203

X 0 0 0 0 0 0 0

00000204

0 0 0 0 0 0 0 0

00000205

DACSR

0 0 0 0 0 0 0 0

(R/W)

00000206

0 0 0 0 0 0 0 0

00000207

0 0 0 0 0 0 0 0

00000208

X X X X X X X X

00000209

DATCR

X X X X 0 0 0 0

(R/W)

0000020A

X X X X 0 0 0 0

0000020B

X X X X 0 0 0 0

· Registers (DMAC internal registers)

(

) : Access

R/W : Readable and writable

X : Indeterminate

· Registers (DMA descriptor)

Address

bit 31

bit 0

DPDP

DMA
ch.0
Descriptor

DPDP

DMA
ch.1
Descriptor

DPDP

DMA
ch.7
Descriptor

MB91121

UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK
synchronous communication, and it has the following features.

The MB91121 consists of 3 channels of UART.

· Full double double buffer
· Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
· Supporting multi-processor mode
· Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section "4. U-TIMER") .

· Any baud rate can be set by external clock.
· Error checking function (parity, framing and overrun)
· Transfer signal : NRZ code
· Enable DMA transfer start by interrupt.

MB91121

· Block diagram

SIDR

SODR

MD1
MD0

CS0

SCKE
SOE

PEN
P
SBL
CL
A/D
REC
RXE
TXE

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

Control signals

From external clock

SI
(receive data)

Clock select

circuit

Receive interrupt
(to CPU)

Transmit interrupt
(to CPU)

Receive control circuit

Start bit detect

circuit

Receive bit counter

Receive parity

counter

Transmit control circuit

Transmit start

circuit

Transmit bit counter

Transmit parity

counter

Transmit clock

Receive clock

SC (clock)

From U-TIMER

Receive status

judge circuit

Receive shifter

Receive
complete

Transmit shifter

Transmit
start

Receive error
generate signal
for DMA
(to DMAC)

R-bus

SMR
register

SCR
register

SSR
register

Control signals

SO (transmit data)

MB91121

· Register configuration

Address

Initial value

bit 15

bit 8

bit 0

0000001E

SCR0

0 0 0 0 0 1 0 0

(R/W)

00000022

SCR1

0 0 0 0 0 1 0 0

(R/W)

00000026

SCR2

0 0 0 0 0 1 0 0

(R/W)

0000001F

SMR0

0 0

- -

0 0

(R/W)

00000023

SMR1

0 0

- -

0 0

(R/W)

00000027

SMR2

0 0

- -

0 0

(R/W)

0000001C

SSR0

0 0 0 0 1

0 0

(R/W)

00000020

SSR1

0 0 0 0 1

0 0

(R/W)

00000024

SSR2

0 0 0 0 1

0 0

(R/W)

0000001D

SIDR0/SODR0

X X X X X X X X

(R/W)

00000021

SIDR1/SIDR1

X X X X X X X X

(R/W)

00000002

SIDR2/SIDR2

X X X X X X X X

(R/W)

(

) : Access

R/W : Readable and writable

: Unused

X : Indeterminate

MB91121

U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91121 has 3 channel U-TIMER embedded on the chip. An interval of up to 2

can be counted.

· Block diagram

· Register configuration

bit 15

bit 0

bit 15

bit 0

f.f.

UTIMR (reload register)

UTIM ( U-TIMER register)

Clock

Underflow

To UART

(Peripheral clock)

Control

Load

Address

Initial value

bit 15

bit 0

00000078

UTIM0/UTIMR0

0 0 0 0 0 0 0 0

(R/W)

00000079

0 0 0 0 0 0 0 0

0000007C

UTIM1/UTIMR1

0 0 0 0 0 0 0 0

(R/W)

0000007D

0 0 0 0 0 0 0 0

00000080

UTIM2/UTIMR2

0 0 0 0 0 0 0 0

(R/W)

00000081

0 0 0 0 0 0 0 0

0000007B

UTIMC0

- -

0 0 0 0 1

(R/W)

0000007F

UTIMC1

- -

0 0 0 0 1

(R/W)

00000083

UTIMC2

- -

0 0 0 0 1

(R/W)

(

) : Access

R/W : Readable and writable

: Unused

MB91121

PWM Timer

The PWM timer can output high accurate PWM waves efficiently.

MB91121 has inner 4-channel PWM timers, and has the following features.

· Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit

compare resister with a buffer for duty setting, and a pin controller.

· The count clock of a 16-bit down counter can be selected from the following four inner clocks.

Inner clock

/4,

/16,

/64

· The counter value can be initialized "FFFF

" by the resetting or the counter borrow.

· PWM output (each channel)
· Resister description

· Block diagram (general construction)

PWM0

PWM1

PWM2

PWM3

16-bit reload timer

ch.0

16-bit reload timer

ch.1

General control

TRG input

PWM timer ch.0

TRG input

PWM timer ch.1

TRG input

PWM timer ch.2

TRG input

PWM timer ch.3

General control

(cause selection)

External TRG0 to TRG3

MB91121

· Register configuration

Address

Initial value

bit 15

bit 8

bit 0

000000DC

GCN1

0 0 1 1 0 0 1 0

(R/W)

000000DD

0 0 0 1 0 0 1 0

000000DF

GCN2

0 0 0 0 0 0 0 0

(R/W)

000000E0

PTMR0

1 1 1 1 1 1 1 1

(R)

000000E1

1 1 1 1 1 1 1 1

000000E2

PCSR0

X X X X X X X X

(W)

000000E3

X X X X X X X X

000000E4

PDUT0

X X X X X X X X

(W)

000000E5

X X X X X X X X

000000E6

PCNH0

0 0 0 0 0 0 0

(R/W)

000000E7

PCNL0

0 0 0 0 0 0 0 0

(R/W)

000000E8

PTMR1

1 1 1 1 1 1 1 1

(R)

000000E9

1 1 1 1 1 1 1 1

000000EA

PCSR1

X X X X X X X X

(W)

000000EB

X X X X X X X X

000000EC

PDUT1

X X X X X X X X

(W)

000000ED

X X X X X X X X

000000EE

PCNH1

0 0 0 0 0 0 0

(R/W)

000000EF

PCNL1

0 0 0 0 0 0 0 0

(R/W)

000000F0

PTMR2

1 1 1 1 1 1 1 1

(R)

000000F1

1 1 1 1 1 1 1 1

000000F2

PCSR2

X X X X X X X X

(W)

000000F3

X X X X X X X X

000000F4

PDUT2

X X X X X X X X

(W)

000000F5

X X X X X X X X

000000F6

PCNH2

0 0 0 0 0 0 0

(R/W)

000000F7

PCNL2

0 0 0 0 0 0 0 0

(R/W)

000000F8

PTMR3

1 1 1 1 1 1 1 1

(R)

000000F9

1 1 1 1 1 1 1 1

000000FA

PCSR3

X X X X X X X X

(W)

000000FB

X X X X X X X X

000000FC

PDUT3

X X X X X X X X

(W)

000000FD

X X X X X X X X

000000FE

PCNH3

0 0 0 0 0 0 0

(R/W)

000000FF

PCNL3

0 0 0 0 0 0 0 0

(R/W)

(

) : Access

R/W : Readable and writable

R : Read only

W : Write only

: Unused

X : Indeterminate

MB91121

16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal
count clock and control registers.

Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) .

The DMA transfer can be started by the interruption.

The MB91121 consists of 3 channels of the 16-bit reload timer.

· Block diagram

RELD

OUTE

OUTL

INTE

CNTE

TRG

OUT
CTL.

CSL1

CSL0

MOD2

MOD1

MOD0

IN CTL.

EXCK

GATE

IRQ

PWM (ch0, ch1)
A/D (ch2)

16-bit reload register

16-bit down counter UF

Clock selector

Reload

Internal clock

Prescaler
clear

Retrigger

R-bus

MB91121

· Register configuration

Address

Initial value

bit 15

bit 0

0000002E

TMCSR0

- - - -

0 0 0 0

(R/W)

0000002F

0 0 0 0 0 0 0 0

00000036

TMCSR1

- - - -

0 0 0 0

(R/W)

00000037

0 0 0 0 0 0 0 0

00000042

TMCSR2

- - - -

0 0 0 0

(R/W)

00000043

0 0 0 0 0 0 0 0

0000002A

TMR0

X X X X X X X X

(R)

0000002B

X X X X X X X X

00000032

TMR1

X X X X X X X X

(R)

00000033

X X X X X X X X

0000003E

TMR2

X X X X X X X X

(R)

0000003F

X X X X X X X X

00000028

TMRLR0

X X X X X X X X

(W)

00000029

X X X X X X X X

00000030

TMRLR1

X X X X X X X X

(W)

00000031

X X X X X X X X

0000003C

TMRLR2

X X X X X X X X

(W)

0000003D

X X X X X X X X

(

) : Access

R/W : Readable and writable

R : Read only

W : Write only

: Unused

X : Indeterminate

MB91121

Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.

· Block diagram

· Register configuration

Input latch

Single-detection data recovery

Bit search circuit

Search result

Address
decoder

Detection

mode

D-bus

Address

Initial value

bit 31

bit 16

bit 0

000003F0

X X X X X X X X

000003F1

BSD0

X X X X X X X X

(W)

000003F2

X X X X X X X X

000003F3

X X X X X X X X

000003F4

X X X X X X X X

000003F5

BSD1

X X X X X X X X

(W)

000003F6

X X X X X X X X

000003F7

X X X X X X X X

000003F8

X X X X X X X X

000003F9

BSDC

X X X X X X X X

(W)

000003FA

X X X X X X X X

000003FB

X X X X X X X X

000003FC

X X X X X X X X

000003FE

BSRR

X X X X X X X X

(W)

000003FD

X X X X X X X X

000003FF

X X X X X X X X

(

) : Access

R/W : Readable and writable

R : Read only

W : Write only

X : Indeterminate

MB91121

10-bit A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.

· Minimum converting time : 5.6

s/ch. (system clock : 25 MHz)

· Inner sample and hold circuit
· Resolution : 10 bits
· Analog input can be selected from 4 channels by program.

Single convert mode : 1 channel is selected and converted.
Scan convert mode : Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode : Converting the specified channel repeatedly.
Stop convert mode : After converting one channel then stop and wait till next activation synchronising at

the beginning of conversion can be peformed.

· DMA transfer operation is available by interruption.
· Operating factor can be selected from the software, the external trigger (falling edge) , and 16-bit reroad timer

(rising edge) .

MB91121

· Block diagram

· Register configuration

AVR

MPX

AN0

AN1

AN2

AN3

ATG

Successive approximation

Internal voltage generator

Comparator

Sample & hold circuit

Data register (ADCR)

A/D control register (ADCS)

Prescaler

Operating clock

Trigger start

TIM0
(internal connection)
(16-bit reload timer ch.2)

Timer start

(Peripheral clock)

R-bus

Input circuit

Decoder

Address

Initial value

bit 15

bit 0

0000003A

ADCS

0 0 0 0 0 0 0 0

(R/W)

0000003B

0 0 0 0 0 0 0 0

00000038

ADCR

- - - - - -

X X

(R)

00000039

X X X X X X X X

(

) : Access

R/W : Readable and writable

: Read only

: Unused

: Indeterminate

MB91121

Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

· Block diagram

LEVEL0

INT0

NMI

·
·
·

RI00

RI47

(DLYIRQ)

·
·
·

DLYI

·
·

ICR00

ICR47

LEVEL4 to

HLDCAN

VCT0

VCT5 to

R-bus

Priority judgment

NMI processing

Level judgment

Vector judgment

Level

vector

generation

HLDREQ

cancel

request

*1 : DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section

"11. Delayed Interrupt Module" for detail) .

*2 : INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3 : HLDCAN is a bus release request signal for bus masters other than CPU.

*4 : LEVEL5 to LEVEL0 are interrupt level outputs.

*5 : VCT5 to VCT0 are interrupt vector outputs.

MB91121

· Register configuration

Address

Initial value

Address

Initial value

bit 7

bit 0

bit 7

bit 0

00000400

ICR00

- - -

1 1 1 1 1

(R/W)

00000411

ICR17

- - -

1 1 1 1 1

(R/W)

00000401

ICR01

- - -

1 1 1 1 1

(R/W)

00000412

ICR18

- - -

1 1 1 1 1

(R/W)

00000402

ICR02

- - -

1 1 1 1 1

(R/W)

00000413

ICR19

- - -

1 1 1 1 1

(R/W)

00000403

ICR03

- - -

1 1 1 1 1

(R/W)

00000414

ICR20

- - -

1 1 1 1 1

(R/W)

00000404

ICR04

- - -

1 1 1 1 1

(R/W)

00000415

ICR21

- - -

1 1 1 1 1

(R/W)

00000405

ICR05

- - -

1 1 1 1 1

(R/W)

00000416

ICR22

- - -

1 1 1 1 1

(R/W)

00000406

ICR06

- - -

1 1 1 1 1

(R/W)

00000417

ICR23

- - -

1 1 1 1 1

(R/W)

00000407

ICR07

- - -

1 1 1 1 1

(R/W)

00000418

ICR24

- - -

1 1 1 1 1

(R/W)

00000408

ICR08

- - -

1 1 1 1 1

(R/W)

00000419

ICR25

- - -

1 1 1 1 1

(R/W)

00000409

ICR09

- - -

1 1 1 1 1

(R/W)

0000041A

ICR26

- - -

1 1 1 1 1

(R/W)

0000040A

ICR10

- - -

1 1 1 1 1

(R/W)

0000041B

ICR27

- - -

1 1 1 1 1

(R/W)

0000040B

ICR11

- - -

1 1 1 1 1

(R/W)

0000041C

ICR28

- - -

1 1 1 1 1

(R/W)

0000040C

ICR12

- - -

1 1 1 1 1

(R/W)

0000041D

ICR29

- - -

1 1 1 1 1

(R/W)

0000040D

ICR13

- - -

1 1 1 1 1

(R/W)

0000041E

ICR30

- - -

1 1 1 1 1

(R/W)

0000040E

ICR14

- - -

1 1 1 1 1

(R/W)

0000041F

ICR31

- - -

1 1 1 1 1

(R/W)

0000040F

ICR15

- - -

1 1 1 1 1

(R/W)

0000042F

ICR47

- - -

1 1 1 1 1

(R/W)

00000410

ICR16

- - -

1 1 1 1 1

(R/W)

00000431

HRCL

- - -

1 1 1 1 1

(R/W)

00000430

DICR

- - - - - - -

(R/W)

(

) : Access

R/W : Readable and writable

: Unused

MB91121

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0 to
INT3 pins.

Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI pin) .

· Block diagram

· Register configuration

INT0 to INT7
NMI

Interrupt enable register

Interrupt cause register

Request level setting register

Gate

Cause F/F

Edge detection circuit

Interrupt

request

R-bus

Address

Initial value

bit 15

bit 8

bit 0

00000095

ENIR

0 0 0 0 0 0 0 0

(R/W)

00000094

EIRR

0 0 0 0 0 0 0 0

(R/W)

00000099

ELVR

0 0 0 0 0 0 0 0

(R/W)

(

) : Access

R/W : Readable and writable

MB91121

· Block diagram

X0
X1

PLL

1 / 2

Gear control register (GCR)

[Gear control block]

PCTR register

CPU gear

Peripheral

gear

Oscillator

circuit

Internal clock

generation

circuit

CPU clock
Internal bus clock

External bus clock

Peripheral DMA clock

Internal
peripheral clock

[Stop/sleep control block]

Internal
interrupt request
Internal reset

Standby control
register (STCR)

STOP state

SLEEP state

CPU hold request

Internal reset

Reset

generation

F/F

CPU hold enable

HST pin

R-bus

Selection

circuit

Status

transition

control circuit

DMA
request

Power on sel

RST pin

DMA request prohibit

[DMA prohibit circuit]

Reset cause register (RSRR)

Timebase timer

Count clock

Watchdog reset

postpone register

[Watchdog control block]

Timebase timer clear

Watchdog reset generation

postpone register (WPR)

[Reset cause circuit]

DSP Macros clock

MB91121

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.

· 25-bit (32 Mbytes) address output
· 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes

6 area setting is available by the address pin and the chip select pin.

· 8/16-bit bus width setting are available for every chip select area.
· Programmable automatic memory wait (max. for 7 cycles) can be inserted.
· DRAM interface support

Three kinds of DRAM interface : Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM
Hyper DRAM

2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable wave form

· Unused address/data pin can be used for I/O port.
· Little endian mode supported
· Clock doublure : Internal bus 50 MHz, external bus 25 MHz

MB91121

· Register configuration

Address

Initial value

bit 31

bit 16

bit 0

0000060C

ASR1

0 0 0 0 0 0 0 0

(W)

0000060D

0 0 0 0 0 0 0 1

0000060E

AMR1

0 0 0 0 0 0 0 0

(W)

0000060F

0 0 0 0 0 0 0 0

00000610

ASR2

0 0 0 0 0 0 0 0

(W)

00000611

0 0 0 0 0 0 1 0

00000612

AMR2

0 0 0 0 0 0 0 0

(W)

00000613

0 0 0 0 0 0 0 0

00000614

ASR3

0 0 0 0 0 0 0 0

(W)

00000615

0 0 0 0 0 0 1 1

00000616

AMR3

0 0 0 0 0 0 0 0

(W)

00000617

0 0 0 0 0 0 0 0

00000618

ASR4

0 0 0 0 0 0 0 0

(W)

00000619

0 0 0 0 0 1 0 0

0000061A

AMR4

0 0 0 0 0 0 0 0

(W)

0000061B

0 0 0 0 0 0 0 0

0000061C

ASR5

0 0 0 0 0 0 0 0

(W)

0000061D

0 0 0 0 0 1 0 1

0000061E

AMR5

0 0 0 0 0 0 0 0

(W)

0000061F

0 0 0 0 0 0 0 0

00000620

AMD0

- - -

0 0 1 1 1

(R/W)

00000621

AMD1

- -

0 0 0 0 0

(R/W)

00000622

AMD32

0 0 0 0 0 0 0 0

(R/W)

00000623

AMD4

- -

0 0 0 0 0

(R/W)

00000624

AMD5

- -

0 0 0 0 0

(R/W)

00000625

DSCR

0 0 0 0 0 0 0 0

(W)

00000626

RFCR

- -

X X X X X X

(R/W)

00000627

0 0

- - -

0 0 0

00000628

EPCR0

- - -

1 1 0 0 0

(W)

00000629

1 1 1 1 1 1 1

0000062B

EPCR1

1 1 1 1 1 1 1 1

(W)

0000062C

DMCR4

0 0 0 0 0 0 0 0

(R/W)

0000062D

0 0 0 0 0 0 0

0000062E

DMCR5

0 0 0 0 0 0 0 0

(R/W)

0000062F

0 0 0 0 0 0 0

000007FE

LER

- - - - -

0 0 0

(W)

000007FF

MODR

X X X X X X X X

(W)

(

) : Access

R/W : Readable and writable

: Write only

: Unused

: Indeterminate

MB91121

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

*1 : Make sure that the voltage does not exceed V

0.3 V, such as when turning on the device.

*2 : Maximum output current is a peak current value measured at a corresponding pin.

*3 : Average output current is an average current for a 100 ms period at a corresponding pin.

*4 : Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

0.0 V)

Parameter Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

0.3

3.6

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

0.3

3.6

Input voltage

0.3

Analog pin input voltage

0.3

Output voltage

0.3

"L" level maximum output current

"L" level average output current

OLAV

"L" level maximum total output current

100

"L" level average total output current

OLAV

"H" level maximum output current

"H" level average output current

OHAV

"H" level maximum total output current

"H" level average total output current

OHAV

Power consumption

600

Operating temperature

Storage temperature

Tstg

150

MB91121

Recommended Operating Conditions

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

0.0 V)

Parameter Symbol

Value

Unit

Remarks

Min.

Max.

Power supply voltage

3.0

3.6

Analog supply voltage

0.3

3.6

Analog reference voltage

AVRH

Operating temperature

MB91121

DC Characteristics

*1 : Hysteresis input pin : NMI, RST, P60 to P67, PA1 to PA6, PB0 to PB7, PE0 to PE7, PF0 to PF7, PG0 to PG7,

PI0, PI1

*2 : V

3 = 3.3

0.2 V (internal regulator output voltage) when using 5 V power supply, V

3 = power supply voltage

when using 3V power supply (internal regulator unused)

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Typ.

Max.

"H" level
input voltage

Input pin
except for
hysteresis
input

0.65

0.3

IHS

0.8

0.3

Hysteresis
input*2

"L" level
input voltage

Input pin
except for
hysteresis
input

0.3

0.25

ILS

0.3

0.2

Hysteresis
input*2

"H" level
output voltage

D16 to D31
A00 to A24
P6 to PF

3.0 V

4.0 mA

0.5

"L" level
output voltage

D16 to D31
A00 to A24
P6 to PF

3.0 V

4.0 mA

0.4

Input leakage
current
(Hi-Z output
leakage current)

D00 to D31
A00 to A23
P8 to PF

3.6 V

0.45 V< V

< V

Pull-up
resistance

PULL

RST

3.6 V

0.45 V

100

Power supply
current

12.5 MHz

3.3 V

130

180

(4 multipli-
cation)
Operation at
50 MHz

CCS

12.5 MHz

3.3 V

120

mA Sleep mode

CCH

3.3 V

150

Stop mode

Input
capacitance

Except for
V

, AV

, V

MB91121

(2) Clock Timing Rating

*1 : Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock

multiplication system.

*2 : These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and

a 1/8 gear.

*3 : Values when using the doublure and CPU operation at 50 MHz.

3.0 V to 3.6 V, V

0 .0V, T

C to

Parameter

Symbol Pin name Condition

Value

Unit

Remarks

Min.

Max.

Clock frequency (1)

X0, X1

12.5

MHz

When using PLL

Clock cycle time

X0, X1

100

Frequency shift ratio*

(when locked)

Clock frequency (2)

X0, X1

MHz

Self-oscillation
(divide-by-2 input)

Clock frequency (3)

X0, X1

MHz

External clock
(divide-by-2 input)

Clock cycle time

X0, X1

100

Input clock pulse width

, P

X0, X1

Input to X0 only

Input to X0, X1

Input clock rising/falling time

, t

X0, X1

)

Internal operating clock
frequency

0.625*

MHz

CPU system

CPB

0.625*

25*

MHz

Bus system

CPP

0.625*

MHz

Peripheral system

Internal operating clock
cycle time

1600*

CPU system

CPB

40*

1600*

Bus system

CPP

1600*

Peripheral system

100 (%)

Center frequency

MB91121

· Clock timing rating measurement conditions

· Guaranteed operating range

· External/internal clock setting range

0.8 V

0.2 V

3.3 V

0.3 V

Guaranteed operating range (T

C to

CPP

falls within the shaded range.

Internal clock

Power supply

(V)

3.6

3.0

0.625

/ f

CPP

[MHz]

CPU

External clock

Internal oscillation

Oscillation input clock

PLL system
(4 multiplication)

Divide-by-2 system

Peripheral

Internal clock setting upper limit

CPP

12.5

10 12.5

[MHz]

Note1 : If the PLL is used, the external clock input should be 10.0 MHz to 12.5 MHz.

Note2 : The PLL oscillation settling time must be longer than 300

Note3 : The internal clock gear setting must fall within the above range.

MB91121

(3) Clock Output Timing

*1 : t

CYC

is a frequency for 1 clock cycle including a gear cycle.

Use the doublure when CPU frequency is above 25 MHz.

*2 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : (1

CYC

Max. : (1

CYC

Select a gear cycle of

1 when using the doublure.

*3 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equations with 1/2, 1/4, 1/8,
respectively.

Min. : n

CYC

Max. : n

CYC

Select a gear cycle of

1 when using the doublure.

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Cycle time

CYC

CLK

CPB

Using the
doublure

CLK

CHCL

CLK

CYC

CLK

CLCH

CLK

CYC

CLK

CYC

CLCH

CHCL

MB91121

The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows:

However, in this chart source oscillation input means X0 input clock.

CYC

CCK1/0: "00"

Source oscillation input
(when using the doublure)

Source oscillation input

(1) PLL system
(CHC bit of GCR set to "0")

(2) 2 dividing system
(CHC bit of GCR set to "1")

(a) Gear

1 CLK pin

CCK1/0: "00"

(b) Gear

1/2 CLK pin

CCK1/0: "01"

1/4 CLK pin

CCK1/0: "10"

(d) Gear

1/8 CLK pin

CCK1/0: "11"

(a) Gear

1 CLK pin

MB91121

· Ceramc oscillator applications

· Discrete type

*1 : Feedback resistor Rf is built in the LSI.

*2 : No dumping resistor is required.
( ) : C

and C

integrated

Oscillation frequency

[MHz]

Model name

Circuit constants

Pin type

C1[pF]

Rf[

Rd[

10.00 to 13.00

CSA

MTZ

Two-pin

CST

MTW

(30)

Three-pin

13.01 to 15.99

CSA

MXZ040

Two-pin

CST

MXW0C3

(15)

Three-pin

16.00 to 19.99

CSA

MXZ040

(10)

Two-pin

Three-pin

20.00 to 25.00

CSA

MXZ004

None

Two-pin

Three-pin

Recommended circuit (2 contacts)

Recommended circuit (3 contacts)

, C

internally

connected.

* : Murata Mfg. Co., Ltd.

MB91121

· SMD type

*1 : Feedback resistor Rf is built in the LSI.

*2 : No dumping resistor is required.
( ) : C

and C

integrated

Oscillation frequency

[MHz]

Model name

Circuit constants

Pin type

C1[pF]

Rf[

Rd[

10.00 to 13.00

CSACS

Two-pin

CSTCS

(30)

Three-pin

13.01 to 15.99

CSACS

MX040

Two-pin

CSTCS

MX0C3

(15)

Three-pin

16.00 to 19.99

CSACS

MX040

Two-pin

CSTCS

MX0C2

(10)

Three-pin

20.00 to 25.00

CSACS

MX040

None

Two-pin

Three-pin

MB91121

(5) Power-on Reset

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

Power supply rising time

3.3 V

< 0.2 V

before the
power supply
rising

Power supply shut off time

OFF

Repeated
operations

Oscillation stabilizing time

OSC

300

0.2 V

0.9

RST

OFF

OSC

RSTL

A voltage rising rate of 50 mV/ms or
less is recommended.

Sudden change in supply voltage during operation may initiate a power-on sequence.
To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid
fluctuations in the supply voltage.

Note:

(Oscillation stabilizing time)

Note: Set RST pin to "L" level when turning on the device, at least the described above duration after the

supply voltage reaches Vcc is necessary before turning the RST to "H" level.

336 ms approx. (@12.5 MHz)

MB91121

(6) Normal Bus Access Read/write Operation

*1 : When bus timing is delayed by automatic wait insertion or RDY input, add (t

CYC

extended cycle number for

delay) to this rating.

*2 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively.

Equation : (2

CYC

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit Remarks

Min.

Max.

CS0 to CS5 delay time

CHCSL

CLK
CS0 to CS5

CHCSH

Address delay time

CHAV

CLK
A24 to A00

Data delay time

CHDV

CLK
D31 to D16

RD delay time

CLRL

CLK
RD

CLRH

WR0, WR1 delay time

CLWL

CLK
WR0, WR1

CLWH

Valid address

valid data input time

AVDV

A24 to A00
D31 to D16

CYC

*1
*2

valid data input time

RLDV

RD
D31 to D16

CYC

Data set up

time

DSRH

data hold time

RHDX

MB91121

(8) Hold Timing

Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin

name

Condition

Value

Unit

Remarks

Min.

Max.

BGRNT delay time

CHBGL

CLK
BGRNT

CHBGH

Pin floating

BGRNT

time

XHAL

BGRNT

CYC

BGRNT

pin valid time

HAHV

CYC

CHBGL

CHBGH

CYC

HAHV

XHAL

CLK

Each pin

High impedance

BRQ

BGRNT

MB91121

(9) Normal DRAM Mode Read/Write Cycle

*1 : When Q1 cycle or Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

*2 : Rating at a gear cycle of

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8,
respectively.

Equation : (3

CYC

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK
RAS

CHRAL

CAS delay time

CLCASL

CLK
CAS

CLCASH

ROW address delay time

CHRAV

CLK
A24 to A00

COLUMN address delay time

CHCAV

DW delay time

CHDWL

CLK
DW

CHDWH

Output data delay time

CHDV1

CLK
D31 to D16

RAS

valid data input time

RLDV

RAS
D31 to D16

CYC

*1
*2

CAS

valid data input time

CLDV

CAS
D31 to D16

CYC

CAS

data hold time

CADH

MB91121

(10) Normal DRAM Mode Fast Page Read/Write Cycle

* : When Q4 cycle is extended for 1 cycle, add t

CYC

time to this rating.

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH

CLK, RAS

CAS delay time

CLCASL

CLK
CAS

CLCASH

COLUMN address delay time

CHCAV

CLK
A24 to A00

DW delay time

CHDWH

CLK, DW

Output data delay time

CHDV1

CLK
D31 to D16

CAS

valid data input time

CLDV

CAS
D31 to D16

CYC

CAS

data hold time

CADH

MB91121

(11) Single DRAM Timing

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

RAS delay time

CLRAH2

CLK
RAS

CHRAL2

CAS delay time

CHCASL2

CLK
CAS

CYC

CHCASH2

ROW address delay time

CHRAV2

CLK
A24 to A00

COLUMN address delay time

CHCAV2

DW delay time

CHDWL2

CLK
DW

CHDWH2

Output data delay time

CHDV2

CLK
D31 to D16

CAS

Valid data input time

CLDV2

CAS
D31 to D16

CYC

CAS

data hold time

CADH2

MB91121

COLUMN-2

CHCASH2

CHRAL2

CHDWH2

CHDWL2

CHDV2

Q4S

CADH2

CLDV2

CHRAV2

CHCAV2

CHCASL2

CYC

CLRAH2

COLUMN-0

ROW address

COLUMN-1

Write-0

Write-1

Write-2

Read-1

Read-2

Read-0

D31 to D16

CLK

D31 to D16

RAS

CAS

A24 to A00

*1 : Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.

*2 :

indicates the timing when the bus cycle begins from the high spead page mode.

MB91121

(12) Hyper DRAM Timing

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit Remarks

Min.

Max.

RAS delay time

CLRAH3

CLK
RAS

CHRAL3

CAS delay time

CHCASL3

CLK
CAS

CYC

CHCASH3

ROW address delay time

CHRAV3

CLK
A24 to A00

COLUMN address delay time

CHCAV3

RD delay time

CHRL3

CLK
RD

CHRH3

CLRL3

DW delay time

CHDWL3

CLK
DW

CHDWH3

Output data delay time

CHDV3

CLK
D31 to D16

CAS

valid data input time

CLDV3

CAS
D31 to D16

CYC

CAS

data hold time

CADH3

MB91121

CHCASH3

CHRAL3

CHDWH3

CHDWL3

CHDV3

Q4H

CADH3

CLDV3

CHRAV3

CLRL3

CHRL3

CHCASL3

CYC

CLRAH3

COLUMN-0

COLUMN-1

COLUMN-2

CHRH3

CHCAV3

ROW address

Write-0

Write-1

Write-2

Read-1

Read-0

D31 to D16

CLK

D31 to D16

RAS

CAS

A24 to A00

*1 : Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle.

*2 :

indicates the timing when the bus cycle begins from the high spead page mode.

MB91121

(15) UART Timing

Note : This rating is for AC characteristics in CLK synchronous mode.

CYCP

is a cycle time of peripheral system clock

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

Serial clock cycle time

SCYC

Internal

shift clock

mode

CYCP

SCLK

SOUT delay time

SLOV

Valid SIN

SCLK

IVSH

100

SCLK

valid SIN hold time

SHIX

Serial clock "H" pulse width

SHSL

External

shift clock

mode

CYCP

Serial clock "L" pulse width

SLSH

CYCP

SCLK

SOUT delay time

SLOV

150

Valid SIN

SCLK

IVSH

SCLK

valid SIN hold time

SHIX

SCLK

SOUT

SIN

SCLK

SOUT

SIN

SCYC

SLOV

IVSH

SHIX

SLOV

SLSH

SHSL

IVSH

SHIX

· Internal shift clock mode

· External shift clock mode

MB91121

(17) DMA Controller Timing

3.0 V to 3.6 V, V

0.0 V, T

C to

Parameter

Symbol

Pin name

Condition

Value

Unit

Remarks

Min.

Max.

DREQ input pulse width

DRWH

DREQ0 to DREQ2

CYC

DACK delay time
(Normal bus)
(Normal DRAM)

CLDL

CLK
DACK0 to DACK2

CLDH

EOP delay time
(Normal bus)
(Normal DRAM)

CLEL

CLK
EOP0 to EOP2

CLEH

DACK delay time
(Single DRAM)
(Hyper DRAM)

CHDL

CLK
DACK0 to DACK2

CYC

CHDH

EOP delay time
(Single DRAM)
(Hyper DRAM)

CHEL

CLK
EOP0 to EOP2

CYC

CHEH

CLK

DREQ0 to DREQ2

DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)

DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)

CYC

DRWH

CLDL

CLEL

CHDL

CHEL

CLDH

CLEH

CHDH

MB91121

A/D Converter Block Electrical Characteristics

*1 : Machine clock

25 MHz

*2 : Current value for A/D converters not in operation, CPU stop mode (V

AVRH

3.3 V)

Note :

As the absolute value of AVRH decreases, relative error increases.

Output impedance of external circuit of analog input under following conditions;

Output impedance of external circuit < 5 k

If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling.

Analog input circuit example

AVRH

3.3 V, AV

0.0 V, T

C to

Parameter

Symbol

Pin name

Value

Unit

Min.

Typ.

Max.

Resolution

BIT

Total error

5.0

LSB

Linearity error

3.5

LSB

Differentiation linearity error

2.0

LSB

Zero transition voltage

AN0 to AN7

1.5

0.5

2.5

LSB

Full-scale transition voltage

FST

AN0 to AN7 AVRH

4.5 AVRH

1.5 AVRH

0.5 LSB

Conversion time

5.6*

Analog port input current

AIN

AN0 to AN7

0.1

Analog input voltage

AIN

AN0 to AN7

AVRH

Reference voltage

AVRH

Power supply current

Reference voltage supply current

AVRH

200

Conversion variance between channels

AN0 to AN7

LSB

ON1

0. 2 k

ON2

1. 4 k

ON3

1. 4 k

ON4

0. 2 k

16.6 pF

4.0 pF

ON2

ON3

ON4

Sample-and-hold circuit

Analog input

Comparator

Note : These values are given for reference purposes.

MB91121

A/D Converter Glossary

· Resolution

The smallest change in analog voltage detected by A/D converter.

· Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000
0000"

"00 0000 0001") to the full-scale transition point (between "11 1111 1110"

"11 1111 1111") .

· Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage.

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

{1 LSB

}

FST

AVRL

AVRH

1)T

Linearity error

Analog input

Actual conversion
characteristic

Ideal characteristic

(measured value)

(measured
value)

(measured value)

Differential linearity error

Analog input

Actual conversion

characteristic

Ideal characteristic

Actual conversion characteristic

(measured value)

Digital output

1 LSB =

[V]

FST

1022

Linearity error of digital output N =

{1 LSB

1) + V

}

1 LSB

: A voltage for causing transition of digital output from (000)

to (001)

[LSB]

Differential linearity error

of digital output N =

(N + 1)T

1 LSB

[LSB]

FST

: A voltage for causing transition of digital output from (3FE)

to (3FF)

: A voltage for causing transition of digital output from (N

to N

MB91121

· Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error, full-
scale transition error and linearity error.

3FF

3FE

3FD

004

003

002

001

AVRL

AVRH

1.5 LSB

0.5 LSB

{1 LSB

0.5 LSB}

: A voltage for causing transition of digital output from (N

1) to N

Total error

Analog input

Actual conversion
characteristic

(measured value)

Actual conversion
characteristic

Ideal characteristic

(ideal value) = AVRL + 0.5 LSB

[LSB]

(ideal value) = AVRL

1.5 LSB [V]

[V]

FST

Total error of digital output N =

{1 LSB

1) + 0.5 LSB}

1 LSB

Digital output

1 LSB (ideal value) =

[V]

AVRH

AVRL

1024

MB91121

FUJITSU LIMITED

For further information please contact:

Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608
Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220

http://www.fmap.com.sg/

F9909

FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).

CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91121PFV

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MB91121PFV